1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __MSM_DRM_H__ 8 #define __MSM_DRM_H__ 9 #include "drm.h" 10 #include "sde_drm.h" 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 #define MSM_PIPE_NONE 0x00 15 #define MSM_PIPE_2D0 0x01 16 #define MSM_PIPE_2D1 0x02 17 #define MSM_PIPE_3D0 0x10 18 #define MSM_PIPE_ID_MASK 0xffff 19 #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) 20 #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) 21 struct drm_msm_timespec { 22 __s64 tv_sec; 23 __s64 tv_nsec; 24 }; 25 #define DRM_EDID_CLRMETRY_xvYCC_601 (1 << 0) 26 #define DRM_EDID_CLRMETRY_xvYCC_709 (1 << 1) 27 #define DRM_EDID_CLRMETRY_sYCC_601 (1 << 2) 28 #define DRM_EDID_CLRMETRY_ADOBE_YCC_601 (1 << 3) 29 #define DRM_EDID_CLRMETRY_ADOBE_RGB (1 << 4) 30 #define DRM_EDID_CLRMETRY_BT2020_CYCC (1 << 5) 31 #define DRM_EDID_CLRMETRY_BT2020_YCC (1 << 6) 32 #define DRM_EDID_CLRMETRY_BT2020_RGB (1 << 7) 33 #define DRM_EDID_CLRMETRY_DCI_P3 (1 << 15) 34 #define HDR_PRIMARIES_COUNT 3 35 #define HDR_EOTF_SDR_LUM_RANGE 0x0 36 #define HDR_EOTF_HDR_LUM_RANGE 0x1 37 #define HDR_EOTF_SMTPE_ST2084 0x2 38 #define HDR_EOTF_HLG 0x3 39 #define DRM_MSM_EXT_HDR_METADATA 40 #define DRM_MSM_EXT_HDR_PLUS_METADATA 41 struct drm_msm_ext_hdr_metadata { 42 __u32 hdr_state; 43 __u32 eotf; 44 __u32 hdr_supported; 45 __u32 display_primaries_x[HDR_PRIMARIES_COUNT]; 46 __u32 display_primaries_y[HDR_PRIMARIES_COUNT]; 47 __u32 white_point_x; 48 __u32 white_point_y; 49 __u32 max_luminance; 50 __u32 min_luminance; 51 __u32 max_content_light_level; 52 __u32 max_average_light_level; 53 __u64 hdr_plus_payload; 54 __u32 hdr_plus_payload_size; 55 }; 56 #define DRM_MSM_EXT_HDR_PROPERTIES 57 #define DRM_MSM_EXT_HDR_PLUS_PROPERTIES 58 struct drm_msm_ext_hdr_properties { 59 __u8 hdr_metadata_type_one; 60 __u32 hdr_supported; 61 __u32 hdr_eotf; 62 __u32 hdr_max_luminance; 63 __u32 hdr_avg_luminance; 64 __u32 hdr_min_luminance; 65 __u32 hdr_plus_supported; 66 }; 67 #define MSM_PARAM_GPU_ID 0x01 68 #define MSM_PARAM_GMEM_SIZE 0x02 69 #define MSM_PARAM_CHIP_ID 0x03 70 #define MSM_PARAM_MAX_FREQ 0x04 71 #define MSM_PARAM_TIMESTAMP 0x05 72 #define MSM_PARAM_GMEM_BASE 0x06 73 #define MSM_PARAM_NR_RINGS 0x07 74 struct drm_msm_param { 75 __u32 pipe; 76 __u32 param; 77 __u64 value; 78 }; 79 #define MSM_BO_SCANOUT 0x00000001 80 #define MSM_BO_GPU_READONLY 0x00000002 81 #define MSM_BO_CACHE_MASK 0x000f0000 82 #define MSM_BO_CACHED 0x00010000 83 #define MSM_BO_WC 0x00020000 84 #define MSM_BO_UNCACHED 0x00040000 85 #define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED) 86 struct drm_msm_gem_new { 87 __u64 size; 88 __u32 flags; 89 __u32 handle; 90 }; 91 #define MSM_INFO_IOVA 0x01 92 #define MSM_INFO_FLAGS (MSM_INFO_IOVA) 93 struct drm_msm_gem_info { 94 __u32 handle; 95 __u32 flags; 96 __u64 offset; 97 }; 98 #define MSM_PREP_READ 0x01 99 #define MSM_PREP_WRITE 0x02 100 #define MSM_PREP_NOSYNC 0x04 101 #define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC) 102 struct drm_msm_gem_cpu_prep { 103 __u32 handle; 104 __u32 op; 105 struct drm_msm_timespec timeout; 106 }; 107 struct drm_msm_gem_cpu_fini { 108 __u32 handle; 109 }; 110 struct drm_msm_gem_submit_reloc { 111 __u32 submit_offset; 112 #ifdef __cplusplus 113 __u32 or_val; 114 #else 115 __u32 or; 116 #endif 117 __s32 shift; 118 __u32 reloc_idx; 119 __u64 reloc_offset; 120 }; 121 #define MSM_SUBMIT_CMD_BUF 0x0001 122 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 123 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 124 struct drm_msm_gem_submit_cmd { 125 __u32 type; 126 __u32 submit_idx; 127 __u32 submit_offset; 128 __u32 size; 129 __u32 pad; 130 __u32 nr_relocs; 131 __u64 relocs; 132 }; 133 #define MSM_SUBMIT_BO_READ 0x0001 134 #define MSM_SUBMIT_BO_WRITE 0x0002 135 #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE) 136 struct drm_msm_gem_submit_bo { 137 __u32 flags; 138 __u32 handle; 139 __u64 presumed; 140 }; 141 #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 142 #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 143 #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 144 #define MSM_SUBMIT_SUDO 0x10000000 145 #define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | 0) 146 struct drm_msm_gem_submit { 147 __u32 flags; 148 __u32 fence; 149 __u32 nr_bos; 150 __u32 nr_cmds; 151 __u64 bos; 152 __u64 cmds; 153 __s32 fence_fd; 154 __u32 queueid; 155 }; 156 struct drm_msm_wait_fence { 157 __u32 fence; 158 __u32 pad; 159 struct drm_msm_timespec timeout; 160 __u32 queueid; 161 }; 162 #define MSM_MADV_WILLNEED 0 163 #define MSM_MADV_DONTNEED 1 164 #define __MSM_MADV_PURGED 2 165 struct drm_msm_gem_madvise { 166 __u32 handle; 167 __u32 madv; 168 __u32 retained; 169 }; 170 #define DISPLAY_PRIMARIES_WX 0 171 #define DISPLAY_PRIMARIES_WY 1 172 #define DISPLAY_PRIMARIES_RX 2 173 #define DISPLAY_PRIMARIES_RY 3 174 #define DISPLAY_PRIMARIES_GX 4 175 #define DISPLAY_PRIMARIES_GY 5 176 #define DISPLAY_PRIMARIES_BX 6 177 #define DISPLAY_PRIMARIES_BY 7 178 #define DISPLAY_PRIMARIES_MAX 8 179 struct drm_panel_hdr_properties { 180 __u32 hdr_enabled; 181 __u32 display_primaries[DISPLAY_PRIMARIES_MAX]; 182 __u32 peak_brightness; 183 __u32 blackness_level; 184 }; 185 struct drm_msm_event_req { 186 __u32 object_id; 187 __u32 object_type; 188 __u32 event; 189 __u64 client_context; 190 __u32 index; 191 }; 192 struct drm_msm_event_resp { 193 struct drm_event base; 194 struct drm_msm_event_req info; 195 __u8 data[]; 196 }; 197 #define MSM_SUBMITQUEUE_FLAGS (0) 198 struct drm_msm_submitqueue { 199 __u32 flags; 200 __u32 prio; 201 __u32 id; 202 }; 203 struct drm_msm_power_ctrl { 204 __u32 enable; 205 __u32 flags; 206 }; 207 #define DRM_MSM_GET_PARAM 0x00 208 #define DRM_MSM_GEM_NEW 0x02 209 #define DRM_MSM_GEM_INFO 0x03 210 #define DRM_MSM_GEM_CPU_PREP 0x04 211 #define DRM_MSM_GEM_CPU_FINI 0x05 212 #define DRM_MSM_GEM_SUBMIT 0x06 213 #define DRM_MSM_WAIT_FENCE 0x07 214 #define DRM_MSM_GEM_MADVISE 0x08 215 #define DRM_MSM_SUBMITQUEUE_NEW 0x0A 216 #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B 217 #define DRM_SDE_WB_CONFIG 0x40 218 #define DRM_MSM_REGISTER_EVENT 0x41 219 #define DRM_MSM_DEREGISTER_EVENT 0x42 220 #define DRM_MSM_RMFB2 0x43 221 #define DRM_MSM_POWER_CTRL 0x44 222 #define DRM_EVENT_HISTOGRAM 0x80000000 223 #define DRM_EVENT_AD_BACKLIGHT 0x80000001 224 #define DRM_EVENT_CRTC_POWER 0x80000002 225 #define DRM_EVENT_SYS_BACKLIGHT 0x80000003 226 #define DRM_EVENT_SDE_POWER 0x80000004 227 #define DRM_EVENT_IDLE_NOTIFY 0x80000005 228 #define DRM_EVENT_PANEL_DEAD 0x80000006 229 #define DRM_EVENT_SDE_HW_RECOVERY 0X80000007 230 #define DRM_EVENT_LTM_HIST 0X80000008 231 #define DRM_EVENT_LTM_WB_PB 0X80000009 232 #define DRM_EVENT_LTM_OFF 0X8000000A 233 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 234 #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 235 #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info) 236 #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep) 237 #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 238 #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 239 #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 240 #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise) 241 #define DRM_IOCTL_SDE_WB_CONFIG DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg) 242 #define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req) 243 #define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req) 244 #define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_RMFB2), unsigned int) 245 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue) 246 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32) 247 #define DRM_IOCTL_MSM_POWER_CTRL DRM_IOW((DRM_COMMAND_BASE + DRM_MSM_POWER_CTRL), struct drm_msm_power_ctrl) 248 #ifdef __cplusplus 249 } 250 #endif 251 #endif 252