1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef IPA_QMI_SERVICE_V01_H 8 #define IPA_QMI_SERVICE_V01_H 9 #include <linux/types.h> 10 #define QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01 6 11 #define QMI_IPA_MAX_FILTERS_EX_V01 128 12 #define QMI_IPA_MAX_FILTERS_EX2_V01 256 13 #define QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01 2 14 #define QMI_IPA_MAX_FILTERS_V01 64 15 #define QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01 2 16 #define QMI_IPA_ENDP_DESC_NUM_MAX_V01 31 17 #define QMI_IPA_MAX_APN_V01 8 18 #define QMI_IPA_MAX_CLIENT_DST_PIPES_V01 8 19 #define QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01 2 20 #define QMI_IPA_MAX_UL_FIREWALL_RULES_V01 64 21 #define QMI_IPA_REMOTE_MHI_MEMORY_MAPPING_NUM_MAX_V01 6 22 #define QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01 2 23 #define QMI_IPA_MAX_PIPES_V01 20 24 #define QMI_IPA_MAX_PER_CLIENTS_V01 64 25 #define IPA_QMI_SUPPORTS_STATS 26 #define IPA_QMI_SUPPORT_MHI_DEFAULT 27 #define IPA_INT_MAX ((int) (~0U >> 1)) 28 #define IPA_INT_MIN (- IPA_INT_MAX - 1) 29 enum ipa_qmi_result_type_v01 { 30 IPA_QMI_RESULT_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, 31 IPA_QMI_RESULT_SUCCESS_V01 = 0, 32 IPA_QMI_RESULT_FAILURE_V01 = 1, 33 IPA_QMI_RESULT_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, 34 }; 35 enum ipa_qmi_error_type_v01 { 36 IPA_QMI_ERROR_TYPE_MIN_ENUM_VAL_V01 = IPA_INT_MIN, 37 IPA_QMI_ERR_NONE_V01 = 0x0000, 38 IPA_QMI_ERR_MALFORMED_MSG_V01 = 0x0001, 39 IPA_QMI_ERR_NO_MEMORY_V01 = 0x0002, 40 IPA_QMI_ERR_INTERNAL_V01 = 0x0003, 41 IPA_QMI_ERR_CLIENT_IDS_EXHAUSTED_V01 = 0x0005, 42 IPA_QMI_ERR_INVALID_ID_V01 = 0x0029, 43 IPA_QMI_ERR_ENCODING_V01 = 0x003A, 44 IPA_QMI_ERR_INCOMPATIBLE_STATE_V01 = 0x005A, 45 IPA_QMI_ERR_NOT_SUPPORTED_V01 = 0x005E, 46 IPA_QMI_ERROR_TYPE_MAX_ENUM_VAL_V01 = IPA_INT_MAX, 47 }; 48 struct ipa_qmi_response_type_v01 { 49 uint16_t result; 50 uint16_t error; 51 }; 52 enum ipa_platform_type_enum_v01 { 53 IPA_PLATFORM_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 54 QMI_IPA_PLATFORM_TYPE_INVALID_V01 = 0, 55 QMI_IPA_PLATFORM_TYPE_TN_V01 = 1, 56 QMI_IPA_PLATFORM_TYPE_LE_V01 = 2, 57 QMI_IPA_PLATFORM_TYPE_MSM_ANDROID_V01 = 3, 58 QMI_IPA_PLATFORM_TYPE_MSM_WINDOWS_V01 = 4, 59 QMI_IPA_PLATFORM_TYPE_MSM_QNX_V01 = 5, 60 QMI_IPA_PLATFORM_TYPE_LE_MHI_V01 = 6, 61 IPA_PLATFORM_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 62 }; 63 #define QMI_IPA_PLATFORM_TYPE_LE_MHI_V01 QMI_IPA_PLATFORM_TYPE_LE_MHI_V01 64 struct ipa_hdr_tbl_info_type_v01 { 65 uint32_t modem_offset_start; 66 uint32_t modem_offset_end; 67 }; 68 struct ipa_route_tbl_info_type_v01 { 69 uint32_t route_tbl_start_addr; 70 uint32_t num_indices; 71 }; 72 struct ipa_modem_mem_info_type_v01 { 73 uint32_t block_start_addr; 74 uint32_t size; 75 }; 76 struct ipa_hdr_proc_ctx_tbl_info_type_v01 { 77 uint32_t modem_offset_start; 78 uint32_t modem_offset_end; 79 }; 80 struct ipa_zip_tbl_info_type_v01 { 81 uint32_t modem_offset_start; 82 uint32_t modem_offset_end; 83 }; 84 struct ipa_init_modem_driver_req_msg_v01 { 85 uint8_t platform_type_valid; 86 enum ipa_platform_type_enum_v01 platform_type; 87 uint8_t hdr_tbl_info_valid; 88 struct ipa_hdr_tbl_info_type_v01 hdr_tbl_info; 89 uint8_t v4_route_tbl_info_valid; 90 struct ipa_route_tbl_info_type_v01 v4_route_tbl_info; 91 uint8_t v6_route_tbl_info_valid; 92 struct ipa_route_tbl_info_type_v01 v6_route_tbl_info; 93 uint8_t v4_filter_tbl_start_addr_valid; 94 uint32_t v4_filter_tbl_start_addr; 95 uint8_t v6_filter_tbl_start_addr_valid; 96 uint32_t v6_filter_tbl_start_addr; 97 uint8_t modem_mem_info_valid; 98 struct ipa_modem_mem_info_type_v01 modem_mem_info; 99 uint8_t ctrl_comm_dest_end_pt_valid; 100 uint32_t ctrl_comm_dest_end_pt; 101 uint8_t is_ssr_bootup_valid; 102 uint8_t is_ssr_bootup; 103 uint8_t hdr_proc_ctx_tbl_info_valid; 104 struct ipa_hdr_proc_ctx_tbl_info_type_v01 hdr_proc_ctx_tbl_info; 105 uint8_t zip_tbl_info_valid; 106 struct ipa_zip_tbl_info_type_v01 zip_tbl_info; 107 uint8_t v4_hash_route_tbl_info_valid; 108 struct ipa_route_tbl_info_type_v01 v4_hash_route_tbl_info; 109 uint8_t v6_hash_route_tbl_info_valid; 110 struct ipa_route_tbl_info_type_v01 v6_hash_route_tbl_info; 111 uint8_t v4_hash_filter_tbl_start_addr_valid; 112 uint32_t v4_hash_filter_tbl_start_addr; 113 uint8_t v6_hash_filter_tbl_start_addr_valid; 114 uint32_t v6_hash_filter_tbl_start_addr; 115 uint8_t hw_stats_quota_base_addr_valid; 116 uint32_t hw_stats_quota_base_addr; 117 uint8_t hw_stats_quota_size_valid; 118 uint32_t hw_stats_quota_size; 119 uint8_t hw_drop_stats_base_addr_valid; 120 uint32_t hw_drop_stats_base_addr; 121 uint8_t hw_drop_stats_table_size_valid; 122 uint32_t hw_drop_stats_table_size; 123 }; 124 struct ipa_init_modem_driver_resp_msg_v01 { 125 struct ipa_qmi_response_type_v01 resp; 126 uint8_t ctrl_comm_dest_end_pt_valid; 127 uint32_t ctrl_comm_dest_end_pt; 128 uint8_t default_end_pt_valid; 129 uint32_t default_end_pt; 130 uint8_t modem_driver_init_pending_valid; 131 uint8_t modem_driver_init_pending; 132 }; 133 struct ipa_init_modem_driver_cmplt_req_msg_v01 { 134 uint8_t status; 135 }; 136 struct ipa_init_modem_driver_cmplt_resp_msg_v01 { 137 struct ipa_qmi_response_type_v01 resp; 138 }; 139 struct ipa_indication_reg_req_msg_v01 { 140 uint8_t master_driver_init_complete_valid; 141 uint8_t master_driver_init_complete; 142 uint8_t data_usage_quota_reached_valid; 143 uint8_t data_usage_quota_reached; 144 uint8_t ipa_mhi_ready_ind_valid; 145 uint8_t ipa_mhi_ready_ind; 146 uint8_t endpoint_desc_ind_valid; 147 uint8_t endpoint_desc_ind; 148 uint8_t bw_change_ind_valid; 149 uint8_t bw_change_ind; 150 }; 151 struct ipa_indication_reg_resp_msg_v01 { 152 struct ipa_qmi_response_type_v01 resp; 153 }; 154 struct ipa_master_driver_init_complt_ind_msg_v01 { 155 struct ipa_qmi_response_type_v01 master_driver_init_status; 156 }; 157 struct ipa_ipfltr_range_eq_16_type_v01 { 158 uint8_t offset; 159 uint16_t range_low; 160 uint16_t range_high; 161 }; 162 struct ipa_ipfltr_mask_eq_32_type_v01 { 163 uint8_t offset; 164 uint32_t mask; 165 uint32_t value; 166 }; 167 struct ipa_ipfltr_eq_16_type_v01 { 168 uint8_t offset; 169 uint16_t value; 170 }; 171 struct ipa_ipfltr_eq_32_type_v01 { 172 uint8_t offset; 173 uint32_t value; 174 }; 175 struct ipa_ipfltr_mask_eq_128_type_v01 { 176 uint8_t offset; 177 uint8_t mask[16]; 178 uint8_t value[16]; 179 }; 180 struct ipa_filter_rule_type_v01 { 181 uint16_t rule_eq_bitmap; 182 uint8_t tos_eq_present; 183 uint8_t tos_eq; 184 uint8_t protocol_eq_present; 185 uint8_t protocol_eq; 186 uint8_t num_ihl_offset_range_16; 187 struct ipa_ipfltr_range_eq_16_type_v01 ihl_offset_range_16[QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01]; 188 uint8_t num_offset_meq_32; 189 struct ipa_ipfltr_mask_eq_32_type_v01 offset_meq_32[QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01]; 190 uint8_t tc_eq_present; 191 uint8_t tc_eq; 192 uint8_t flow_eq_present; 193 uint32_t flow_eq; 194 uint8_t ihl_offset_eq_16_present; 195 struct ipa_ipfltr_eq_16_type_v01 ihl_offset_eq_16; 196 uint8_t ihl_offset_eq_32_present; 197 struct ipa_ipfltr_eq_32_type_v01 ihl_offset_eq_32; 198 uint8_t num_ihl_offset_meq_32; 199 struct ipa_ipfltr_mask_eq_32_type_v01 ihl_offset_meq_32[QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01]; 200 uint8_t num_offset_meq_128; 201 struct ipa_ipfltr_mask_eq_128_type_v01 offset_meq_128[QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01]; 202 uint8_t metadata_meq32_present; 203 struct ipa_ipfltr_mask_eq_32_type_v01 metadata_meq32; 204 uint8_t ipv4_frag_eq_present; 205 }; 206 struct ipa_filter_rule_req2_type_v01 { 207 uint16_t rule_eq_bitmap; 208 uint8_t pure_ack_eq_present; 209 uint8_t pure_ack_eq; 210 uint8_t protocol_eq_present; 211 uint8_t protocol_eq; 212 uint8_t num_ihl_offset_range_16; 213 struct ipa_ipfltr_range_eq_16_type_v01 ihl_offset_range_16[QMI_IPA_IPFLTR_NUM_IHL_RANGE_16_EQNS_V01]; 214 uint8_t num_offset_meq_32; 215 struct ipa_ipfltr_mask_eq_32_type_v01 offset_meq_32[QMI_IPA_IPFLTR_NUM_MEQ_32_EQNS_V01]; 216 uint8_t tc_eq_present; 217 uint8_t tc_eq; 218 uint8_t flow_eq_present; 219 uint32_t flow_eq; 220 uint8_t ihl_offset_eq_16_present; 221 struct ipa_ipfltr_eq_16_type_v01 ihl_offset_eq_16; 222 uint8_t ihl_offset_eq_32_present; 223 struct ipa_ipfltr_eq_32_type_v01 ihl_offset_eq_32; 224 uint8_t num_ihl_offset_meq_32; 225 struct ipa_ipfltr_mask_eq_32_type_v01 ihl_offset_meq_32[QMI_IPA_IPFLTR_NUM_IHL_MEQ_32_EQNS_V01]; 226 uint8_t num_offset_meq_128; 227 struct ipa_ipfltr_mask_eq_128_type_v01 offset_meq_128[QMI_IPA_IPFLTR_NUM_MEQ_128_EQNS_V01]; 228 uint8_t metadata_meq32_present; 229 struct ipa_ipfltr_mask_eq_32_type_v01 metadata_meq32; 230 uint8_t ipv4_frag_eq_present; 231 }; 232 enum ipa_ip_type_enum_v01 { 233 IPA_IP_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 234 QMI_IPA_IP_TYPE_INVALID_V01 = 0, 235 QMI_IPA_IP_TYPE_V4_V01 = 1, 236 QMI_IPA_IP_TYPE_V6_V01 = 2, 237 QMI_IPA_IP_TYPE_V4V6_V01 = 3, 238 IPA_IP_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 239 }; 240 enum ipa_filter_action_enum_v01 { 241 IPA_FILTER_ACTION_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 242 QMI_IPA_FILTER_ACTION_INVALID_V01 = 0, 243 QMI_IPA_FILTER_ACTION_SRC_NAT_V01 = 1, 244 QMI_IPA_FILTER_ACTION_DST_NAT_V01 = 2, 245 QMI_IPA_FILTER_ACTION_ROUTING_V01 = 3, 246 QMI_IPA_FILTER_ACTION_EXCEPTION_V01 = 4, 247 IPA_FILTER_ACTION_ENUM_MAX_ENUM_VAL_V01 = 2147483647 248 }; 249 struct ipa_filter_spec_type_v01 { 250 uint32_t filter_spec_identifier; 251 enum ipa_ip_type_enum_v01 ip_type; 252 struct ipa_filter_rule_type_v01 filter_rule; 253 enum ipa_filter_action_enum_v01 filter_action; 254 uint8_t is_routing_table_index_valid; 255 uint32_t route_table_index; 256 uint8_t is_mux_id_valid; 257 uint32_t mux_id; 258 }; 259 struct ipa_filter_spec_ex_type_v01 { 260 enum ipa_ip_type_enum_v01 ip_type; 261 struct ipa_filter_rule_type_v01 filter_rule; 262 enum ipa_filter_action_enum_v01 filter_action; 263 uint8_t is_routing_table_index_valid; 264 uint32_t route_table_index; 265 uint8_t is_mux_id_valid; 266 uint32_t mux_id; 267 uint32_t rule_id; 268 uint8_t is_rule_hashable; 269 }; 270 struct ipa_filter_spec_ex2_type_v01 { 271 enum ipa_ip_type_enum_v01 ip_type; 272 struct ipa_filter_rule_req2_type_v01 filter_rule; 273 enum ipa_filter_action_enum_v01 filter_action; 274 uint8_t is_routing_table_index_valid; 275 uint32_t route_table_index; 276 uint8_t is_mux_id_valid; 277 uint32_t mux_id; 278 uint32_t rule_id; 279 uint8_t is_rule_hashable; 280 }; 281 struct ipa_install_fltr_rule_req_msg_v01 { 282 uint8_t filter_spec_list_valid; 283 uint32_t filter_spec_list_len; 284 struct ipa_filter_spec_type_v01 filter_spec_list[QMI_IPA_MAX_FILTERS_V01]; 285 uint8_t source_pipe_index_valid; 286 uint32_t source_pipe_index; 287 uint8_t num_ipv4_filters_valid; 288 uint32_t num_ipv4_filters; 289 uint8_t num_ipv6_filters_valid; 290 uint32_t num_ipv6_filters; 291 uint8_t xlat_filter_indices_list_valid; 292 uint32_t xlat_filter_indices_list_len; 293 uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_V01]; 294 uint8_t filter_spec_ex_list_valid; 295 uint32_t filter_spec_ex_list_len; 296 struct ipa_filter_spec_ex_type_v01 filter_spec_ex_list[QMI_IPA_MAX_FILTERS_V01]; 297 uint8_t filter_spec_ex2_list_valid; 298 uint32_t filter_spec_ex2_list_len; 299 struct ipa_filter_spec_ex2_type_v01 filter_spec_ex2_list[QMI_IPA_MAX_FILTERS_V01]; 300 uint8_t ul_firewall_indices_list_valid; 301 uint32_t ul_firewall_indices_list_len; 302 uint32_t ul_firewall_indices_list[QMI_IPA_MAX_FILTERS_V01]; 303 }; 304 struct ipa_filter_rule_identifier_to_handle_map_v01 { 305 uint32_t filter_spec_identifier; 306 uint32_t filter_handle; 307 }; 308 struct ipa_install_fltr_rule_resp_msg_v01 { 309 struct ipa_qmi_response_type_v01 resp; 310 uint8_t filter_handle_list_valid; 311 uint32_t filter_handle_list_len; 312 struct ipa_filter_rule_identifier_to_handle_map_v01 filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; 313 uint8_t rule_id_valid; 314 uint32_t rule_id_len; 315 uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01]; 316 }; 317 struct ipa_filter_handle_to_index_map_v01 { 318 uint32_t filter_handle; 319 uint32_t filter_index; 320 }; 321 struct ipa_fltr_installed_notif_req_msg_v01 { 322 uint32_t source_pipe_index; 323 enum ipa_qmi_result_type_v01 install_status; 324 uint32_t filter_index_list_len; 325 struct ipa_filter_handle_to_index_map_v01 filter_index_list[QMI_IPA_MAX_FILTERS_V01]; 326 uint8_t embedded_pipe_index_valid; 327 uint32_t embedded_pipe_index; 328 uint8_t retain_header_valid; 329 uint8_t retain_header; 330 uint8_t embedded_call_mux_id_valid; 331 uint32_t embedded_call_mux_id; 332 uint8_t num_ipv4_filters_valid; 333 uint32_t num_ipv4_filters; 334 uint8_t num_ipv6_filters_valid; 335 uint32_t num_ipv6_filters; 336 uint8_t start_ipv4_filter_idx_valid; 337 uint32_t start_ipv4_filter_idx; 338 uint8_t start_ipv6_filter_idx_valid; 339 uint32_t start_ipv6_filter_idx; 340 uint8_t rule_id_valid; 341 uint32_t rule_id_len; 342 uint32_t rule_id[QMI_IPA_MAX_FILTERS_V01]; 343 uint8_t dst_pipe_id_valid; 344 uint32_t dst_pipe_id_len; 345 uint32_t dst_pipe_id[QMI_IPA_MAX_CLIENT_DST_PIPES_V01]; 346 uint8_t rule_id_ex_valid; 347 uint32_t rule_id_ex_len; 348 uint32_t rule_id_ex[QMI_IPA_MAX_FILTERS_EX2_V01]; 349 }; 350 struct ipa_fltr_installed_notif_resp_msg_v01 { 351 struct ipa_qmi_response_type_v01 resp; 352 }; 353 struct ipa_enable_force_clear_datapath_req_msg_v01 { 354 uint32_t source_pipe_bitmask; 355 uint32_t request_id; 356 uint8_t throttle_source_valid; 357 uint8_t throttle_source; 358 }; 359 struct ipa_enable_force_clear_datapath_resp_msg_v01 { 360 struct ipa_qmi_response_type_v01 resp; 361 }; 362 struct ipa_disable_force_clear_datapath_req_msg_v01 { 363 uint32_t request_id; 364 }; 365 struct ipa_disable_force_clear_datapath_resp_msg_v01 { 366 struct ipa_qmi_response_type_v01 resp; 367 }; 368 enum ipa_peripheral_speed_enum_v01 { 369 IPA_PERIPHERAL_SPEED_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 370 QMI_IPA_PER_USB_FS_V01 = 1, 371 QMI_IPA_PER_USB_HS_V01 = 2, 372 QMI_IPA_PER_USB_SS_V01 = 3, 373 QMI_IPA_PER_WLAN_V01 = 4, 374 IPA_PERIPHERAL_SPEED_ENUM_MAX_ENUM_VAL_V01 = 2147483647 375 }; 376 enum ipa_pipe_mode_enum_v01 { 377 IPA_PIPE_MODE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 378 QMI_IPA_PIPE_MODE_HW_V01 = 1, 379 QMI_IPA_PIPE_MODE_SW_V01 = 2, 380 IPA_PIPE_MODE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 381 }; 382 enum ipa_peripheral_type_enum_v01 { 383 IPA_PERIPHERAL_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 384 QMI_IPA_PERIPHERAL_USB_V01 = 1, 385 QMI_IPA_PERIPHERAL_HSIC_V01 = 2, 386 QMI_IPA_PERIPHERAL_PCIE_V01 = 3, 387 IPA_PERIPHERAL_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 388 }; 389 struct ipa_config_req_msg_v01 { 390 uint8_t peripheral_type_valid; 391 enum ipa_peripheral_type_enum_v01 peripheral_type; 392 uint8_t hw_deaggr_supported_valid; 393 uint8_t hw_deaggr_supported; 394 uint8_t max_aggr_frame_size_valid; 395 uint32_t max_aggr_frame_size; 396 uint8_t ipa_ingress_pipe_mode_valid; 397 enum ipa_pipe_mode_enum_v01 ipa_ingress_pipe_mode; 398 uint8_t peripheral_speed_info_valid; 399 enum ipa_peripheral_speed_enum_v01 peripheral_speed_info; 400 uint8_t dl_accumulation_time_limit_valid; 401 uint32_t dl_accumulation_time_limit; 402 uint8_t dl_accumulation_pkt_limit_valid; 403 uint32_t dl_accumulation_pkt_limit; 404 uint8_t dl_accumulation_byte_limit_valid; 405 uint32_t dl_accumulation_byte_limit; 406 uint8_t ul_accumulation_time_limit_valid; 407 uint32_t ul_accumulation_time_limit; 408 uint8_t hw_control_flags_valid; 409 uint32_t hw_control_flags; 410 uint8_t ul_msi_event_threshold_valid; 411 uint32_t ul_msi_event_threshold; 412 uint8_t dl_msi_event_threshold_valid; 413 uint32_t dl_msi_event_threshold; 414 uint8_t ul_fifo_size_valid; 415 uint32_t ul_fifo_size; 416 uint8_t dl_fifo_size_valid; 417 uint32_t dl_fifo_size; 418 uint8_t dl_buf_size_valid; 419 uint32_t dl_buf_size; 420 }; 421 struct ipa_config_resp_msg_v01 { 422 struct ipa_qmi_response_type_v01 resp; 423 }; 424 enum ipa_stats_type_enum_v01 { 425 IPA_STATS_TYPE_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 426 QMI_IPA_STATS_TYPE_INVALID_V01 = 0, 427 QMI_IPA_STATS_TYPE_PIPE_V01 = 1, 428 QMI_IPA_STATS_TYPE_FILTER_RULES_V01 = 2, 429 IPA_STATS_TYPE_ENUM_MAX_ENUM_VAL_V01 = 2147483647 430 }; 431 struct ipa_pipe_stats_info_type_v01 { 432 uint32_t pipe_index; 433 uint64_t num_ipv4_packets; 434 uint64_t num_ipv4_bytes; 435 uint64_t num_ipv6_packets; 436 uint64_t num_ipv6_bytes; 437 }; 438 struct ipa_stats_type_filter_rule_v01 { 439 uint32_t filter_rule_index; 440 uint64_t num_packets; 441 }; 442 struct ipa_get_data_stats_req_msg_v01 { 443 enum ipa_stats_type_enum_v01 ipa_stats_type; 444 uint8_t reset_stats_valid; 445 uint8_t reset_stats; 446 }; 447 struct ipa_get_data_stats_resp_msg_v01 { 448 struct ipa_qmi_response_type_v01 resp; 449 uint8_t ipa_stats_type_valid; 450 enum ipa_stats_type_enum_v01 ipa_stats_type; 451 uint8_t ul_src_pipe_stats_list_valid; 452 uint32_t ul_src_pipe_stats_list_len; 453 struct ipa_pipe_stats_info_type_v01 ul_src_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; 454 uint8_t dl_dst_pipe_stats_list_valid; 455 uint32_t dl_dst_pipe_stats_list_len; 456 struct ipa_pipe_stats_info_type_v01 dl_dst_pipe_stats_list[QMI_IPA_MAX_PIPES_V01]; 457 uint8_t dl_filter_rule_stats_list_valid; 458 uint32_t dl_filter_rule_stats_list_len; 459 struct ipa_stats_type_filter_rule_v01 dl_filter_rule_stats_list[QMI_IPA_MAX_FILTERS_V01]; 460 }; 461 struct ipa_apn_data_stats_info_type_v01 { 462 uint32_t mux_id; 463 uint64_t num_ul_packets; 464 uint64_t num_ul_bytes; 465 uint64_t num_dl_packets; 466 uint64_t num_dl_bytes; 467 }; 468 struct ipa_get_apn_data_stats_req_msg_v01 { 469 uint8_t mux_id_list_valid; 470 uint32_t mux_id_list_len; 471 uint32_t mux_id_list[QMI_IPA_MAX_APN_V01]; 472 }; 473 struct ipa_get_apn_data_stats_resp_msg_v01 { 474 struct ipa_qmi_response_type_v01 resp; 475 uint8_t apn_data_stats_list_valid; 476 uint32_t apn_data_stats_list_len; 477 struct ipa_apn_data_stats_info_type_v01 apn_data_stats_list[QMI_IPA_MAX_APN_V01]; 478 }; 479 struct ipa_data_usage_quota_info_type_v01 { 480 uint32_t mux_id; 481 uint64_t num_Mbytes; 482 }; 483 struct ipa_set_data_usage_quota_req_msg_v01 { 484 uint8_t apn_quota_list_valid; 485 uint32_t apn_quota_list_len; 486 struct ipa_data_usage_quota_info_type_v01 apn_quota_list[QMI_IPA_MAX_APN_V01]; 487 }; 488 struct ipa_set_data_usage_quota_resp_msg_v01 { 489 struct ipa_qmi_response_type_v01 resp; 490 }; 491 struct ipa_data_usage_quota_reached_ind_msg_v01 { 492 struct ipa_data_usage_quota_info_type_v01 apn; 493 }; 494 struct ipa_stop_data_usage_quota_req_msg_v01 { 495 char __placeholder; 496 }; 497 struct ipa_stop_data_usage_quota_resp_msg_v01 { 498 struct ipa_qmi_response_type_v01 resp; 499 }; 500 struct ipa_install_fltr_rule_req_ex_msg_v01 { 501 uint8_t filter_spec_ex_list_valid; 502 uint32_t filter_spec_ex_list_len; 503 struct ipa_filter_spec_ex_type_v01 filter_spec_ex_list[QMI_IPA_MAX_FILTERS_EX_V01]; 504 uint8_t source_pipe_index_valid; 505 uint32_t source_pipe_index; 506 uint8_t num_ipv4_filters_valid; 507 uint32_t num_ipv4_filters; 508 uint8_t num_ipv6_filters_valid; 509 uint32_t num_ipv6_filters; 510 uint8_t xlat_filter_indices_list_valid; 511 uint32_t xlat_filter_indices_list_len; 512 uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_EX_V01]; 513 uint8_t filter_spec_ex2_list_valid; 514 uint32_t filter_spec_ex2_list_len; 515 struct ipa_filter_spec_ex2_type_v01 filter_spec_ex2_list[QMI_IPA_MAX_FILTERS_V01]; 516 uint8_t ul_firewall_indices_list_valid; 517 uint32_t ul_firewall_indices_list_len; 518 uint32_t ul_firewall_indices_list[QMI_IPA_MAX_FILTERS_V01]; 519 }; 520 struct ipa_install_fltr_rule_resp_ex_msg_v01 { 521 struct ipa_qmi_response_type_v01 resp; 522 uint8_t rule_id_valid; 523 uint32_t rule_id_len; 524 uint32_t rule_id[QMI_IPA_MAX_FILTERS_EX_V01]; 525 }; 526 struct ipa_enable_per_client_stats_req_msg_v01 { 527 uint8_t enable_per_client_stats; 528 }; 529 struct ipa_enable_per_client_stats_resp_msg_v01 { 530 struct ipa_qmi_response_type_v01 resp; 531 }; 532 struct ipa_per_client_stats_info_type_v01 { 533 uint32_t client_id; 534 uint32_t src_pipe_id; 535 uint64_t num_ul_ipv4_bytes; 536 uint64_t num_ul_ipv6_bytes; 537 uint64_t num_dl_ipv4_bytes; 538 uint64_t num_dl_ipv6_bytes; 539 uint32_t num_ul_ipv4_pkts; 540 uint32_t num_ul_ipv6_pkts; 541 uint32_t num_dl_ipv4_pkts; 542 uint32_t num_dl_ipv6_pkts; 543 }; 544 struct ipa_get_stats_per_client_req_msg_v01 { 545 uint32_t client_id; 546 uint32_t src_pipe_id; 547 uint8_t reset_stats_valid; 548 uint8_t reset_stats; 549 }; 550 struct ipa_get_stats_per_client_resp_msg_v01 { 551 struct ipa_qmi_response_type_v01 resp; 552 uint8_t per_client_stats_list_valid; 553 uint32_t per_client_stats_list_len; 554 struct ipa_per_client_stats_info_type_v01 per_client_stats_list[QMI_IPA_MAX_PER_CLIENTS_V01]; 555 }; 556 struct ipa_ul_firewall_rule_type_v01 { 557 enum ipa_ip_type_enum_v01 ip_type; 558 struct ipa_filter_rule_type_v01 filter_rule; 559 }; 560 struct ipa_configure_ul_firewall_rules_req_msg_v01 { 561 uint32_t firewall_rules_list_len; 562 struct ipa_ul_firewall_rule_type_v01 firewall_rules_list[QMI_IPA_MAX_UL_FIREWALL_RULES_V01]; 563 uint32_t mux_id; 564 uint8_t disable_valid; 565 uint8_t disable; 566 uint8_t are_blacklist_filters_valid; 567 uint8_t are_blacklist_filters; 568 }; 569 struct ipa_configure_ul_firewall_rules_resp_msg_v01 { 570 struct ipa_qmi_response_type_v01 resp; 571 }; 572 enum ipa_ul_firewall_status_enum_v01 { 573 IPA_UL_FIREWALL_STATUS_ENUM_MIN_ENUM_VAL_V01 = - 2147483647, 574 QMI_IPA_UL_FIREWALL_STATUS_SUCCESS_V01 = 0, 575 QMI_IPA_UL_FIREWALL_STATUS_FAILURE_V01 = 1, 576 IPA_UL_FIREWALL_STATUS_ENUM_MAX_ENUM_VAL_V01 = 2147483647 577 }; 578 struct ipa_ul_firewall_config_result_type_v01 { 579 enum ipa_ul_firewall_status_enum_v01 is_success; 580 uint32_t mux_id; 581 }; 582 struct ipa_configure_ul_firewall_rules_ind_msg_v01 { 583 struct ipa_ul_firewall_config_result_type_v01 result; 584 }; 585 struct ipa_mhi_ch_init_info_type_v01 { 586 uint8_t ch_id; 587 uint8_t er_id; 588 uint32_t ch_doorbell_addr; 589 uint32_t er_doorbell_addr; 590 uint32_t direction_type; 591 }; 592 struct ipa_mhi_smmu_info_type_v01 { 593 uint64_t iova_ctl_base_addr; 594 uint64_t iova_ctl_size; 595 uint64_t iova_data_base_addr; 596 uint64_t iova_data_size; 597 }; 598 struct ipa_mhi_ready_indication_msg_v01 { 599 uint32_t ch_info_arr_len; 600 struct ipa_mhi_ch_init_info_type_v01 ch_info_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; 601 uint8_t smmu_info_valid; 602 struct ipa_mhi_smmu_info_type_v01 smmu_info; 603 }; 604 #define IPA_MHI_READY_INDICATION_MSG_V01_MAX_MSG_LEN 123 605 struct ipa_mhi_mem_addr_info_type_v01 { 606 uint64_t pa; 607 uint64_t iova; 608 uint64_t size; 609 }; 610 enum ipa_mhi_brst_mode_enum_v01 { 611 IPA_MHI_BRST_MODE_ENUM_MIN_VAL_V01 = IPA_INT_MIN, 612 QMI_IPA_BURST_MODE_DEFAULT_V01 = 0, 613 QMI_IPA_BURST_MODE_ENABLED_V01 = 1, 614 QMI_IPA_BURST_MODE_DISABLED_V01 = 2, 615 IPA_MHI_BRST_MODE_ENUM_MAX_VAL_V01 = IPA_INT_MAX, 616 }; 617 struct ipa_mhi_tr_info_type_v01 { 618 uint8_t ch_id; 619 uint16_t poll_cfg; 620 enum ipa_mhi_brst_mode_enum_v01 brst_mode_type; 621 uint64_t ring_iova; 622 uint64_t ring_len; 623 uint64_t rp; 624 uint64_t wp; 625 }; 626 struct ipa_mhi_er_info_type_v01 { 627 uint8_t er_id; 628 uint32_t intmod_cycles; 629 uint32_t intmod_count; 630 uint32_t msi_addr; 631 uint64_t ring_iova; 632 uint64_t ring_len; 633 uint64_t rp; 634 uint64_t wp; 635 }; 636 struct ipa_mhi_alloc_channel_req_msg_v01 { 637 uint32_t tr_info_arr_len; 638 struct ipa_mhi_tr_info_type_v01 tr_info_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; 639 uint32_t er_info_arr_len; 640 struct ipa_mhi_er_info_type_v01 er_info_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; 641 uint32_t ctrl_addr_map_info_len; 642 struct ipa_mhi_mem_addr_info_type_v01 ctrl_addr_map_info[QMI_IPA_REMOTE_MHI_MEMORY_MAPPING_NUM_MAX_V01]; 643 uint32_t data_addr_map_info_len; 644 struct ipa_mhi_mem_addr_info_type_v01 data_addr_map_info[QMI_IPA_REMOTE_MHI_MEMORY_MAPPING_NUM_MAX_V01]; 645 }; 646 #define IPA_MHI_ALLOC_CHANNEL_REQ_MSG_V01_MAX_MSG_LEN 808 647 struct ipa_mhi_ch_alloc_resp_type_v01 { 648 uint8_t ch_id; 649 uint8_t is_success; 650 }; 651 struct ipa_mhi_alloc_channel_resp_msg_v01 { 652 struct ipa_qmi_response_type_v01 resp; 653 uint8_t alloc_resp_arr_valid; 654 uint32_t alloc_resp_arr_len; 655 struct ipa_mhi_ch_alloc_resp_type_v01 alloc_resp_arr[QMI_IPA_REMOTE_MHI_CHANNELS_NUM_MAX_V01]; 656 }; 657 #define IPA_MHI_ALLOC_CHANNEL_RESP_MSG_V01_MAX_MSG_LEN 23 658 enum ipa_clock_rate_enum_v01 { 659 IPA_CLOCK_RATE_ENUM_MIN_ENUM_VAL_V01 = IPA_INT_MIN, 660 QMI_IPA_CLOCK_RATE_INVALID_V01 = 0, 661 QMI_IPA_CLOCK_RATE_LOW_SVS_V01 = 1, 662 QMI_IPA_CLOCK_RATE_SVS_V01 = 2, 663 QMI_IPA_CLOCK_RATE_NOMINAL_V01 = 3, 664 QMI_IPA_CLOCK_RATE_TURBO_V01 = 4, 665 IPA_CLOCK_RATE_ENUM_MAX_ENUM_VAL_V01 = IPA_INT_MAX, 666 }; 667 struct ipa_mhi_clk_vote_req_msg_v01 { 668 uint8_t mhi_vote; 669 uint8_t tput_value_valid; 670 uint32_t tput_value; 671 uint8_t clk_rate_valid; 672 enum ipa_clock_rate_enum_v01 clk_rate; 673 }; 674 #define IPA_MHI_CLK_VOTE_REQ_MSG_V01_MAX_MSG_LEN 18 675 struct ipa_mhi_clk_vote_resp_msg_v01 { 676 struct ipa_qmi_response_type_v01 resp; 677 }; 678 #define IPA_MHI_CLK_VOTE_RESP_MSG_V01_MAX_MSG_LEN 7 679 struct ipa_mhi_cleanup_req_msg_v01 { 680 uint8_t cleanup_valid; 681 uint8_t cleanup; 682 }; 683 #define IPA_MHI_CLEANUP_REQ_MSG_V01_MAX_MSG_LEN 4 684 struct ipa_mhi_cleanup_resp_msg_v01 { 685 struct ipa_qmi_response_type_v01 resp; 686 }; 687 #define IPA_MHI_CLEANUP_RESP_MSG_V01_MAX_MSG_LEN 7 688 enum ipa_ep_desc_type_enum_v01 { 689 IPA_EP_DESC_TYPE_ENUM_MIN_VAL_V01 = IPA_INT_MIN, 690 DATA_EP_DESC_TYPE_RESERVED_V01 = 0x00, 691 DATA_EP_DESC_TYPE_EMB_CONS_V01 = 0x01, 692 DATA_EP_DESC_TYPE_EMB_PROD_V01 = 0x02, 693 DATA_EP_DESC_TYPE_RSC_PROD_V01 = 0x03, 694 DATA_EP_DESC_TYPE_QDSS_PROD_V01 = 0x04, 695 DATA_EP_DESC_TYPE_DPL_PROD_V01 = 0x05, 696 DATA_EP_DESC_TYPE_TETH_CONS_V01 = 0x06, 697 DATA_EP_DESC_TYPE_TETH_PROD_V01 = 0x07, 698 DATA_EP_DESC_TYPE_TETH_RMNET_CONS_V01 = 0x08, 699 DATA_EP_DESC_TYPE_TETH_RMNET_PROD_V01 = 0x09, 700 IPA_EP_DESC_TYPE_ENUM_MAX_VAL_V01 = IPA_INT_MAX, 701 }; 702 enum ipa_ic_type_enum_v01 { 703 IPA_IC_TYPE_ENUM_MIN_VAL_V01 = IPA_INT_MIN, 704 DATA_IC_TYPE_RESERVED_V01 = 0x00, 705 DATA_IC_TYPE_MHI_V01 = 0x01, 706 DATA_IC_TYPE_MHI_PRIME_V01 = 0x02, 707 DATA_IC_TYPE_USB_V01 = 0x03, 708 DATA_IC_TYPE_AP_V01 = 0x04, 709 DATA_IC_TYPE_Q6_V01 = 0x05, 710 DATA_IC_TYPE_UC_V01 = 0x06, 711 IPA_IC_TYPE_ENUM_MAX_VAL_V01 = IPA_INT_MAX, 712 }; 713 enum ipa_ep_status_type_v01 { 714 IPA_EP_STATUS_TYPE_MIN_VAL_V01 = IPA_INT_MIN, 715 DATA_EP_STATUS_RESERVED_V01 = 0x00, 716 DATA_EP_STATUS_STATIC_V01 = 0x01, 717 DATA_EP_STATUS_CONNECTED_V01 = 0x02, 718 DATA_EP_STATUS_DISCONNECTED_V01 = 0x03, 719 IPA_EP_STATUS_TYPE_MAX_VAL_V01 = IPA_INT_MAX, 720 }; 721 struct ipa_ep_id_type_v01 { 722 enum ipa_ic_type_enum_v01 ic_type; 723 enum ipa_ep_desc_type_enum_v01 ep_type; 724 uint32_t ep_id; 725 enum ipa_ep_status_type_v01 ep_status; 726 }; 727 struct ipa_endp_desc_indication_msg_v01 { 728 uint8_t ep_info_valid; 729 uint32_t ep_info_len; 730 struct ipa_ep_id_type_v01 ep_info[QMI_IPA_ENDP_DESC_NUM_MAX_V01]; 731 uint8_t num_eps_valid; 732 uint32_t num_eps; 733 }; 734 #define IPA_ENDP_DESC_INDICATION_MSG_V01_MAX_MSG_LEN 507 735 enum ipa_aggr_enum_type_v01 { 736 IPA_AGGR_ENUM_TYPE_MIN_VAL_V01 = IPA_INT_MIN, 737 DATA_AGGR_TYPE_RESERVED_V01 = 0x00, 738 DATA_AGGR_TYPE_QMAP_V01 = 0x01, 739 DATA_AGGR_TYPE_QMAPv5_V01 = 0x02, 740 DATA_AGGR_TYPE_INHERITED_V01 = 0x03, 741 IPA_AGGR_ENUM_TYPE_MAX_VAL_V01 = IPA_INT_MAX, 742 }; 743 struct ipa_mhi_prime_aggr_info_type_v01 { 744 enum ipa_ic_type_enum_v01 ic_type; 745 enum ipa_ep_desc_type_enum_v01 ep_type; 746 uint32_t bytes_count; 747 uint32_t pkt_count; 748 enum ipa_aggr_enum_type_v01 aggr_type; 749 }; 750 #define IPA_MHI_PRIME_AGGR_INFO_REQ_MSG_V01_MAX_MSG_LEN 631 751 struct ipa_mhi_prime_aggr_info_req_msg_v01 { 752 uint8_t aggr_info_valid; 753 uint32_t aggr_info_len; 754 struct ipa_mhi_prime_aggr_info_type_v01 aggr_info[QMI_IPA_ENDP_DESC_NUM_MAX_V01]; 755 uint8_t num_eps_valid; 756 uint32_t num_eps; 757 }; 758 #define IPA_MHI_PRIME_AGGR_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 759 struct ipa_mhi_prime_aggr_info_resp_msg_v01 { 760 struct ipa_qmi_response_type_v01 resp; 761 }; 762 struct ipa_add_offload_connection_req_msg_v01 { 763 uint8_t num_ipv4_filters_valid; 764 uint32_t num_ipv4_filters; 765 uint8_t num_ipv6_filters_valid; 766 uint32_t num_ipv6_filters; 767 uint8_t xlat_filter_indices_list_valid; 768 uint32_t xlat_filter_indices_list_len; 769 uint32_t xlat_filter_indices_list[QMI_IPA_MAX_FILTERS_V01]; 770 uint8_t filter_spec_ex2_list_valid; 771 uint32_t filter_spec_ex2_list_len; 772 struct ipa_filter_spec_ex2_type_v01 filter_spec_ex2_list[QMI_IPA_MAX_FILTERS_V01]; 773 uint8_t embedded_call_mux_id_valid; 774 uint32_t embedded_call_mux_id; 775 uint8_t default_mhi_path_valid; 776 uint8_t default_mhi_path; 777 }; 778 #define IPA_ADD_OFFLOAD_CONNECTION_REQ_MSG_V01_MAX_MSG_LEN 11361 779 struct ipa_add_offload_connection_resp_msg_v01 { 780 struct ipa_qmi_response_type_v01 resp; 781 uint8_t filter_handle_list_valid; 782 uint32_t filter_handle_list_len; 783 struct ipa_filter_rule_identifier_to_handle_map_v01 filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; 784 }; 785 #define IPA_ADD_OFFLOAD_CONNECTION_RESP_MSG_V01_MAX_MSG_LEN 523 786 struct ipa_remove_offload_connection_req_msg_v01 { 787 uint8_t filter_handle_list_valid; 788 uint32_t filter_handle_list_len; 789 struct ipa_filter_rule_identifier_to_handle_map_v01 filter_handle_list[QMI_IPA_MAX_FILTERS_V01]; 790 uint8_t clean_all_rules_valid; 791 uint8_t clean_all_rules; 792 }; 793 #define IPA_REMOVE_OFFLOAD_CONNECTION_REQ_MSG_V01_MAX_MSG_LEN 520 794 struct ipa_remove_offload_connection_resp_msg_v01 { 795 uint8_t resp_valid; 796 struct ipa_qmi_response_type_v01 resp; 797 }; 798 #define IPA_REMOVE_OFFLOAD_CONNECTION_RESP_MSG_V01_MAX_MSG_LEN 7 799 struct ipa_bw_change_ind_msg_v01 { 800 uint8_t peak_bw_ul_valid; 801 uint32_t peak_bw_ul; 802 uint8_t peak_bw_dl_valid; 803 uint32_t peak_bw_dl; 804 }; 805 #define IPA_BW_CHANGE_IND_MSG_V01_MAX_MSG_LEN 14 806 #define QMI_IPA_INDICATION_REGISTER_REQ_V01 0x0020 807 #define QMI_IPA_INDICATION_REGISTER_RESP_V01 0x0020 808 #define QMI_IPA_INIT_MODEM_DRIVER_REQ_V01 0x0021 809 #define QMI_IPA_INIT_MODEM_DRIVER_RESP_V01 0x0021 810 #define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_V01 0x0022 811 #define QMI_IPA_INSTALL_FILTER_RULE_REQ_V01 0x0023 812 #define QMI_IPA_INSTALL_FILTER_RULE_RESP_V01 0x0023 813 #define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_V01 0x0024 814 #define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_V01 0x0024 815 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0025 816 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0025 817 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_V01 0x0026 818 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_V01 0x0026 819 #define QMI_IPA_CONFIG_REQ_V01 0x0027 820 #define QMI_IPA_CONFIG_RESP_V01 0x0027 821 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0028 822 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0028 823 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_V01 0x0029 824 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_V01 0x0029 825 #define QMI_IPA_GET_DATA_STATS_REQ_V01 0x0030 826 #define QMI_IPA_GET_DATA_STATS_RESP_V01 0x0030 827 #define QMI_IPA_GET_APN_DATA_STATS_REQ_V01 0x0031 828 #define QMI_IPA_GET_APN_DATA_STATS_RESP_V01 0x0031 829 #define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01 0x0032 830 #define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01 0x0032 831 #define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_V01 0x0033 832 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01 0x0034 833 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01 0x0034 834 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_V01 0x0035 835 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_V01 0x0035 836 #define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_V01 0x0037 837 #define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_V01 0x0037 838 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_V01 0x0038 839 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_V01 0x0038 840 #define QMI_IPA_GET_STATS_PER_CLIENT_REQ_V01 0x0039 841 #define QMI_IPA_GET_STATS_PER_CLIENT_RESP_V01 0x0039 842 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_V01 0x003A 843 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_V01 0x003A 844 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_V01 0x003A 845 #define QMI_IPA_MHI_CLK_VOTE_REQ_V01 0x003B 846 #define QMI_IPA_MHI_CLK_VOTE_RESP_V01 0x003B 847 #define QMI_IPA_MHI_READY_IND_V01 0x003C 848 #define QMI_IPA_MHI_ALLOC_CHANNEL_REQ_V01 0x003D 849 #define QMI_IPA_MHI_ALLOC_CHANNEL_RESP_V01 0x003D 850 #define QMI_IPA_MHI_CLEANUP_REQ_V01 0x003E 851 #define QMI_IPA_MHI_CLEANUP_RESP_V01 0x003E 852 #define QMI_IPA_ENDP_DESC_INDICATION_V01 0x003F 853 #define QMI_IPA_MHI_PRIME_AGGR_INFO_REQ_V01 0x0040 854 #define QMI_IPA_MHI_PRIME_AGGR_INFO_RESP_V01 0x0040 855 #define QMI_IPA_ADD_OFFLOAD_CONNECTION_REQ_V01 0x0041 856 #define QMI_IPA_ADD_OFFLOAD_CONNECTION_RESP_V01 0x0041 857 #define QMI_IPA_REMOVE_OFFLOAD_CONNECTION_REQ_V01 0x0042 858 #define QMI_IPA_REMOVE_OFFLOAD_CONNECTION_RESP_V01 0x0042 859 #define QMI_IPA_BW_CHANGE_INDICATION_V01 0x0044 860 #define QMI_IPA_INIT_MODEM_DRIVER_REQ_MAX_MSG_LEN_V01 162 861 #define QMI_IPA_INIT_MODEM_DRIVER_RESP_MAX_MSG_LEN_V01 25 862 #define QMI_IPA_INDICATION_REGISTER_REQ_MAX_MSG_LEN_V01 20 863 #define QMI_IPA_INDICATION_REGISTER_RESP_MAX_MSG_LEN_V01 7 864 #define QMI_IPA_INSTALL_FILTER_RULE_REQ_MAX_MSG_LEN_V01 33705 865 #define QMI_IPA_INSTALL_FILTER_RULE_RESP_MAX_MSG_LEN_V01 783 866 #define QMI_IPA_FILTER_INSTALLED_NOTIF_REQ_MAX_MSG_LEN_V01 1899 867 #define QMI_IPA_FILTER_INSTALLED_NOTIF_RESP_MAX_MSG_LEN_V01 7 868 #define QMI_IPA_MASTER_DRIVER_INIT_COMPLETE_IND_MAX_MSG_LEN_V01 7 869 #define QMI_IPA_DATA_USAGE_QUOTA_REACHED_IND_MAX_MSG_LEN_V01 15 870 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 18 871 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_REQ_MAX_MSG_LEN_V01 7 872 #define QMI_IPA_ENABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 873 #define QMI_IPA_DISABLE_FORCE_CLEAR_DATAPATH_RESP_MAX_MSG_LEN_V01 7 874 #define QMI_IPA_CONFIG_REQ_MAX_MSG_LEN_V01 102 875 #define QMI_IPA_CONFIG_RESP_MAX_MSG_LEN_V01 7 876 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 18 877 #define QMI_IPA_DISABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 878 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_REQ_MAX_MSG_LEN_V01 7 879 #define QMI_IPA_ENABLE_LINK_LOW_PWR_STATE_RESP_MAX_MSG_LEN_V01 7 880 #define QMI_IPA_GET_DATA_STATS_REQ_MAX_MSG_LEN_V01 11 881 #define QMI_IPA_GET_DATA_STATS_RESP_MAX_MSG_LEN_V01 2234 882 #define QMI_IPA_GET_APN_DATA_STATS_REQ_MAX_MSG_LEN_V01 36 883 #define QMI_IPA_GET_APN_DATA_STATS_RESP_MAX_MSG_LEN_V01 299 884 #define QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 100 885 #define QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 886 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_MAX_MSG_LEN_V01 0 887 #define QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_MAX_MSG_LEN_V01 7 888 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_REQ_MAX_MSG_LEN_V01 4 889 #define QMI_IPA_INIT_MODEM_DRIVER_CMPLT_RESP_MAX_MSG_LEN_V01 7 890 #define QMI_IPA_INSTALL_FILTER_RULE_EX_REQ_MAX_MSG_LEN_V01 34021 891 #define QMI_IPA_INSTALL_FILTER_RULE_EX_RESP_MAX_MSG_LEN_V01 523 892 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_REQ_MAX_MSG_LEN_V01 4 893 #define QMI_IPA_ENABLE_PER_CLIENT_STATS_RESP_MAX_MSG_LEN_V01 7 894 #define QMI_IPA_GET_STATS_PER_CLIENT_REQ_MAX_MSG_LEN_V01 18 895 #define QMI_IPA_GET_STATS_PER_CLIENT_RESP_MAX_MSG_LEN_V01 3595 896 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_REQ_MAX_MSG_LEN_V01 9875 897 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_RESP_MAX_MSG_LEN_V01 7 898 #define QMI_IPA_INSTALL_UL_FIREWALL_RULES_IND_MAX_MSG_LEN_V01 11 899 #define QMI_IPA_MAX_MSG_LEN 22685 900 #endif 901