1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _MSM_MDP_H_ 8 #define _MSM_MDP_H_ 9 #include <stdint.h> 10 #include <linux/fb.h> 11 #define MSMFB_IOCTL_MAGIC 'm' 12 #define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int) 13 #define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int) 14 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int) 15 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int) 16 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor) 17 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap) 18 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data) 19 #define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs) 20 #define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs) 21 #define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, struct mdp_overlay) 22 #define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int) 23 #define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, struct msmfb_overlay_data) 24 #define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY 25 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, struct mdp_page_protection) 26 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, struct mdp_page_protection) 27 #define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, struct mdp_overlay) 28 #define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int) 29 #define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, struct msmfb_overlay_blt) 30 #define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int) 31 #define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, struct mdp_histogram_start_req) 32 #define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int) 33 #define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int) 34 #define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, struct msmfb_overlay_3d) 35 #define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, struct msmfb_mixer_info_req) 36 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, struct msmfb_overlay_data) 37 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150) 38 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151) 39 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152) 40 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, struct msmfb_data) 41 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, struct msmfb_data) 42 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155) 43 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp) 44 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int) 45 #define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int) 46 #define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync) 47 #define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163) 48 #define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, struct mdp_display_commit) 49 #define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata) 50 #define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata) 51 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, unsigned int) 52 #define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int) 53 #define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, struct mdp_overlay_list) 54 #define MSMFB_LPM_ENABLE _IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int) 55 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, struct mdp_pp_feature_version) 56 #define FB_TYPE_3D_PANEL 0x10101010 57 #define MDP_IMGTYPE2_START 0x10000 58 #define MSMFB_DRIVER_VERSION 0xF9E8D701 59 #define MDP_IMGTYPE_END 0x100 60 #define MDSS_GET_MAJOR(rev) ((rev) >> 28) 61 #define MDSS_GET_MINOR(rev) (((rev) >> 16) & 0xFFF) 62 #define MDSS_GET_STEP(rev) ((rev) & 0xFFFF) 63 #define MDSS_GET_MAJOR_MINOR(rev) ((rev) >> 16) 64 #define IS_MDSS_MAJOR_MINOR_SAME(rev1,rev2) (MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2))) 65 #define MDSS_MDP_REV(major,minor,step) ((((major) & 0x000F) << 28) | (((minor) & 0x0FFF) << 16) | ((step) & 0xFFFF)) 66 #define MDSS_MDP_HW_REV_100 MDSS_MDP_REV(1, 0, 0) 67 #define MDSS_MDP_HW_REV_101 MDSS_MDP_REV(1, 1, 0) 68 #define MDSS_MDP_HW_REV_101_1 MDSS_MDP_REV(1, 1, 1) 69 #define MDSS_MDP_HW_REV_101_2 MDSS_MDP_REV(1, 1, 2) 70 #define MDSS_MDP_HW_REV_102 MDSS_MDP_REV(1, 2, 0) 71 #define MDSS_MDP_HW_REV_102_1 MDSS_MDP_REV(1, 2, 1) 72 #define MDSS_MDP_HW_REV_103 MDSS_MDP_REV(1, 3, 0) 73 #define MDSS_MDP_HW_REV_103_1 MDSS_MDP_REV(1, 3, 1) 74 #define MDSS_MDP_HW_REV_105 MDSS_MDP_REV(1, 5, 0) 75 #define MDSS_MDP_HW_REV_106 MDSS_MDP_REV(1, 6, 0) 76 #define MDSS_MDP_HW_REV_107 MDSS_MDP_REV(1, 7, 0) 77 #define MDSS_MDP_HW_REV_107_1 MDSS_MDP_REV(1, 7, 1) 78 #define MDSS_MDP_HW_REV_107_2 MDSS_MDP_REV(1, 7, 2) 79 #define MDSS_MDP_HW_REV_108 MDSS_MDP_REV(1, 8, 0) 80 #define MDSS_MDP_HW_REV_109 MDSS_MDP_REV(1, 9, 0) 81 #define MDSS_MDP_HW_REV_110 MDSS_MDP_REV(1, 10, 0) 82 #define MDSS_MDP_HW_REV_200 MDSS_MDP_REV(2, 0, 0) 83 #define MDSS_MDP_HW_REV_112 MDSS_MDP_REV(1, 12, 0) 84 #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) 85 #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) 86 #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) 87 #define MDSS_MDP_HW_REV_117 MDSS_MDP_REV(1, 17, 0) 88 #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) 89 #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) 90 #define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) 91 #define MDSS_MDP_HW_REV_330 MDSS_MDP_REV(3, 3, 0) 92 enum { 93 NOTIFY_UPDATE_INIT, 94 NOTIFY_UPDATE_DEINIT, 95 NOTIFY_UPDATE_START, 96 NOTIFY_UPDATE_STOP, 97 NOTIFY_UPDATE_POWER_OFF, 98 }; 99 enum { 100 NOTIFY_TYPE_NO_UPDATE, 101 NOTIFY_TYPE_SUSPEND, 102 NOTIFY_TYPE_UPDATE, 103 NOTIFY_TYPE_BL_UPDATE, 104 NOTIFY_TYPE_BL_AD_ATTEN_UPDATE, 105 }; 106 enum { 107 MDP_RGB_565, 108 MDP_XRGB_8888, 109 MDP_Y_CBCR_H2V2, 110 MDP_Y_CBCR_H2V2_ADRENO, 111 MDP_ARGB_8888, 112 MDP_RGB_888, 113 MDP_Y_CRCB_H2V2, 114 MDP_YCRYCB_H2V1, 115 MDP_CBYCRY_H2V1, 116 MDP_Y_CRCB_H2V1, 117 MDP_Y_CBCR_H2V1, 118 MDP_Y_CRCB_H1V2, 119 MDP_Y_CBCR_H1V2, 120 MDP_RGBA_8888, 121 MDP_BGRA_8888, 122 MDP_RGBX_8888, 123 MDP_Y_CRCB_H2V2_TILE, 124 MDP_Y_CBCR_H2V2_TILE, 125 MDP_Y_CR_CB_H2V2, 126 MDP_Y_CR_CB_GH2V2, 127 MDP_Y_CB_CR_H2V2, 128 MDP_Y_CRCB_H1V1, 129 MDP_Y_CBCR_H1V1, 130 MDP_YCRCB_H1V1, 131 MDP_YCBCR_H1V1, 132 MDP_BGR_565, 133 MDP_BGR_888, 134 MDP_Y_CBCR_H2V2_VENUS, 135 MDP_BGRX_8888, 136 MDP_RGBA_8888_TILE, 137 MDP_ARGB_8888_TILE, 138 MDP_ABGR_8888_TILE, 139 MDP_BGRA_8888_TILE, 140 MDP_RGBX_8888_TILE, 141 MDP_XRGB_8888_TILE, 142 MDP_XBGR_8888_TILE, 143 MDP_BGRX_8888_TILE, 144 MDP_YCBYCR_H2V1, 145 MDP_RGB_565_TILE, 146 MDP_BGR_565_TILE, 147 MDP_ARGB_1555, 148 MDP_RGBA_5551, 149 MDP_ARGB_4444, 150 MDP_RGBA_4444, 151 MDP_RGB_565_UBWC, 152 MDP_RGBA_8888_UBWC, 153 MDP_Y_CBCR_H2V2_UBWC, 154 MDP_RGBX_8888_UBWC, 155 MDP_Y_CRCB_H2V2_VENUS, 156 MDP_IMGTYPE_LIMIT, 157 MDP_RGB_BORDERFILL, 158 MDP_XRGB_1555, 159 MDP_RGBX_5551, 160 MDP_XRGB_4444, 161 MDP_RGBX_4444, 162 MDP_ABGR_1555, 163 MDP_BGRA_5551, 164 MDP_XBGR_1555, 165 MDP_BGRX_5551, 166 MDP_ABGR_4444, 167 MDP_BGRA_4444, 168 MDP_XBGR_4444, 169 MDP_BGRX_4444, 170 MDP_ABGR_8888, 171 MDP_XBGR_8888, 172 MDP_RGBA_1010102, 173 MDP_ARGB_2101010, 174 MDP_RGBX_1010102, 175 MDP_XRGB_2101010, 176 MDP_BGRA_1010102, 177 MDP_ABGR_2101010, 178 MDP_BGRX_1010102, 179 MDP_XBGR_2101010, 180 MDP_RGBA_1010102_UBWC, 181 MDP_RGBX_1010102_UBWC, 182 MDP_Y_CBCR_H2V2_P010, 183 MDP_Y_CBCR_H2V2_TP10_UBWC, 184 MDP_CRYCBY_H2V1, 185 MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END, 186 MDP_FB_FORMAT = MDP_IMGTYPE2_START, 187 MDP_IMGTYPE_LIMIT2 188 }; 189 #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1 190 enum { 191 PMEM_IMG, 192 FB_IMG, 193 }; 194 enum { 195 HSIC_HUE = 0, 196 HSIC_SAT, 197 HSIC_INT, 198 HSIC_CON, 199 NUM_HSIC_PARAM, 200 }; 201 enum mdss_mdp_max_bw_mode { 202 MDSS_MAX_BW_LIMIT_DEFAULT = 0x1, 203 MDSS_MAX_BW_LIMIT_CAMERA = 0x2, 204 MDSS_MAX_BW_LIMIT_HFLIP = 0x4, 205 MDSS_MAX_BW_LIMIT_VFLIP = 0x8, 206 }; 207 #define MDSS_MDP_ROT_ONLY 0x80 208 #define MDSS_MDP_RIGHT_MIXER 0x100 209 #define MDSS_MDP_DUAL_PIPE 0x200 210 #define MDP_ROT_NOP 0 211 #define MDP_FLIP_LR 0x1 212 #define MDP_FLIP_UD 0x2 213 #define MDP_ROT_90 0x4 214 #define MDP_ROT_180 (MDP_FLIP_UD | MDP_FLIP_LR) 215 #define MDP_ROT_270 (MDP_ROT_90 | MDP_FLIP_UD | MDP_FLIP_LR) 216 #define MDP_DITHER 0x8 217 #define MDP_BLUR 0x10 218 #define MDP_BLEND_FG_PREMULT 0x20000 219 #define MDP_IS_FG 0x40000 220 #define MDP_SOLID_FILL 0x00000020 221 #define MDP_VPU_PIPE 0x00000040 222 #define MDP_DEINTERLACE 0x80000000 223 #define MDP_SHARPENING 0x40000000 224 #define MDP_NO_DMA_BARRIER_START 0x20000000 225 #define MDP_NO_DMA_BARRIER_END 0x10000000 226 #define MDP_NO_BLIT 0x08000000 227 #define MDP_BLIT_WITH_DMA_BARRIERS 0x000 228 #define MDP_BLIT_WITH_NO_DMA_BARRIERS (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END) 229 #define MDP_BLIT_SRC_GEM 0x04000000 230 #define MDP_BLIT_DST_GEM 0x02000000 231 #define MDP_BLIT_NON_CACHED 0x01000000 232 #define MDP_OV_PIPE_SHARE 0x00800000 233 #define MDP_DEINTERLACE_ODD 0x00400000 234 #define MDP_OV_PLAY_NOWAIT 0x00200000 235 #define MDP_SOURCE_ROTATED_90 0x00100000 236 #define MDP_OVERLAY_PP_CFG_EN 0x00080000 237 #define MDP_BACKEND_COMPOSITION 0x00040000 238 #define MDP_BORDERFILL_SUPPORTED 0x00010000 239 #define MDP_SECURE_OVERLAY_SESSION 0x00008000 240 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000 241 #define MDP_OV_PIPE_FORCE_DMA 0x00004000 242 #define MDP_MEMORY_ID_TYPE_FB 0x00001000 243 #define MDP_BWC_EN 0x00000400 244 #define MDP_DECIMATION_EN 0x00000800 245 #define MDP_SMP_FORCE_ALLOC 0x00200000 246 #define MDP_TRANSP_NOP 0xffffffff 247 #define MDP_ALPHA_NOP 0xff 248 #define MDP_FB_PAGE_PROTECTION_NONCACHED (0) 249 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1) 250 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2) 251 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3) 252 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4) 253 #define MDP_FB_PAGE_PROTECTION_INVALID (5) 254 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5) 255 #define MDP_DEEP_COLOR_YUV444 0x1 256 #define MDP_DEEP_COLOR_RGB30B 0x2 257 #define MDP_DEEP_COLOR_RGB36B 0x4 258 #define MDP_DEEP_COLOR_RGB48B 0x8 259 struct mdp_rect { 260 uint32_t x; 261 uint32_t y; 262 uint32_t w; 263 uint32_t h; 264 }; 265 struct mdp_img { 266 uint32_t width; 267 uint32_t height; 268 uint32_t format; 269 uint32_t offset; 270 int memory_id; 271 uint32_t priv; 272 }; 273 struct mult_factor { 274 uint32_t numer; 275 uint32_t denom; 276 }; 277 #define MDP_CCS_RGB2YUV 0 278 #define MDP_CCS_YUV2RGB 1 279 #define MDP_CCS_SIZE 9 280 #define MDP_BV_SIZE 3 281 struct mdp_ccs { 282 int direction; 283 uint16_t ccs[MDP_CCS_SIZE]; 284 uint16_t bv[MDP_BV_SIZE]; 285 }; 286 struct mdp_csc { 287 int id; 288 uint32_t csc_mv[9]; 289 uint32_t csc_pre_bv[3]; 290 uint32_t csc_post_bv[3]; 291 uint32_t csc_pre_lv[6]; 292 uint32_t csc_post_lv[6]; 293 }; 294 #define MDP_BLIT_REQ_VERSION 3 295 struct color { 296 uint32_t r; 297 uint32_t g; 298 uint32_t b; 299 uint32_t alpha; 300 }; 301 struct mdp_blit_req { 302 struct mdp_img src; 303 struct mdp_img dst; 304 struct mdp_rect src_rect; 305 struct mdp_rect dst_rect; 306 struct color const_color; 307 uint32_t alpha; 308 uint32_t transp_mask; 309 uint32_t flags; 310 int sharpening_strength; 311 uint8_t color_space; 312 uint32_t fps; 313 }; 314 struct mdp_blit_req_list { 315 uint32_t count; 316 struct mdp_blit_req req[]; 317 }; 318 #define MSMFB_DATA_VERSION 2 319 struct msmfb_data { 320 uint32_t offset; 321 int memory_id; 322 int id; 323 uint32_t flags; 324 uint32_t priv; 325 uint32_t iova; 326 }; 327 #define MSMFB_NEW_REQUEST - 1 328 struct msmfb_overlay_data { 329 uint32_t id; 330 struct msmfb_data data; 331 uint32_t version_key; 332 struct msmfb_data plane1_data; 333 struct msmfb_data plane2_data; 334 struct msmfb_data dst_data; 335 }; 336 struct msmfb_img { 337 uint32_t width; 338 uint32_t height; 339 uint32_t format; 340 }; 341 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1 342 struct msmfb_writeback_data { 343 struct msmfb_data buf_info; 344 struct msmfb_img img; 345 }; 346 #define MDP_PP_OPS_ENABLE 0x1 347 #define MDP_PP_OPS_READ 0x2 348 #define MDP_PP_OPS_WRITE 0x4 349 #define MDP_PP_OPS_DISABLE 0x8 350 #define MDP_PP_IGC_FLAG_ROM0 0x10 351 #define MDP_PP_IGC_FLAG_ROM1 0x20 352 #define MDSS_PP_DSPP_CFG 0x000 353 #define MDSS_PP_SSPP_CFG 0x100 354 #define MDSS_PP_LM_CFG 0x200 355 #define MDSS_PP_WB_CFG 0x300 356 #define MDSS_PP_ARG_MASK 0x3C00 357 #define MDSS_PP_ARG_NUM 4 358 #define MDSS_PP_ARG_SHIFT 10 359 #define MDSS_PP_LOCATION_MASK 0x0300 360 #define MDSS_PP_LOGICAL_MASK 0x00FF 361 #define MDSS_PP_ADD_ARG(var,arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg)))) 362 #define PP_ARG(x,var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x)))) 363 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK) 364 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK) 365 struct mdp_qseed_cfg { 366 uint32_t table_num; 367 uint32_t ops; 368 uint32_t len; 369 uint32_t * data; 370 }; 371 struct mdp_sharp_cfg { 372 uint32_t flags; 373 uint32_t strength; 374 uint32_t edge_thr; 375 uint32_t smooth_thr; 376 uint32_t noise_thr; 377 }; 378 struct mdp_qseed_cfg_data { 379 uint32_t block; 380 struct mdp_qseed_cfg qseed_data; 381 }; 382 #define MDP_OVERLAY_PP_CSC_CFG 0x1 383 #define MDP_OVERLAY_PP_QSEED_CFG 0x2 384 #define MDP_OVERLAY_PP_PA_CFG 0x4 385 #define MDP_OVERLAY_PP_IGC_CFG 0x8 386 #define MDP_OVERLAY_PP_SHARP_CFG 0x10 387 #define MDP_OVERLAY_PP_HIST_CFG 0x20 388 #define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40 389 #define MDP_OVERLAY_PP_PA_V2_CFG 0x80 390 #define MDP_OVERLAY_PP_PCC_CFG 0x100 391 #define MDP_CSC_FLAG_ENABLE 0x1 392 #define MDP_CSC_FLAG_YUV_IN 0x2 393 #define MDP_CSC_FLAG_YUV_OUT 0x4 394 #define MDP_CSC_MATRIX_COEFF_SIZE 9 395 #define MDP_CSC_CLAMP_SIZE 6 396 #define MDP_CSC_BIAS_SIZE 3 397 struct mdp_csc_cfg { 398 uint32_t flags; 399 uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE]; 400 uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE]; 401 uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE]; 402 uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE]; 403 uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE]; 404 }; 405 struct mdp_csc_cfg_data { 406 uint32_t block; 407 struct mdp_csc_cfg csc_data; 408 }; 409 struct mdp_pa_cfg { 410 uint32_t flags; 411 uint32_t hue_adj; 412 uint32_t sat_adj; 413 uint32_t val_adj; 414 uint32_t cont_adj; 415 }; 416 struct mdp_pa_mem_col_cfg { 417 uint32_t color_adjust_p0; 418 uint32_t color_adjust_p1; 419 uint32_t hue_region; 420 uint32_t sat_region; 421 uint32_t val_region; 422 }; 423 #define MDP_SIX_ZONE_LUT_SIZE 384 424 #define MDP_PP_PA_HUE_ENABLE 0x10 425 #define MDP_PP_PA_SAT_ENABLE 0x20 426 #define MDP_PP_PA_VAL_ENABLE 0x40 427 #define MDP_PP_PA_CONT_ENABLE 0x80 428 #define MDP_PP_PA_SIX_ZONE_ENABLE 0x100 429 #define MDP_PP_PA_SKIN_ENABLE 0x200 430 #define MDP_PP_PA_SKY_ENABLE 0x400 431 #define MDP_PP_PA_FOL_ENABLE 0x800 432 #define MDP_PP_PA_MEM_PROT_HUE_EN 0x1 433 #define MDP_PP_PA_MEM_PROT_SAT_EN 0x2 434 #define MDP_PP_PA_MEM_PROT_VAL_EN 0x4 435 #define MDP_PP_PA_MEM_PROT_CONT_EN 0x8 436 #define MDP_PP_PA_MEM_PROT_SIX_EN 0x10 437 #define MDP_PP_PA_MEM_PROT_BLEND_EN 0x20 438 #define MDP_PP_PA_HUE_MASK 0x1000 439 #define MDP_PP_PA_SAT_MASK 0x2000 440 #define MDP_PP_PA_VAL_MASK 0x4000 441 #define MDP_PP_PA_CONT_MASK 0x8000 442 #define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000 443 #define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000 444 #define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000 445 #define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000 446 #define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000 447 #define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000 448 #define MDP_PP_PA_MEM_PROTECT_EN 0x400000 449 #define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000 450 #define MDP_PP_PA_LEFT_HOLD 0x1 451 #define MDP_PP_PA_RIGHT_HOLD 0x2 452 struct mdp_pa_v2_data { 453 uint32_t flags; 454 uint32_t global_hue_adj; 455 uint32_t global_sat_adj; 456 uint32_t global_val_adj; 457 uint32_t global_cont_adj; 458 struct mdp_pa_mem_col_cfg skin_cfg; 459 struct mdp_pa_mem_col_cfg sky_cfg; 460 struct mdp_pa_mem_col_cfg fol_cfg; 461 uint32_t six_zone_len; 462 uint32_t six_zone_thresh; 463 uint32_t * six_zone_curve_p0; 464 uint32_t * six_zone_curve_p1; 465 }; 466 struct mdp_pa_mem_col_data_v1_7 { 467 uint32_t color_adjust_p0; 468 uint32_t color_adjust_p1; 469 uint32_t color_adjust_p2; 470 uint32_t blend_gain; 471 uint8_t sat_hold; 472 uint8_t val_hold; 473 uint32_t hue_region; 474 uint32_t sat_region; 475 uint32_t val_region; 476 }; 477 struct mdp_pa_data_v1_7 { 478 uint32_t mode; 479 uint32_t global_hue_adj; 480 uint32_t global_sat_adj; 481 uint32_t global_val_adj; 482 uint32_t global_cont_adj; 483 struct mdp_pa_mem_col_data_v1_7 skin_cfg; 484 struct mdp_pa_mem_col_data_v1_7 sky_cfg; 485 struct mdp_pa_mem_col_data_v1_7 fol_cfg; 486 uint32_t six_zone_thresh; 487 uint32_t six_zone_adj_p0; 488 uint32_t six_zone_adj_p1; 489 uint8_t six_zone_sat_hold; 490 uint8_t six_zone_val_hold; 491 uint32_t six_zone_len; 492 uint32_t * six_zone_curve_p0; 493 uint32_t * six_zone_curve_p1; 494 }; 495 struct mdp_pa_v2_cfg_data { 496 uint32_t version; 497 uint32_t block; 498 uint32_t flags; 499 struct mdp_pa_v2_data pa_v2_data; 500 void * cfg_payload; 501 }; 502 enum { 503 mdp_igc_rec601 = 1, 504 mdp_igc_rec709, 505 mdp_igc_srgb, 506 mdp_igc_custom, 507 mdp_igc_rec_max, 508 }; 509 struct mdp_igc_lut_data { 510 uint32_t block; 511 uint32_t version; 512 uint32_t len, ops; 513 uint32_t * c0_c1_data; 514 uint32_t * c2_data; 515 void * cfg_payload; 516 }; 517 struct mdp_igc_lut_data_v1_7 { 518 uint32_t table_fmt; 519 uint32_t len; 520 uint32_t * c0_c1_data; 521 uint32_t * c2_data; 522 }; 523 struct mdp_igc_lut_data_payload { 524 uint32_t table_fmt; 525 uint32_t len; 526 uint64_t c0_c1_data; 527 uint64_t c2_data; 528 uint32_t strength; 529 }; 530 struct mdp_histogram_cfg { 531 uint32_t ops; 532 uint32_t block; 533 uint8_t frame_cnt; 534 uint8_t bit_mask; 535 uint16_t num_bins; 536 }; 537 struct mdp_hist_lut_data_v1_7 { 538 uint32_t len; 539 uint32_t * data; 540 }; 541 struct mdp_hist_lut_data { 542 uint32_t block; 543 uint32_t version; 544 uint32_t hist_lut_first; 545 uint32_t ops; 546 uint32_t len; 547 uint32_t * data; 548 void * cfg_payload; 549 }; 550 struct mdp_pcc_coeff { 551 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1; 552 }; 553 struct mdp_pcc_coeff_v1_7 { 554 uint32_t c, r, g, b, rg, gb, rb, rgb; 555 }; 556 struct mdp_pcc_data_v1_7 { 557 struct mdp_pcc_coeff_v1_7 r, g, b; 558 }; 559 struct mdp_pcc_cfg_data { 560 uint32_t version; 561 uint32_t block; 562 uint32_t ops; 563 struct mdp_pcc_coeff r, g, b; 564 void * cfg_payload; 565 }; 566 enum { 567 mdp_lut_igc, 568 mdp_lut_pgc, 569 mdp_lut_hist, 570 mdp_lut_rgb, 571 mdp_lut_max, 572 }; 573 struct mdp_overlay_pp_params { 574 uint32_t config_ops; 575 struct mdp_csc_cfg csc_cfg; 576 struct mdp_qseed_cfg qseed_cfg[2]; 577 struct mdp_pa_cfg pa_cfg; 578 struct mdp_pa_v2_data pa_v2_cfg; 579 struct mdp_igc_lut_data igc_cfg; 580 struct mdp_sharp_cfg sharp_cfg; 581 struct mdp_histogram_cfg hist_cfg; 582 struct mdp_hist_lut_data hist_lut_cfg; 583 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 584 struct mdp_pcc_cfg_data pcc_cfg_data; 585 }; 586 enum mdss_mdp_blend_op { 587 BLEND_OP_NOT_DEFINED = 0, 588 BLEND_OP_OPAQUE, 589 BLEND_OP_PREMULTIPLIED, 590 BLEND_OP_COVERAGE, 591 BLEND_OP_MAX, 592 }; 593 #define DECIMATED_DIMENSION(dim,deci) (((dim) + ((1 << (deci)) - 1)) >> (deci)) 594 #define MAX_PLANES 4 595 struct mdp_scale_data { 596 uint8_t enable_pxl_ext; 597 int init_phase_x[MAX_PLANES]; 598 int phase_step_x[MAX_PLANES]; 599 int init_phase_y[MAX_PLANES]; 600 int phase_step_y[MAX_PLANES]; 601 int num_ext_pxls_left[MAX_PLANES]; 602 int num_ext_pxls_right[MAX_PLANES]; 603 int num_ext_pxls_top[MAX_PLANES]; 604 int num_ext_pxls_btm[MAX_PLANES]; 605 int left_ftch[MAX_PLANES]; 606 int left_rpt[MAX_PLANES]; 607 int right_ftch[MAX_PLANES]; 608 int right_rpt[MAX_PLANES]; 609 int top_rpt[MAX_PLANES]; 610 int btm_rpt[MAX_PLANES]; 611 int top_ftch[MAX_PLANES]; 612 int btm_ftch[MAX_PLANES]; 613 uint32_t roi_w[MAX_PLANES]; 614 }; 615 enum mdp_overlay_pipe_type { 616 PIPE_TYPE_AUTO = 0, 617 PIPE_TYPE_VIG, 618 PIPE_TYPE_RGB, 619 PIPE_TYPE_DMA, 620 PIPE_TYPE_CURSOR, 621 PIPE_TYPE_MAX, 622 }; 623 struct mdp_overlay { 624 struct msmfb_img src; 625 struct mdp_rect src_rect; 626 struct mdp_rect dst_rect; 627 uint32_t z_order; 628 uint32_t is_fg; 629 uint32_t alpha; 630 uint32_t blend_op; 631 uint32_t transp_mask; 632 uint32_t flags; 633 uint32_t pipe_type; 634 uint32_t id; 635 uint8_t priority; 636 uint32_t user_data[6]; 637 uint32_t bg_color; 638 uint8_t horz_deci; 639 uint8_t vert_deci; 640 struct mdp_overlay_pp_params overlay_pp_cfg; 641 struct mdp_scale_data scale; 642 uint8_t color_space; 643 uint32_t frame_rate; 644 }; 645 struct msmfb_overlay_3d { 646 uint32_t is_3d; 647 uint32_t width; 648 uint32_t height; 649 }; 650 struct msmfb_overlay_blt { 651 uint32_t enable; 652 uint32_t offset; 653 uint32_t width; 654 uint32_t height; 655 uint32_t bpp; 656 }; 657 struct mdp_histogram { 658 uint32_t frame_cnt; 659 uint32_t bin_cnt; 660 uint32_t * r; 661 uint32_t * g; 662 uint32_t * b; 663 }; 664 #define MISR_CRC_BATCH_SIZE 32 665 enum { 666 DISPLAY_MISR_EDP, 667 DISPLAY_MISR_DSI0, 668 DISPLAY_MISR_DSI1, 669 DISPLAY_MISR_HDMI, 670 DISPLAY_MISR_LCDC, 671 DISPLAY_MISR_MDP, 672 DISPLAY_MISR_ATV, 673 DISPLAY_MISR_DSI_CMD, 674 DISPLAY_MISR_MAX 675 }; 676 enum { 677 MISR_OP_NONE, 678 MISR_OP_SFM, 679 MISR_OP_MFM, 680 MISR_OP_BM, 681 MISR_OP_MAX 682 }; 683 struct mdp_misr { 684 uint32_t block_id; 685 uint32_t frame_count; 686 uint32_t crc_op_mode; 687 uint32_t crc_value[MISR_CRC_BATCH_SIZE]; 688 }; 689 enum { 690 MDP_BLOCK_RESERVED = 0, 691 MDP_BLOCK_OVERLAY_0, 692 MDP_BLOCK_OVERLAY_1, 693 MDP_BLOCK_VG_1, 694 MDP_BLOCK_VG_2, 695 MDP_BLOCK_RGB_1, 696 MDP_BLOCK_RGB_2, 697 MDP_BLOCK_DMA_P, 698 MDP_BLOCK_DMA_S, 699 MDP_BLOCK_DMA_E, 700 MDP_BLOCK_OVERLAY_2, 701 MDP_LOGICAL_BLOCK_DISP_0 = 0x10, 702 MDP_LOGICAL_BLOCK_DISP_1, 703 MDP_LOGICAL_BLOCK_DISP_2, 704 MDP_BLOCK_MAX, 705 }; 706 struct mdp_histogram_start_req { 707 uint32_t block; 708 uint8_t frame_cnt; 709 uint8_t bit_mask; 710 uint16_t num_bins; 711 }; 712 struct mdp_histogram_data { 713 uint32_t block; 714 uint32_t bin_cnt; 715 uint32_t * c0; 716 uint32_t * c1; 717 uint32_t * c2; 718 uint32_t * extra_info; 719 }; 720 #define GC_LUT_ENTRIES_V1_7 512 721 struct mdp_ar_gc_lut_data { 722 uint32_t x_start; 723 uint32_t slope; 724 uint32_t offset; 725 }; 726 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10 727 struct mdp_pgc_lut_data { 728 uint32_t version; 729 uint32_t block; 730 uint32_t flags; 731 uint8_t num_r_stages; 732 uint8_t num_g_stages; 733 uint8_t num_b_stages; 734 struct mdp_ar_gc_lut_data * r_data; 735 struct mdp_ar_gc_lut_data * g_data; 736 struct mdp_ar_gc_lut_data * b_data; 737 void * cfg_payload; 738 }; 739 #define PGC_LUT_ENTRIES 1024 740 struct mdp_pgc_lut_data_v1_7 { 741 uint32_t len; 742 uint32_t * c0_data; 743 uint32_t * c1_data; 744 uint32_t * c2_data; 745 }; 746 struct mdp_rgb_lut_data { 747 uint32_t flags; 748 uint32_t lut_type; 749 struct fb_cmap cmap; 750 }; 751 enum { 752 mdp_rgb_lut_gc, 753 mdp_rgb_lut_hist, 754 }; 755 struct mdp_lut_cfg_data { 756 uint32_t lut_type; 757 union { 758 struct mdp_igc_lut_data igc_lut_data; 759 struct mdp_pgc_lut_data pgc_lut_data; 760 struct mdp_hist_lut_data hist_lut_data; 761 struct mdp_rgb_lut_data rgb_lut_data; 762 } data; 763 }; 764 struct mdp_bl_scale_data { 765 uint32_t min_lvl; 766 uint32_t scale; 767 }; 768 struct mdp_pa_cfg_data { 769 uint32_t block; 770 struct mdp_pa_cfg pa_data; 771 }; 772 #define MDP_DITHER_DATA_V1_7_SZ 16 773 struct mdp_dither_data_v1_7 { 774 uint32_t g_y_depth; 775 uint32_t r_cr_depth; 776 uint32_t b_cb_depth; 777 uint32_t len; 778 uint32_t data[MDP_DITHER_DATA_V1_7_SZ]; 779 uint32_t temporal_en; 780 }; 781 struct mdp_pa_dither_data { 782 uint64_t data_flags; 783 uint32_t matrix_sz; 784 uint64_t matrix_data; 785 uint32_t strength; 786 uint32_t offset_en; 787 }; 788 struct mdp_dither_cfg_data { 789 uint32_t version; 790 uint32_t block; 791 uint32_t flags; 792 uint32_t mode; 793 uint32_t g_y_depth; 794 uint32_t r_cr_depth; 795 uint32_t b_cb_depth; 796 void * cfg_payload; 797 }; 798 #define MDP_GAMUT_TABLE_NUM 8 799 #define MDP_GAMUT_TABLE_NUM_V1_7 4 800 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM 3 801 #define MDP_GAMUT_TABLE_V1_7_SZ 1229 802 #define MDP_GAMUT_SCALE_OFF_SZ 16 803 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32 804 struct mdp_gamut_cfg_data { 805 uint32_t block; 806 uint32_t flags; 807 uint32_t version; 808 uint32_t gamut_first; 809 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM]; 810 uint16_t * r_tbl[MDP_GAMUT_TABLE_NUM]; 811 uint16_t * g_tbl[MDP_GAMUT_TABLE_NUM]; 812 uint16_t * b_tbl[MDP_GAMUT_TABLE_NUM]; 813 void * cfg_payload; 814 }; 815 enum { 816 mdp_gamut_fine_mode = 0x1, 817 mdp_gamut_coarse_mode, 818 }; 819 struct mdp_gamut_data_v1_7 { 820 uint32_t mode; 821 uint32_t map_en; 822 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7]; 823 uint32_t * c0_data[MDP_GAMUT_TABLE_NUM_V1_7]; 824 uint32_t * c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7]; 825 uint32_t tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 826 uint32_t * scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM]; 827 }; 828 struct mdp_calib_config_data { 829 uint32_t ops; 830 uint32_t addr; 831 uint32_t data; 832 }; 833 struct mdp_calib_config_buffer { 834 uint32_t ops; 835 uint32_t size; 836 uint32_t * buffer; 837 }; 838 struct mdp_calib_dcm_state { 839 uint32_t ops; 840 uint32_t dcm_state; 841 }; 842 enum { 843 DCM_UNINIT, 844 DCM_UNBLANK, 845 DCM_ENTER, 846 DCM_EXIT, 847 DCM_BLANK, 848 DTM_ENTER, 849 DTM_EXIT, 850 }; 851 #define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000 852 #define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000 853 #define MDSS_PP_SPLIT_MASK 0x30000000 854 #define MDSS_MAX_BL_BRIGHTNESS 255 855 #define AD_BL_LIN_LEN 256 856 #define AD_BL_ATT_LUT_LEN 33 857 #define MDSS_AD_MODE_AUTO_BL 0x0 858 #define MDSS_AD_MODE_AUTO_STR 0x1 859 #define MDSS_AD_MODE_TARG_STR 0x3 860 #define MDSS_AD_MODE_MAN_STR 0x7 861 #define MDSS_AD_MODE_CALIB 0xF 862 #define MDP_PP_AD_INIT 0x10 863 #define MDP_PP_AD_CFG 0x20 864 struct mdss_ad_init { 865 uint32_t asym_lut[33]; 866 uint32_t color_corr_lut[33]; 867 uint8_t i_control[2]; 868 uint16_t black_lvl; 869 uint16_t white_lvl; 870 uint8_t var; 871 uint8_t limit_ampl; 872 uint8_t i_dither; 873 uint8_t slope_max; 874 uint8_t slope_min; 875 uint8_t dither_ctl; 876 uint8_t format; 877 uint8_t auto_size; 878 uint16_t frame_w; 879 uint16_t frame_h; 880 uint8_t logo_v; 881 uint8_t logo_h; 882 uint32_t alpha; 883 uint32_t alpha_base; 884 uint32_t al_thresh; 885 uint32_t bl_lin_len; 886 uint32_t bl_att_len; 887 uint32_t * bl_lin; 888 uint32_t * bl_lin_inv; 889 uint32_t * bl_att_lut; 890 }; 891 #define MDSS_AD_BL_CTRL_MODE_EN 1 892 #define MDSS_AD_BL_CTRL_MODE_DIS 0 893 struct mdss_ad_cfg { 894 uint32_t mode; 895 uint32_t al_calib_lut[33]; 896 uint16_t backlight_min; 897 uint16_t backlight_max; 898 uint16_t backlight_scale; 899 uint16_t amb_light_min; 900 uint16_t filter[2]; 901 uint16_t calib[4]; 902 uint8_t strength_limit; 903 uint8_t t_filter_recursion; 904 uint16_t stab_itr; 905 uint32_t bl_ctrl_mode; 906 }; 907 struct mdss_ad_bl_cfg { 908 uint32_t bl_min_delta; 909 uint32_t bl_low_limit; 910 }; 911 struct mdss_ad_init_cfg { 912 uint32_t ops; 913 union { 914 struct mdss_ad_init init; 915 struct mdss_ad_cfg cfg; 916 } params; 917 }; 918 struct mdss_ad_input { 919 uint32_t mode; 920 union { 921 uint32_t amb_light; 922 uint32_t strength; 923 uint32_t calib_bl; 924 } in; 925 uint32_t output; 926 }; 927 #define MDSS_CALIB_MODE_BL 0x1 928 struct mdss_calib_cfg { 929 uint32_t ops; 930 uint32_t calib_mask; 931 }; 932 enum { 933 mdp_op_pcc_cfg, 934 mdp_op_csc_cfg, 935 mdp_op_lut_cfg, 936 mdp_op_qseed_cfg, 937 mdp_bl_scale_cfg, 938 mdp_op_pa_cfg, 939 mdp_op_pa_v2_cfg, 940 mdp_op_dither_cfg, 941 mdp_op_gamut_cfg, 942 mdp_op_calib_cfg, 943 mdp_op_ad_cfg, 944 mdp_op_ad_input, 945 mdp_op_calib_mode, 946 mdp_op_calib_buffer, 947 mdp_op_calib_dcm_state, 948 mdp_op_max, 949 mdp_op_pa_dither_cfg, 950 mdp_op_ad_bl_cfg, 951 mdp_op_pp_max = 255, 952 }; 953 #define mdp_op_pa_dither_cfg mdp_op_pa_dither_cfg 954 #define mdp_op_pp_max mdp_op_pp_max 955 #define mdp_op_ad_bl_cfg mdp_op_ad_bl_cfg 956 enum { 957 WB_FORMAT_NV12, 958 WB_FORMAT_RGB_565, 959 WB_FORMAT_RGB_888, 960 WB_FORMAT_xRGB_8888, 961 WB_FORMAT_ARGB_8888, 962 WB_FORMAT_BGRA_8888, 963 WB_FORMAT_BGRX_8888, 964 WB_FORMAT_ARGB_8888_INPUT_ALPHA 965 }; 966 struct msmfb_mdp_pp { 967 uint32_t op; 968 union { 969 struct mdp_pcc_cfg_data pcc_cfg_data; 970 struct mdp_csc_cfg_data csc_cfg_data; 971 struct mdp_lut_cfg_data lut_cfg_data; 972 struct mdp_qseed_cfg_data qseed_cfg_data; 973 struct mdp_bl_scale_data bl_scale_data; 974 struct mdp_pa_cfg_data pa_cfg_data; 975 struct mdp_pa_v2_cfg_data pa_v2_cfg_data; 976 struct mdp_dither_cfg_data dither_cfg_data; 977 struct mdp_gamut_cfg_data gamut_cfg_data; 978 struct mdp_calib_config_data calib_cfg; 979 struct mdss_ad_init_cfg ad_init_cfg; 980 struct mdss_calib_cfg mdss_calib_cfg; 981 struct mdss_ad_input ad_input; 982 struct mdp_calib_config_buffer calib_buffer; 983 struct mdp_calib_dcm_state calib_dcm; 984 struct mdss_ad_bl_cfg ad_bl_cfg; 985 } data; 986 }; 987 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1 988 enum { 989 metadata_op_none, 990 metadata_op_base_blend, 991 metadata_op_frame_rate, 992 metadata_op_vic, 993 metadata_op_wb_format, 994 metadata_op_wb_secure, 995 metadata_op_get_caps, 996 metadata_op_crc, 997 metadata_op_get_ion_fd, 998 metadata_op_max 999 }; 1000 struct mdp_blend_cfg { 1001 uint32_t is_premultiplied; 1002 }; 1003 struct mdp_mixer_cfg { 1004 uint32_t writeback_format; 1005 uint32_t alpha; 1006 }; 1007 struct mdss_hw_caps { 1008 uint32_t mdp_rev; 1009 uint8_t rgb_pipes; 1010 uint8_t vig_pipes; 1011 uint8_t dma_pipes; 1012 uint8_t max_smp_cnt; 1013 uint8_t smp_per_pipe; 1014 uint32_t features; 1015 }; 1016 struct msmfb_metadata { 1017 uint32_t op; 1018 uint32_t flags; 1019 union { 1020 struct mdp_misr misr_request; 1021 struct mdp_blend_cfg blend_cfg; 1022 struct mdp_mixer_cfg mixer_cfg; 1023 uint32_t panel_frame_rate; 1024 uint32_t video_info_code; 1025 struct mdss_hw_caps caps; 1026 uint8_t secure_en; 1027 int fbmem_ionfd; 1028 } data; 1029 }; 1030 #define MDP_MAX_FENCE_FD 32 1031 #define MDP_BUF_SYNC_FLAG_WAIT 1 1032 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10 1033 struct mdp_buf_sync { 1034 uint32_t flags; 1035 uint32_t acq_fen_fd_cnt; 1036 uint32_t session_id; 1037 int * acq_fen_fd; 1038 int * rel_fen_fd; 1039 int * retire_fen_fd; 1040 }; 1041 struct mdp_async_blit_req_list { 1042 struct mdp_buf_sync sync; 1043 uint32_t count; 1044 struct mdp_blit_req req[]; 1045 }; 1046 #define MDP_DISPLAY_COMMIT_OVERLAY 1 1047 struct mdp_display_commit { 1048 uint32_t flags; 1049 uint32_t wait_for_finish; 1050 struct fb_var_screeninfo var; 1051 struct mdp_rect l_roi; 1052 struct mdp_rect r_roi; 1053 }; 1054 struct mdp_overlay_list { 1055 uint32_t num_overlays; 1056 struct mdp_overlay * * overlay_list; 1057 uint32_t flags; 1058 uint32_t processed_overlays; 1059 }; 1060 struct mdp_page_protection { 1061 uint32_t page_protection; 1062 }; 1063 struct mdp_mixer_info { 1064 int pndx; 1065 int pnum; 1066 int ptype; 1067 int mixer_num; 1068 int z_order; 1069 }; 1070 #define MAX_PIPE_PER_MIXER 7 1071 struct msmfb_mixer_info_req { 1072 int mixer_num; 1073 int cnt; 1074 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER]; 1075 }; 1076 enum { 1077 DISPLAY_SUBSYSTEM_ID, 1078 ROTATOR_SUBSYSTEM_ID, 1079 }; 1080 enum { 1081 MDP_IOMMU_DOMAIN_CP, 1082 MDP_IOMMU_DOMAIN_NS, 1083 }; 1084 enum { 1085 MDP_WRITEBACK_MIRROR_OFF, 1086 MDP_WRITEBACK_MIRROR_ON, 1087 MDP_WRITEBACK_MIRROR_PAUSE, 1088 MDP_WRITEBACK_MIRROR_RESUME, 1089 }; 1090 enum mdp_color_space { 1091 MDP_CSC_ITU_R_601, 1092 MDP_CSC_ITU_R_601_FR, 1093 MDP_CSC_ITU_R_709, 1094 }; 1095 #define MDP_CSC_ITU_R_2020 (MDP_CSC_ITU_R_709 + 1) 1096 #define MDP_CSC_ITU_R_2020_FR (MDP_CSC_ITU_R_2020 + 1) 1097 enum { 1098 mdp_igc_v1_7 = 1, 1099 mdp_igc_vmax, 1100 mdp_hist_lut_v1_7, 1101 mdp_hist_lut_vmax, 1102 mdp_pgc_v1_7, 1103 mdp_pgc_vmax, 1104 mdp_dither_v1_7, 1105 mdp_dither_vmax, 1106 mdp_gamut_v1_7, 1107 mdp_gamut_vmax, 1108 mdp_pa_v1_7, 1109 mdp_pa_vmax, 1110 mdp_pcc_v1_7, 1111 mdp_pcc_vmax, 1112 mdp_pp_legacy, 1113 mdp_dither_pa_v1_7, 1114 mdp_igc_v3, 1115 mdp_pp_unknown = 255 1116 }; 1117 #define mdp_dither_pa_v1_7 mdp_dither_pa_v1_7 1118 #define mdp_pp_unknown mdp_pp_unknown 1119 #define mdp_igc_v3 mdp_igc_v3 1120 enum { 1121 IGC = 1, 1122 PCC, 1123 GC, 1124 PA, 1125 GAMUT, 1126 DITHER, 1127 QSEED, 1128 HIST_LUT, 1129 HIST, 1130 PP_FEATURE_MAX, 1131 PA_DITHER, 1132 PP_MAX_FEATURES = 25, 1133 }; 1134 #define PA_DITHER PA_DITHER 1135 #define PP_MAX_FEATURES PP_MAX_FEATURES 1136 struct mdp_pp_feature_version { 1137 uint32_t pp_feature; 1138 uint32_t version_info; 1139 }; 1140 #endif 1141