1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef _MSM_NPU_H_ 8 #define _MSM_NPU_H_ 9 #include <linux/types.h> 10 #define MSM_NPU_IOCTL_MAGIC 'n' 11 #define MSM_NPU_GET_INFO _IOWR(MSM_NPU_IOCTL_MAGIC, 1, struct msm_npu_get_info_ioctl) 12 #define MSM_NPU_MAP_BUF _IOWR(MSM_NPU_IOCTL_MAGIC, 2, struct msm_npu_map_buf_ioctl) 13 #define MSM_NPU_UNMAP_BUF _IOWR(MSM_NPU_IOCTL_MAGIC, 3, struct msm_npu_unmap_buf_ioctl) 14 #define MSM_NPU_LOAD_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 4, struct msm_npu_load_network_ioctl) 15 #define MSM_NPU_UNLOAD_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 5, struct msm_npu_unload_network_ioctl) 16 #define MSM_NPU_EXEC_NETWORK _IOWR(MSM_NPU_IOCTL_MAGIC, 6, struct msm_npu_exec_network_ioctl) 17 #define MSM_NPU_LOAD_NETWORK_V2 _IOWR(MSM_NPU_IOCTL_MAGIC, 7, struct msm_npu_load_network_ioctl_v2) 18 #define MSM_NPU_EXEC_NETWORK_V2 _IOWR(MSM_NPU_IOCTL_MAGIC, 8, struct msm_npu_exec_network_ioctl_v2) 19 #define MSM_NPU_RECEIVE_EVENT _IOR(MSM_NPU_IOCTL_MAGIC, 9, struct msm_npu_event) 20 #define MSM_NPU_SET_PROP _IOW(MSM_NPU_IOCTL_MAGIC, 10, struct msm_npu_property) 21 #define MSM_NPU_GET_PROP _IOW(MSM_NPU_IOCTL_MAGIC, 11, struct msm_npu_property) 22 #define MSM_NPU_EVENT_TYPE_START 0x10000000 23 #define MSM_NPU_EVENT_TYPE_EXEC_DONE (MSM_NPU_EVENT_TYPE_START + 1) 24 #define MSM_NPU_EVENT_TYPE_EXEC_V2_DONE (MSM_NPU_EVENT_TYPE_START + 2) 25 #define MSM_NPU_EVENT_TYPE_SSR (MSM_NPU_EVENT_TYPE_START + 3) 26 #define MSM_NPU_MAX_INPUT_LAYER_NUM 8 27 #define MSM_NPU_MAX_OUTPUT_LAYER_NUM 4 28 #define MSM_NPU_MAX_PATCH_LAYER_NUM (MSM_NPU_MAX_INPUT_LAYER_NUM + MSM_NPU_MAX_OUTPUT_LAYER_NUM) 29 #define MSM_NPU_PROP_ID_START 0x100 30 #define MSM_NPU_PROP_ID_FW_STATE (MSM_NPU_PROP_ID_START + 0) 31 #define MSM_NPU_PROP_ID_PERF_MODE (MSM_NPU_PROP_ID_START + 1) 32 #define MSM_NPU_PROP_ID_PERF_MODE_MAX (MSM_NPU_PROP_ID_START + 2) 33 #define MSM_NPU_PROP_ID_DRV_VERSION (MSM_NPU_PROP_ID_START + 3) 34 #define MSM_NPU_PROP_ID_HARDWARE_VERSION (MSM_NPU_PROP_ID_START + 4) 35 #define MSM_NPU_PROP_ID_IPC_QUEUE_INFO (MSM_NPU_PROP_ID_START + 5) 36 #define MSM_NPU_PROP_ID_DRV_FEATURE (MSM_NPU_PROP_ID_START + 6) 37 #define MSM_NPU_FW_PROP_ID_START 0x1000 38 #define MSM_NPU_PROP_ID_DCVS_MODE (MSM_NPU_FW_PROP_ID_START + 0) 39 #define MSM_NPU_PROP_ID_DCVS_MODE_MAX (MSM_NPU_FW_PROP_ID_START + 1) 40 #define MSM_NPU_PROP_ID_CLK_GATING_MODE (MSM_NPU_FW_PROP_ID_START + 2) 41 #define MSM_NPU_PROP_ID_HW_VERSION (MSM_NPU_FW_PROP_ID_START + 3) 42 #define MSM_NPU_PROP_ID_FW_VERSION (MSM_NPU_FW_PROP_ID_START + 4) 43 #define MSM_NPU_PROP_ID_FW_GETCAPS (MSM_NPU_FW_PROP_ID_START + 5) 44 #define MSM_NPU_FEATURE_MULTI_EXECUTE 0x1 45 #define MSM_NPU_FEATURE_ASYNC_EXECUTE 0x2 46 #define MSM_NPU_FEATURE_DSP_SID_MAPPED 0x8 47 #define PROP_PARAM_MAX_SIZE 8 48 struct msm_npu_patch_info { 49 uint32_t chunk_id; 50 uint16_t instruction_size_in_bytes; 51 uint16_t variable_size_in_bits; 52 uint16_t shift_value_in_bits; 53 uint32_t loc_offset; 54 }; 55 struct msm_npu_layer { 56 uint32_t layer_id; 57 struct msm_npu_patch_info patch_info; 58 int32_t buf_hdl; 59 uint32_t buf_size; 60 uint64_t buf_phys_addr; 61 }; 62 struct msm_npu_patch_info_v2 { 63 uint32_t value; 64 uint32_t chunk_id; 65 uint32_t instruction_size_in_bytes; 66 uint32_t variable_size_in_bits; 67 uint32_t shift_value_in_bits; 68 uint32_t loc_offset; 69 }; 70 struct msm_npu_patch_buf_info { 71 uint64_t buf_phys_addr; 72 uint32_t buf_id; 73 }; 74 struct msm_npu_map_buf_ioctl { 75 int32_t buf_ion_hdl; 76 uint32_t size; 77 uint64_t npu_phys_addr; 78 }; 79 struct msm_npu_unmap_buf_ioctl { 80 int32_t buf_ion_hdl; 81 uint64_t npu_phys_addr; 82 }; 83 struct msm_npu_get_info_ioctl { 84 uint32_t firmware_version; 85 uint32_t flags; 86 }; 87 struct msm_npu_load_network_ioctl { 88 int32_t buf_ion_hdl; 89 uint64_t buf_phys_addr; 90 uint32_t buf_size; 91 uint32_t first_block_size; 92 uint32_t flags; 93 uint32_t network_hdl; 94 uint32_t priority; 95 uint32_t perf_mode; 96 }; 97 struct msm_npu_load_network_ioctl_v2 { 98 uint64_t buf_phys_addr; 99 uint64_t patch_info; 100 int32_t buf_ion_hdl; 101 uint32_t buf_size; 102 uint32_t first_block_size; 103 uint32_t flags; 104 uint32_t network_hdl; 105 uint32_t priority; 106 uint32_t perf_mode; 107 uint32_t num_layers; 108 uint32_t patch_info_num; 109 uint32_t reserved; 110 }; 111 struct msm_npu_unload_network_ioctl { 112 uint32_t network_hdl; 113 }; 114 struct msm_npu_exec_network_ioctl { 115 uint32_t network_hdl; 116 uint32_t input_layer_num; 117 struct msm_npu_layer input_layers[MSM_NPU_MAX_INPUT_LAYER_NUM]; 118 uint32_t output_layer_num; 119 struct msm_npu_layer output_layers[MSM_NPU_MAX_OUTPUT_LAYER_NUM]; 120 uint32_t patching_required; 121 uint32_t async; 122 uint32_t flags; 123 }; 124 struct msm_npu_exec_network_ioctl_v2 { 125 uint64_t stats_buf_addr; 126 uint64_t patch_buf_info; 127 uint32_t network_hdl; 128 uint32_t async; 129 uint32_t flags; 130 uint32_t stats_buf_size; 131 uint32_t patch_buf_info_num; 132 uint32_t reserved; 133 }; 134 struct msm_npu_event_execute_done { 135 uint32_t network_hdl; 136 int32_t exec_result; 137 }; 138 struct msm_npu_event_execute_v2_done { 139 uint32_t network_hdl; 140 int32_t exec_result; 141 uint32_t stats_buf_size; 142 }; 143 struct msm_npu_event_ssr { 144 uint32_t network_hdl; 145 }; 146 struct msm_npu_event { 147 uint32_t type; 148 union { 149 struct msm_npu_event_execute_done exec_done; 150 struct msm_npu_event_execute_v2_done exec_v2_done; 151 struct msm_npu_event_ssr ssr; 152 uint8_t data[128]; 153 } u; 154 uint32_t reserved[4]; 155 }; 156 struct msm_npu_property { 157 uint32_t prop_id; 158 uint32_t num_of_params; 159 uint32_t network_hdl; 160 uint32_t prop_param[PROP_PARAM_MAX_SIZE]; 161 }; 162 #endif 163