1 /* 2 * This file is auto-generated. Modifications will be lost. 3 * 4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ 5 * for more information. 6 */ 7 #ifndef __UAPI_CAM_ISP_H__ 8 #define __UAPI_CAM_ISP_H__ 9 #include <media/cam_defs.h> 10 #include <media/cam_isp_vfe.h> 11 #include <media/cam_isp_ife.h> 12 #include <media/cam_cpas.h> 13 #define CAM_ISP_DEV_NAME "cam-isp" 14 #define CAM_ISP_HW_BASE 0 15 #define CAM_ISP_HW_CSID 1 16 #define CAM_ISP_HW_VFE 2 17 #define CAM_ISP_HW_IFE 3 18 #define CAM_ISP_HW_ISPIF 4 19 #define CAM_ISP_HW_MAX 5 20 #define CAM_ISP_PATTERN_BAYER_RGRGRG 0 21 #define CAM_ISP_PATTERN_BAYER_GRGRGR 1 22 #define CAM_ISP_PATTERN_BAYER_BGBGBG 2 23 #define CAM_ISP_PATTERN_BAYER_GBGBGB 3 24 #define CAM_ISP_PATTERN_YUV_YCBYCR 4 25 #define CAM_ISP_PATTERN_YUV_YCRYCB 5 26 #define CAM_ISP_PATTERN_YUV_CBYCRY 6 27 #define CAM_ISP_PATTERN_YUV_CRYCBY 7 28 #define CAM_ISP_PATTERN_MAX 8 29 #define CAM_ISP_RES_USAGE_SINGLE 0 30 #define CAM_ISP_RES_USAGE_DUAL 1 31 #define CAM_ISP_RES_USAGE_MAX 2 32 #define CAM_ISP_RES_ID_PORT 0 33 #define CAM_ISP_RES_ID_CLK 1 34 #define CAM_ISP_RES_ID_MAX 2 35 #define CAM_ISP_LANE_TYPE_DPHY 0 36 #define CAM_ISP_LANE_TYPE_CPHY 1 37 #define CAM_ISP_LANE_TYPE_MAX 2 38 #define CAM_ISP_RES_COMP_GROUP_NONE 0 39 #define CAM_ISP_RES_COMP_GROUP_ID_0 1 40 #define CAM_ISP_RES_COMP_GROUP_ID_1 2 41 #define CAM_ISP_RES_COMP_GROUP_ID_2 3 42 #define CAM_ISP_RES_COMP_GROUP_ID_3 4 43 #define CAM_ISP_RES_COMP_GROUP_ID_4 5 44 #define CAM_ISP_RES_COMP_GROUP_ID_5 6 45 #define CAM_ISP_RES_COMP_GROUP_ID_MAX 6 46 #define CAM_ISP_PACKET_OP_BASE 0 47 #define CAM_ISP_PACKET_INIT_DEV 1 48 #define CAM_ISP_PACKET_UPDATE_DEV 2 49 #define CAM_ISP_PACKET_OP_MAX 3 50 #define CAM_ISP_PACKET_META_BASE 0 51 #define CAM_ISP_PACKET_META_LEFT 1 52 #define CAM_ISP_PACKET_META_RIGHT 2 53 #define CAM_ISP_PACKET_META_COMMON 3 54 #define CAM_ISP_PACKET_META_DMI_LEFT 4 55 #define CAM_ISP_PACKET_META_DMI_RIGHT 5 56 #define CAM_ISP_PACKET_META_DMI_COMMON 6 57 #define CAM_ISP_PACKET_META_CLOCK 7 58 #define CAM_ISP_PACKET_META_CSID 8 59 #define CAM_ISP_PACKET_META_DUAL_CONFIG 9 60 #define CAM_ISP_PACKET_META_GENERIC_BLOB_LEFT 10 61 #define CAM_ISP_PACKET_META_GENERIC_BLOB_RIGHT 11 62 #define CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON 12 63 #define CAM_ISP_PACKET_META_REG_DUMP_PER_REQUEST 13 64 #define CAM_ISP_PACKET_META_REG_DUMP_ON_FLUSH 14 65 #define CAM_ISP_PACKET_META_REG_DUMP_ON_ERROR 15 66 #define CAM_ISP_DSP_MODE_NONE 0 67 #define CAM_ISP_DSP_MODE_ONE_WAY 1 68 #define CAM_ISP_DSP_MODE_ROUND 2 69 #define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG 0 70 #define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1 71 #define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG 2 72 #define CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG 3 73 #define CAM_ISP_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG 4 74 #define CAM_ISP_GENERIC_BLOB_TYPE_FE_CONFIG 5 75 #define CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG_V2 6 76 #define CAM_ISP_GENERIC_BLOB_TYPE_IFE_CORE_CONFIG 7 77 #define CAM_ISP_GENERIC_BLOB_TYPE_VFE_OUT_CONFIG 8 78 #define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG_V2 9 79 #define CAM_ISP_GENERIC_BLOB_TYPE_CSID_CONFIG 10 80 #define CAM_ISP_GENERIC_BLOB_TYPE_SENSOR_DIMENSION_CONFIG 11 81 #define CAM_ISP_GENERIC_BLOB_TYPE_CSID_QCFA_CONFIG 12 82 #define CAM_ISP_VC_DT_CFG 4 83 #define CAM_ISP_IFE0_HW 0x1 84 #define CAM_ISP_IFE1_HW 0x2 85 #define CAM_ISP_IFE0_LITE_HW 0x4 86 #define CAM_ISP_IFE1_LITE_HW 0x8 87 #define CAM_ISP_IFE2_LITE_HW 0x10 88 #define CAM_ISP_IFE2_HW 0x100 89 #define CAM_ISP_PXL_PATH 0x1 90 #define CAM_ISP_PPP_PATH 0x2 91 #define CAM_ISP_LCR_PATH 0x4 92 #define CAM_ISP_RDI0_PATH 0x8 93 #define CAM_ISP_RDI1_PATH 0x10 94 #define CAM_ISP_RDI2_PATH 0x20 95 #define CAM_ISP_RDI3_PATH 0x40 96 #define CAM_ISP_USAGE_INVALID 0 97 #define CAM_ISP_USAGE_LEFT_PX 1 98 #define CAM_ISP_USAGE_RIGHT_PX 2 99 #define CAM_ISP_USAGE_RDI 3 100 #define CAM_ISP_ACQ_CUSTOM_NONE 0 101 #define CAM_ISP_ACQ_CUSTOM_PRIMARY 1 102 #define CAM_ISP_ACQ_CUSTOM_SECONDARY 2 103 #define CAM_IFE_CSID_RDI_MAX 4 104 struct cam_isp_dev_cap_info { 105 uint32_t hw_type; 106 uint32_t reserved; 107 struct cam_hw_version hw_version; 108 }; 109 struct cam_isp_query_cap_cmd { 110 struct cam_iommu_handle device_iommu; 111 struct cam_iommu_handle cdm_iommu; 112 int32_t num_dev; 113 uint32_t reserved; 114 struct cam_isp_dev_cap_info dev_caps[CAM_ISP_HW_MAX]; 115 }; 116 struct cam_isp_out_port_info { 117 uint32_t res_type; 118 uint32_t format; 119 uint32_t width; 120 uint32_t height; 121 uint32_t comp_grp_id; 122 uint32_t split_point; 123 uint32_t secure_mode; 124 uint32_t reserved; 125 }; 126 struct cam_isp_out_port_info_v2 { 127 uint32_t res_type; 128 uint32_t format; 129 uint32_t width; 130 uint32_t height; 131 uint32_t comp_grp_id; 132 uint32_t split_point; 133 uint32_t secure_mode; 134 uint32_t wm_mode; 135 uint32_t out_port_res1; 136 uint32_t out_port_res2; 137 }; 138 struct cam_isp_in_port_info { 139 uint32_t res_type; 140 uint32_t lane_type; 141 uint32_t lane_num; 142 uint32_t lane_cfg; 143 uint32_t vc; 144 uint32_t dt; 145 uint32_t format; 146 uint32_t test_pattern; 147 uint32_t usage_type; 148 uint32_t left_start; 149 uint32_t left_stop; 150 uint32_t left_width; 151 uint32_t right_start; 152 uint32_t right_stop; 153 uint32_t right_width; 154 uint32_t line_start; 155 uint32_t line_stop; 156 uint32_t height; 157 uint32_t pixel_clk; 158 uint32_t batch_size; 159 uint32_t dsp_mode; 160 uint32_t hbi_cnt; 161 uint32_t reserved; 162 uint32_t num_out_res; 163 struct cam_isp_out_port_info data[1]; 164 }; 165 struct cam_isp_in_port_info_v2 { 166 uint32_t res_type; 167 uint32_t lane_type; 168 uint32_t lane_num; 169 uint32_t lane_cfg; 170 uint32_t vc[CAM_ISP_VC_DT_CFG]; 171 uint32_t dt[CAM_ISP_VC_DT_CFG]; 172 uint32_t num_valid_vc_dt; 173 uint32_t format; 174 uint32_t test_pattern; 175 uint32_t usage_type; 176 uint32_t left_start; 177 uint32_t left_stop; 178 uint32_t left_width; 179 uint32_t right_start; 180 uint32_t right_stop; 181 uint32_t right_width; 182 uint32_t line_start; 183 uint32_t line_stop; 184 uint32_t height; 185 uint32_t pixel_clk; 186 uint32_t batch_size; 187 uint32_t dsp_mode; 188 uint32_t hbi_cnt; 189 uint32_t cust_node; 190 uint32_t num_out_res; 191 uint32_t offline_mode; 192 uint32_t horizontal_bin; 193 uint32_t qcfa_bin; 194 uint32_t csid_res_1; 195 uint32_t csid_res_2; 196 uint32_t ife_res_1; 197 uint32_t ife_res_2; 198 struct cam_isp_out_port_info_v2 data[1]; 199 }; 200 struct cam_isp_resource { 201 uint32_t resource_id; 202 uint32_t length; 203 uint32_t handle_type; 204 uint32_t reserved; 205 uint64_t res_hdl; 206 }; 207 struct cam_isp_port_hfr_config { 208 uint32_t resource_type; 209 uint32_t subsample_pattern; 210 uint32_t subsample_period; 211 uint32_t framedrop_pattern; 212 uint32_t framedrop_period; 213 uint32_t reserved; 214 } __attribute__((packed)); 215 struct cam_isp_resource_hfr_config { 216 uint32_t num_ports; 217 uint32_t reserved; 218 struct cam_isp_port_hfr_config port_hfr_config[1]; 219 } __attribute__((packed)); 220 struct cam_isp_dual_split_params { 221 uint32_t split_point; 222 uint32_t right_padding; 223 uint32_t left_padding; 224 uint32_t reserved; 225 }; 226 struct cam_isp_dual_stripe_config { 227 uint32_t offset; 228 uint32_t width; 229 uint32_t tileconfig; 230 uint32_t port_id; 231 }; 232 struct cam_isp_dual_config { 233 uint32_t num_ports; 234 uint32_t reserved; 235 struct cam_isp_dual_split_params split_params; 236 struct cam_isp_dual_stripe_config stripes[1]; 237 } __attribute__((packed)); 238 struct cam_isp_clock_config { 239 uint32_t usage_type; 240 uint32_t num_rdi; 241 uint64_t left_pix_hz; 242 uint64_t right_pix_hz; 243 uint64_t rdi_hz[1]; 244 } __attribute__((packed)); 245 struct cam_isp_csid_clock_config { 246 uint64_t csid_clock; 247 } __attribute__((packed)); 248 struct cam_isp_csid_qcfa_config { 249 uint32_t csid_binning; 250 } __attribute__((packed)); 251 struct cam_isp_bw_vote { 252 uint32_t resource_id; 253 uint32_t reserved; 254 uint64_t cam_bw_bps; 255 uint64_t ext_bw_bps; 256 } __attribute__((packed)); 257 struct cam_isp_bw_config { 258 uint32_t usage_type; 259 uint32_t num_rdi; 260 struct cam_isp_bw_vote left_pix_vote; 261 struct cam_isp_bw_vote right_pix_vote; 262 struct cam_isp_bw_vote rdi_vote[1]; 263 } __attribute__((packed)); 264 struct cam_isp_bw_config_v2 { 265 uint32_t usage_type; 266 uint32_t num_paths; 267 struct cam_axi_per_path_bw_vote axi_path[1]; 268 } __attribute__((packed)); 269 struct cam_fe_config { 270 uint64_t version; 271 uint32_t min_vbi; 272 uint32_t fs_mode; 273 uint32_t fs_line_sync_en; 274 uint32_t hbi_count; 275 uint32_t fs_sync_enable; 276 uint32_t go_cmd_sel; 277 uint32_t client_enable; 278 uint32_t source_addr; 279 uint32_t width; 280 uint32_t height; 281 uint32_t stride; 282 uint32_t format; 283 uint32_t unpacker_cfg; 284 uint32_t latency_buf_size; 285 } __attribute__((packed)); 286 struct cam_isp_sensor_dimension { 287 uint32_t width; 288 uint32_t height; 289 uint32_t measure_enabled; 290 } __attribute__((packed)); 291 struct cam_isp_sensor_config { 292 struct cam_isp_sensor_dimension ppp_path; 293 struct cam_isp_sensor_dimension ipp_path; 294 struct cam_isp_sensor_dimension rdi_path[CAM_IFE_CSID_RDI_MAX]; 295 uint32_t hbi; 296 uint32_t vbi; 297 } __attribute__((packed)); 298 struct cam_isp_core_config { 299 uint32_t version; 300 uint32_t vid_ds16_r2pd; 301 uint32_t vid_ds4_r2pd; 302 uint32_t disp_ds16_r2pd; 303 uint32_t disp_ds4_r2pd; 304 uint32_t dsp_streaming_tap_point; 305 uint32_t ihist_src_sel; 306 uint32_t hdr_be_src_sel; 307 uint32_t hdr_bhist_src_sel; 308 uint32_t input_mux_sel_pdaf; 309 uint32_t input_mux_sel_pp; 310 uint32_t reserved; 311 } __attribute__((packed)); 312 struct cam_isp_acquire_hw_info { 313 uint16_t common_info_version; 314 uint16_t common_info_size; 315 uint32_t common_info_offset; 316 uint32_t num_inputs; 317 uint32_t input_info_version; 318 uint32_t input_info_size; 319 uint32_t input_info_offset; 320 uint64_t data; 321 }; 322 struct cam_isp_vfe_wm_config { 323 uint32_t port_type; 324 uint32_t wm_mode; 325 uint32_t h_init; 326 uint32_t height; 327 uint32_t width; 328 uint32_t virtual_frame_en; 329 uint32_t stride; 330 uint32_t offset; 331 uint32_t reserved_1; 332 uint32_t reserved_2; 333 uint32_t reserved_3; 334 uint32_t reserved_4; 335 }; 336 struct cam_isp_vfe_out_config { 337 uint32_t num_ports; 338 uint32_t reserved; 339 struct cam_isp_vfe_wm_config wm_config[1]; 340 }; 341 struct cam_isp_csid_epd_config { 342 uint32_t is_epd_supported; 343 }; 344 #define CAM_ISP_ACQUIRE_COMMON_VER0 0x1000 345 #define CAM_ISP_ACQUIRE_COMMON_SIZE_VER0 0x0 346 #define CAM_ISP_ACQUIRE_INPUT_VER0 0x2000 347 #define CAM_ISP_ACQUIRE_INPUT_SIZE_VER0 sizeof(struct cam_isp_in_port_info) 348 #define CAM_ISP_ACQUIRE_OUT_VER0 0x3000 349 #define CAM_ISP_ACQUIRE_OUT_SIZE_VER0 sizeof(struct cam_isp_out_port_info) 350 #endif 351