1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ 2 /* 3 * Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef _SDE_DRM_H_ 8 #define _SDE_DRM_H_ 9 10 #include "drm.h" 11 12 /* Total number of supported color planes */ 13 #define SDE_MAX_PLANES 4 14 15 /* Total number of parameterized detail enhancer mapping curves */ 16 #define SDE_MAX_DE_CURVES 3 17 18 /* Y/RGB and UV filter configuration */ 19 #define FILTER_EDGE_DIRECTED_2D 0x0 20 #define FILTER_CIRCULAR_2D 0x1 21 #define FILTER_SEPARABLE_1D 0x2 22 #define FILTER_BILINEAR 0x3 23 24 /* Alpha filters */ 25 #define FILTER_ALPHA_DROP_REPEAT 0x0 26 #define FILTER_ALPHA_BILINEAR 0x1 27 #define FILTER_ALPHA_2D 0x3 28 29 /* Blend filters */ 30 #define FILTER_BLEND_CIRCULAR_2D 0x0 31 #define FILTER_BLEND_SEPARABLE_1D 0x1 32 33 /* LUT configuration flags */ 34 #define SCALER_LUT_SWAP 0x1 35 #define SCALER_LUT_DIR_WR 0x2 36 #define SCALER_LUT_Y_CIR_WR 0x4 37 #define SCALER_LUT_UV_CIR_WR 0x8 38 #define SCALER_LUT_Y_SEP_WR 0x10 39 #define SCALER_LUT_UV_SEP_WR 0x20 40 41 /** 42 * Blend operations for "blend_op" property 43 * 44 * @SDE_DRM_BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. 45 * @SDE_DRM_BLEND_OP_OPAQUE: Apply a constant blend operation. The layer 46 * would appear opaque in case fg plane alpha 47 * is 0xff. 48 * @SDE_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already 49 * has alpha pre-multiplication done. If the fg 50 * plane alpha is less than 0xff, apply 51 * modulation as well. This operation is 52 * intended on layers having alpha channel. 53 * @SDE_DRM_BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not 54 * alpha pre-multiplied. Apply 55 * pre-multiplication. If fg plane alpha is 56 * less than 0xff, apply modulation as well. 57 * @SDE_DRM_BLEND_OP_LAYER_COLOR: Blend_op type for layer color component, 58 * apply a constant blend operation. 59 * @SDE_DRM_BLEND_OP_MAX: Used to track maximum blend operation 60 * possible by mdp. 61 */ 62 #define SDE_DRM_BLEND_OP_NOT_DEFINED 0 63 #define SDE_DRM_BLEND_OP_OPAQUE 1 64 #define SDE_DRM_BLEND_OP_PREMULTIPLIED 2 65 #define SDE_DRM_BLEND_OP_COVERAGE 3 66 #define SDE_DRM_BLEND_OP_LAYER_COLOR 4 67 #define SDE_DRM_BLEND_OP_MAX 5 68 69 /** 70 * Bit masks for "src_config" property 71 * construct bitmask via (1UL << SDE_DRM_<flag>) 72 */ 73 #define SDE_DRM_DEINTERLACE 0 /* Specifies interlaced input */ 74 75 /* DRM bitmasks are restricted to 0..63 */ 76 #define SDE_DRM_BITMASK_COUNT 64 77 78 /** 79 * Framebuffer modes for "fb_translation_mode" PLANE and CONNECTOR property 80 * 81 * @SDE_DRM_FB_NON_SEC: IOMMU configuration for this framebuffer mode 82 * is non-secure domain and requires 83 * both stage I and stage II translations when 84 * this buffer is accessed by the display HW. 85 * This is the default mode of all frambuffers. 86 * @SDE_DRM_FB_SEC: IOMMU configuration for this framebuffer mode 87 * is secure domain and requires 88 * both stage I and stage II translations when 89 * this buffer is accessed by the display HW. 90 * @SDE_DRM_FB_NON_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode 91 * is non-secure domain and requires 92 * only stage II translation when 93 * this buffer is accessed by the display HW. 94 * @SDE_DRM_FB_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode 95 * is secure domain and requires 96 * only stage II translation when 97 * this buffer is accessed by the display HW. 98 */ 99 100 #define SDE_DRM_FB_NON_SEC 0 101 #define SDE_DRM_FB_SEC 1 102 #define SDE_DRM_FB_NON_SEC_DIR_TRANS 2 103 #define SDE_DRM_FB_SEC_DIR_TRANS 3 104 105 /** 106 * Secure levels for "security_level" CRTC property. 107 * CRTC property which specifies what plane types 108 * can be attached to this CRTC. Plane component 109 * derives the plane type based on the FB_MODE. 110 * @ SDE_DRM_SEC_NON_SEC: Both Secure and non-secure plane types can be 111 * attached to this CRTC. This is the default state of 112 * the CRTC. 113 * @ SDE_DRM_SEC_ONLY: Only secure planes can be added to this CRTC. If a 114 * CRTC is instructed to be in this mode it follows the 115 * platform dependent restrictions. 116 */ 117 #define SDE_DRM_SEC_NON_SEC 0 118 #define SDE_DRM_SEC_ONLY 1 119 120 /** 121 * struct sde_drm_pix_ext_v1 - version 1 of pixel ext structure 122 * @num_ext_pxls_lr: Number of total horizontal pixels 123 * @num_ext_pxls_tb: Number of total vertical lines 124 * @left_ftch: Number of extra pixels to overfetch from left 125 * @right_ftch: Number of extra pixels to overfetch from right 126 * @top_ftch: Number of extra lines to overfetch from top 127 * @btm_ftch: Number of extra lines to overfetch from bottom 128 * @left_rpt: Number of extra pixels to repeat from left 129 * @right_rpt: Number of extra pixels to repeat from right 130 * @top_rpt: Number of extra lines to repeat from top 131 * @btm_rpt: Number of extra lines to repeat from bottom 132 */ 133 struct sde_drm_pix_ext_v1 { 134 /* 135 * Number of pixels ext in left, right, top and bottom direction 136 * for all color components. 137 */ 138 int32_t num_ext_pxls_lr[SDE_MAX_PLANES]; 139 int32_t num_ext_pxls_tb[SDE_MAX_PLANES]; 140 141 /* 142 * Number of pixels needs to be overfetched in left, right, top 143 * and bottom directions from source image for scaling. 144 */ 145 int32_t left_ftch[SDE_MAX_PLANES]; 146 int32_t right_ftch[SDE_MAX_PLANES]; 147 int32_t top_ftch[SDE_MAX_PLANES]; 148 int32_t btm_ftch[SDE_MAX_PLANES]; 149 /* 150 * Number of pixels needs to be repeated in left, right, top and 151 * bottom directions for scaling. 152 */ 153 int32_t left_rpt[SDE_MAX_PLANES]; 154 int32_t right_rpt[SDE_MAX_PLANES]; 155 int32_t top_rpt[SDE_MAX_PLANES]; 156 int32_t btm_rpt[SDE_MAX_PLANES]; 157 158 }; 159 160 /** 161 * struct sde_drm_scaler_v1 - version 1 of struct sde_drm_scaler 162 * @lr: Pixel extension settings for left/right 163 * @tb: Pixel extension settings for top/botton 164 * @init_phase_x: Initial scaler phase values for x 165 * @phase_step_x: Phase step values for x 166 * @init_phase_y: Initial scaler phase values for y 167 * @phase_step_y: Phase step values for y 168 * @horz_filter: Horizontal filter array 169 * @vert_filter: Vertical filter array 170 */ 171 struct sde_drm_scaler_v1 { 172 /* 173 * Pix ext settings 174 */ 175 struct sde_drm_pix_ext_v1 pe; 176 /* 177 * Phase settings 178 */ 179 int32_t init_phase_x[SDE_MAX_PLANES]; 180 int32_t phase_step_x[SDE_MAX_PLANES]; 181 int32_t init_phase_y[SDE_MAX_PLANES]; 182 int32_t phase_step_y[SDE_MAX_PLANES]; 183 184 /* 185 * Filter type to be used for scaling in horizontal and vertical 186 * directions 187 */ 188 uint32_t horz_filter[SDE_MAX_PLANES]; 189 uint32_t vert_filter[SDE_MAX_PLANES]; 190 }; 191 192 /** 193 * struct sde_drm_de_v1 - version 1 of detail enhancer structure 194 * @enable: Enables/disables detail enhancer 195 * @sharpen_level1: Sharpening strength for noise 196 * @sharpen_level2: Sharpening strength for context 197 * @clip: Clip coefficient 198 * @limit: Detail enhancer limit factor 199 * @thr_quiet: Quite zone threshold 200 * @thr_dieout: Die-out zone threshold 201 * @thr_low: Linear zone left threshold 202 * @thr_high: Linear zone right threshold 203 * @prec_shift: Detail enhancer precision 204 * @adjust_a: Mapping curves A coefficients 205 * @adjust_b: Mapping curves B coefficients 206 * @adjust_c: Mapping curves C coefficients 207 */ 208 struct sde_drm_de_v1 { 209 uint32_t enable; 210 int16_t sharpen_level1; 211 int16_t sharpen_level2; 212 uint16_t clip; 213 uint16_t limit; 214 uint16_t thr_quiet; 215 uint16_t thr_dieout; 216 uint16_t thr_low; 217 uint16_t thr_high; 218 uint16_t prec_shift; 219 int16_t adjust_a[SDE_MAX_DE_CURVES]; 220 int16_t adjust_b[SDE_MAX_DE_CURVES]; 221 int16_t adjust_c[SDE_MAX_DE_CURVES]; 222 }; 223 224 /* 225 * Scaler configuration flags 226 */ 227 228 /* Disable dynamic expansion */ 229 #define SDE_DYN_EXP_DISABLE 0x1 230 231 #define SDE_DRM_QSEED3LITE 232 #define SDE_DRM_QSEED4 233 #define SDE_DRM_INLINE_PREDOWNSCALE 234 235 /** 236 * struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler 237 * @enable: Scaler enable 238 * @dir_en: Detail enhancer enable 239 * @pe: Pixel extension settings 240 * @horz_decimate: Horizontal decimation factor 241 * @vert_decimate: Vertical decimation factor 242 * @init_phase_x: Initial scaler phase values for x 243 * @phase_step_x: Phase step values for x 244 * @init_phase_y: Initial scaler phase values for y 245 * @phase_step_y: Phase step values for y 246 * @preload_x: Horizontal preload value 247 * @preload_y: Vertical preload value 248 * @src_width: Source width 249 * @src_height: Source height 250 * @dst_width: Destination width 251 * @dst_height: Destination height 252 * @y_rgb_filter_cfg: Y/RGB plane filter configuration 253 * @uv_filter_cfg: UV plane filter configuration 254 * @alpha_filter_cfg: Alpha filter configuration 255 * @blend_cfg: Selection of blend coefficients 256 * @lut_flag: LUT configuration flags 257 * @dir_lut_idx: 2d 4x4 LUT index 258 * @y_rgb_cir_lut_idx: Y/RGB circular LUT index 259 * @uv_cir_lut_idx: UV circular LUT index 260 * @y_rgb_sep_lut_idx: Y/RGB separable LUT index 261 * @uv_sep_lut_idx: UV separable LUT index 262 * @de: Detail enhancer settings 263 * @dir_weight: Directional Weight 264 * @unsharp_mask_blend: Unsharp Blend Filter Ratio 265 * @de_blend: Ratio of two unsharp mask filters 266 * @flags: Scaler configuration flags 267 * @pre_downscale_x_0 Pre-downscale ratio, x-direction, plane 0(Y/RGB) 268 * @pre_downscale_x_1 Pre-downscale ratio, x-direction, plane 1(UV) 269 * @pre_downscale_y_0 Pre-downscale ratio, y-direction, plane 0(Y/RGB) 270 * @pre_downscale_y_1 Pre-downscale ratio, y-direction, plane 1(UV) 271 */ 272 struct sde_drm_scaler_v2 { 273 /* 274 * General definitions 275 */ 276 uint32_t enable; 277 uint32_t dir_en; 278 279 /* 280 * Pix ext settings 281 */ 282 struct sde_drm_pix_ext_v1 pe; 283 284 /* 285 * Decimation settings 286 */ 287 uint32_t horz_decimate; 288 uint32_t vert_decimate; 289 290 /* 291 * Phase settings 292 */ 293 int32_t init_phase_x[SDE_MAX_PLANES]; 294 int32_t phase_step_x[SDE_MAX_PLANES]; 295 int32_t init_phase_y[SDE_MAX_PLANES]; 296 int32_t phase_step_y[SDE_MAX_PLANES]; 297 298 uint32_t preload_x[SDE_MAX_PLANES]; 299 uint32_t preload_y[SDE_MAX_PLANES]; 300 uint32_t src_width[SDE_MAX_PLANES]; 301 uint32_t src_height[SDE_MAX_PLANES]; 302 303 uint32_t dst_width; 304 uint32_t dst_height; 305 306 uint32_t y_rgb_filter_cfg; 307 uint32_t uv_filter_cfg; 308 uint32_t alpha_filter_cfg; 309 uint32_t blend_cfg; 310 311 uint32_t lut_flag; 312 uint32_t dir_lut_idx; 313 314 /* for Y(RGB) and UV planes*/ 315 uint32_t y_rgb_cir_lut_idx; 316 uint32_t uv_cir_lut_idx; 317 uint32_t y_rgb_sep_lut_idx; 318 uint32_t uv_sep_lut_idx; 319 320 /* 321 * Detail enhancer settings 322 */ 323 struct sde_drm_de_v1 de; 324 uint32_t dir_weight; 325 uint32_t unsharp_mask_blend; 326 uint32_t de_blend; 327 uint32_t flags; 328 329 /* 330 * Inline pre-downscale settings 331 */ 332 uint32_t pre_downscale_x_0; 333 uint32_t pre_downscale_x_1; 334 uint32_t pre_downscale_y_0; 335 uint32_t pre_downscale_y_1; 336 }; 337 338 /* Number of dest scalers supported */ 339 #define SDE_MAX_DS_COUNT 2 340 341 /* 342 * Destination scaler flag config 343 */ 344 #define SDE_DRM_DESTSCALER_ENABLE 0x1 345 #define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2 346 #define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4 347 #define SDE_DRM_DESTSCALER_PU_ENABLE 0x8 348 349 /** 350 * struct sde_drm_dest_scaler_cfg - destination scaler config structure 351 * @flags: Flag to switch between mode for destination scaler 352 * refer to destination scaler flag config 353 * @index: Destination scaler selection index 354 * @lm_width: Layer mixer width configuration 355 * @lm_height: Layer mixer height configuration 356 * @scaler_cfg: The scaling parameters for all the mode except disable 357 * Userspace pointer to struct sde_drm_scaler_v2 358 */ 359 struct sde_drm_dest_scaler_cfg { 360 uint32_t flags; 361 uint32_t index; 362 uint32_t lm_width; 363 uint32_t lm_height; 364 uint64_t scaler_cfg; 365 }; 366 367 /** 368 * struct sde_drm_dest_scaler_data - destination scaler data struct 369 * @num_dest_scaler: Number of dest scalers to be configured 370 * @ds_cfg: Destination scaler block configuration 371 */ 372 struct sde_drm_dest_scaler_data { 373 uint32_t num_dest_scaler; 374 struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT]; 375 }; 376 377 /* 378 * Define constants for struct sde_drm_csc 379 */ 380 #define SDE_CSC_MATRIX_COEFF_SIZE 9 381 #define SDE_CSC_CLAMP_SIZE 6 382 #define SDE_CSC_BIAS_SIZE 3 383 384 /** 385 * struct sde_drm_csc_v1 - version 1 of struct sde_drm_csc 386 * @ctm_coeff: Matrix coefficients, in S31.32 format 387 * @pre_bias: Pre-bias array values 388 * @post_bias: Post-bias array values 389 * @pre_clamp: Pre-clamp array values 390 * @post_clamp: Post-clamp array values 391 */ 392 struct sde_drm_csc_v1 { 393 int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE]; 394 uint32_t pre_bias[SDE_CSC_BIAS_SIZE]; 395 uint32_t post_bias[SDE_CSC_BIAS_SIZE]; 396 uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE]; 397 uint32_t post_clamp[SDE_CSC_CLAMP_SIZE]; 398 }; 399 400 /** 401 * struct sde_drm_color - struct to store the color and alpha values 402 * @color_0: Color 0 value 403 * @color_1: Color 1 value 404 * @color_2: Color 2 value 405 * @color_3: Color 3 value 406 */ 407 struct sde_drm_color { 408 uint32_t color_0; 409 uint32_t color_1; 410 uint32_t color_2; 411 uint32_t color_3; 412 }; 413 414 /* Total number of supported dim layers */ 415 #define SDE_MAX_DIM_LAYERS 7 416 417 /* SDE_DRM_DIM_LAYER_CONFIG_FLAG - flags for Dim Layer */ 418 /* Color fill inside of the rect, including border */ 419 #define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1 420 /* Color fill outside of the rect, excluding border */ 421 #define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2 422 423 /** 424 * struct sde_drm_dim_layer - dim layer cfg struct 425 * @flags: Refer SDE_DRM_DIM_LAYER_CONFIG_FLAG for possible values 426 * @stage: Blending stage of the dim layer 427 * @color_fill: Color fill for dim layer 428 * @rect: Dim layer coordinates 429 */ 430 struct sde_drm_dim_layer_cfg { 431 uint32_t flags; 432 uint32_t stage; 433 struct sde_drm_color color_fill; 434 struct drm_clip_rect rect; 435 }; 436 437 /** 438 * struct sde_drm_dim_layer_v1 - version 1 of dim layer struct 439 * @num_layers: Numer of Dim Layers 440 * @layer: Dim layer user cfgs ptr for the num_layers 441 */ 442 struct sde_drm_dim_layer_v1 { 443 uint32_t num_layers; 444 struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS]; 445 }; 446 447 /* Writeback Config version definition */ 448 #define SDE_DRM_WB_CFG 0x1 449 450 /* SDE_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */ 451 #define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1<<0) 452 453 /** 454 * struct sde_drm_wb_cfg - Writeback configuration structure 455 * @flags: see DRM_MSM_WB_CONFIG_FLAGS 456 * @connector_id: writeback connector identifier 457 * @count_modes: Count of modes in modes_ptr 458 * @modes: Pointer to struct drm_mode_modeinfo 459 */ 460 struct sde_drm_wb_cfg { 461 uint32_t flags; 462 uint32_t connector_id; 463 uint32_t count_modes; 464 uint64_t modes; 465 }; 466 467 #define SDE_MAX_ROI_V1 4 468 469 /** 470 * struct sde_drm_roi_v1 - list of regions of interest for a drm object 471 * @num_rects: number of valid rectangles in the roi array 472 * @roi: list of roi rectangles 473 */ 474 struct sde_drm_roi_v1 { 475 uint32_t num_rects; 476 struct drm_clip_rect roi[SDE_MAX_ROI_V1]; 477 }; 478 479 /** 480 * Define extended power modes supported by the SDE connectors. 481 */ 482 #define SDE_MODE_DPMS_ON 0 483 #define SDE_MODE_DPMS_LP1 1 484 #define SDE_MODE_DPMS_LP2 2 485 #define SDE_MODE_DPMS_STANDBY 3 486 #define SDE_MODE_DPMS_SUSPEND 4 487 #define SDE_MODE_DPMS_OFF 5 488 489 /** 490 * sde recovery events for notifying client 491 */ 492 #define SDE_RECOVERY_SUCCESS 0 493 #define SDE_RECOVERY_CAPTURE 1 494 #define SDE_RECOVERY_HARD_RESET 2 495 496 /* display format modifiers */ 497 /* 498 * QTI planar fsc Tile Format 499 * 500 * Refers to a tile variant of the planar format. 501 * Implementation may be platform and base-format specific. 502 */ 503 #define DRM_FORMAT_MOD_QCOM_FSC_TILE fourcc_mod_code(QCOM, 0x10) 504 #endif /* _SDE_DRM_H_ */ 505