xref: /external/XNNPACK/Android.bp

// Copyright (C) 2020 The Android Open Source Project
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//      http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

package {
    default_applicable_licenses: ["external_XNNPACK_license"],
}

// Added automatically by a large-scale-change
// See: http://go/android-license-faq
license {
    name: "external_XNNPACK_license",
    visibility: [":__subpackages__"],
    license_kinds: [
        "SPDX-license-identifier-BSD",
    ],
    license_text: [
        "LICENSE",
    ],
}

OPERATOR_SRCS = [
    "src/operator-delete.c",
    "src/operator-run.c",
    "src/operator-utils.c",
    "src/operators/argmax-pooling-nhwc.c",
    "src/operators/average-pooling-nhwc.c",
    "src/operators/binary-elementwise-nd.c",
    "src/operators/channel-shuffle-nc.c",
    "src/operators/constant-pad-nd.c",
    "src/operators/convolution-nchw.c",
    "src/operators/convolution-nhwc.c",
    "src/operators/deconvolution-nhwc.c",
    "src/operators/fully-connected-nc.c",
    "src/operators/global-average-pooling-ncw.c",
    "src/operators/global-average-pooling-nwc.c",
    "src/operators/lut-elementwise-nc.c",
    "src/operators/max-pooling-nhwc.c",
    "src/operators/prelu-nc.c",
    "src/operators/resize-bilinear-nchw.c",
    "src/operators/resize-bilinear-nhwc.c",
    "src/operators/softmax-nc.c",
    "src/operators/transpose-nd.c",
    "src/operators/unary-elementwise-nc.c",
    "src/operators/unpooling-nhwc.c",
]

LOGGING_SRCS = [
    "src/datatype-strings.c",
    "src/log.c",
    "src/node-type.c",
    "src/operator-strings.c",
    "src/ukernel-strings.c",
]

SUBGRAPH_SRCS = [
    "src/memory-planner.c",
    "src/runtime.c",
    "src/subgraph.c",
    "src/subgraph/abs.c",
    "src/subgraph/add2.c",
    "src/subgraph/argmax-pooling-2d.c",
    "src/subgraph/average-pooling-2d.c",
    "src/subgraph/bankers-rounding.c",
    "src/subgraph/ceiling.c",
    "src/subgraph/clamp.c",
    "src/subgraph/concatenate.c",
    "src/subgraph/convert.c",
    "src/subgraph/convolution-2d.c",
    "src/subgraph/deconvolution-2d.c",
    "src/subgraph/depth-to-space.c",
    "src/subgraph/depthwise-convolution-2d.c",
    "src/subgraph/divide.c",
    "src/subgraph/elu.c",
    "src/subgraph/even-split.c",
    "src/subgraph/floor.c",
    "src/subgraph/fully-connected.c",
    "src/subgraph/global-average-pooling.c",
    "src/subgraph/hardswish.c",
    "src/subgraph/leaky-relu.c",
    "src/subgraph/max-pooling-2d.c",
    "src/subgraph/maximum2.c",
    "src/subgraph/minimum2.c",
    "src/subgraph/multiply2.c",
    "src/subgraph/negate.c",
    "src/subgraph/prelu.c",
    "src/subgraph/sigmoid.c",
    "src/subgraph/softmax.c",
    "src/subgraph/square-root.c",
    "src/subgraph/square.c",
    "src/subgraph/squared-difference.c",
    "src/subgraph/static-constant-pad.c",
    "src/subgraph/static-reshape.c",
    "src/subgraph/static-resize-bilinear-2d.c",
    "src/subgraph/static-transpose.c",
    "src/subgraph/subtract.c",
    "src/subgraph/unpooling-2d.c",
    "src/subgraph/validation.c",
    "src/tensor.c",
]

TABLE_SRCS = [
    "src/tables/exp2-k-over-64.c",
    "src/tables/exp2-k-over-2048.c",
    "src/tables/exp2minus-k-over-4.c",
    "src/tables/exp2minus-k-over-8.c",
    "src/tables/exp2minus-k-over-16.c",
    "src/tables/exp2minus-k-over-64.c",
    "src/tables/exp2minus-k-over-2048.c",
    "src/tables/vlog.c",
]

PROD_SCALAR_PORTABLE_MICROKERNEL_SRCS = [
    "src/u8-lut32norm/scalar.c",
    "src/xx-copy/memcpy.c",
    "src/xx-transpose/1x1-memcpy.c",
    "src/x8-lut/gen/lut-scalar-x4.c",
]

PROD_SCALAR_AARCH32_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-scalar-x4.c",
    "src/f32-argmaxpool/4x-scalar-c1.c",
    "src/f32-argmaxpool/9p8x-scalar-c1.c",
    "src/f32-argmaxpool/9x-scalar-c1.c",
    "src/f32-avgpool/9p8x-minmax-scalar-c1.c",
    "src/f32-avgpool/9x-minmax-scalar-c1.c",
    "src/f32-conv-hwc/3x3s2p0p1c3x4-scalar-1x1.c",
    "src/f32-conv-hwc/3x3s2p1c3x4-scalar-1x1.c",
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-scalar-1x1.c",
    "src/f32-dwconv/gen/up1x3-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x3-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x4-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x4-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x9-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x9-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x25-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x25-scalar-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-4x1.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-2x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-2x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-2x1-acc2.c",
    "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x2.c",
    "src/f32-gavgpool-cw/scalar-x1.c",
    "src/f32-gavgpool/7p7x-minmax-scalar-c1.c",
    "src/f32-gavgpool/7x-minmax-scalar-c1.c",
    "src/f32-gemm/gen/1x4-minmax-scalar.c",
    "src/f32-gemm/gen/1x4-relu-scalar.c",
    "src/f32-gemm/gen/1x4-scalar.c",
    "src/f32-gemm/gen/4x2-minmax-scalar.c",
    "src/f32-gemm/gen/4x2-scalar.c",
    "src/f32-gemm/gen/4x4-minmax-scalar.c",
    "src/f32-gemm/gen/4x4-relu-scalar.c",
    "src/f32-gemm/gen/4x4-scalar.c",
    "src/f32-ibilinear-chw/gen/scalar-p4.c",
    "src/f32-ibilinear/gen/scalar-c2.c",
    "src/f32-igemm/gen/1x4-minmax-scalar.c",
    "src/f32-igemm/gen/1x4-relu-scalar.c",
    "src/f32-igemm/gen/1x4-scalar.c",
    "src/f32-igemm/gen/4x2-minmax-scalar.c",
    "src/f32-igemm/gen/4x2-scalar.c",
    "src/f32-igemm/gen/4x4-minmax-scalar.c",
    "src/f32-igemm/gen/4x4-relu-scalar.c",
    "src/f32-igemm/gen/4x4-scalar.c",
    "src/f32-maxpool/9p8x-minmax-scalar-c1.c",
    "src/f32-pavgpool/9p8x-minmax-scalar-c1.c",
    "src/f32-pavgpool/9x-minmax-scalar-c1.c",
    "src/f32-prelu/gen/scalar-2x4.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x4.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x4.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4-acc2.c",
    "src/f32-rmax/scalar.c",
    "src/f32-spmm/gen/8x1-minmax-scalar.c",
    "src/f32-spmm/gen/8x2-minmax-scalar.c",
    "src/f32-spmm/gen/8x4-minmax-scalar.c",
    "src/f32-vbinary/gen/vadd-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vdiv-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vdivc-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vmax-scalar-x8.c",
    "src/f32-vbinary/gen/vmaxc-scalar-x8.c",
    "src/f32-vbinary/gen/vmin-scalar-x8.c",
    "src/f32-vbinary/gen/vminc-scalar-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vrsubc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vsqrdiff-scalar-x8.c",
    "src/f32-vbinary/gen/vsqrdiffc-scalar-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-scalar-x8.c",
    "src/f32-vclamp/gen/vclamp-scalar-x4.c",
    "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x4.c",
    "src/f32-vhswish/gen/vhswish-scalar-x4.c",
    "src/f32-vlrelu/gen/vlrelu-scalar-x4.c",
    "src/f32-vmulcaddc/gen/c1-minmax-scalar-2x.c",
    "src/f32-vrelu/gen/vrelu-scalar-x8.c",
    "src/f32-vrnd/gen/vrndd-scalar-libm-x1.c",
    "src/f32-vrnd/gen/vrndne-scalar-libm-x1.c",
    "src/f32-vrnd/gen/vrndu-scalar-libm-x1.c",
    "src/f32-vrnd/gen/vrndz-scalar-libm-x1.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x2.c",
    "src/f32-vsqrt/gen/scalar-sqrt-x1.c",
    "src/f32-vunary/gen/vabs-scalar-x4.c",
    "src/f32-vunary/gen/vneg-scalar-x4.c",
    "src/f32-vunary/gen/vsqr-scalar-x4.c",
    "src/qc8-dwconv/gen/up1x3-minmax-fp32-scalar-fmagic.c",
    "src/qc8-dwconv/gen/up1x9-minmax-fp32-scalar-fmagic.c",
    "src/qc8-dwconv/gen/up1x25-minmax-fp32-scalar-fmagic.c",
    "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qc8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qc8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qc8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-dwconv/gen/up1x9-minmax-fp32-scalar-fmagic.c",
    "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-fmagic.c",
    "src/qs8-f32-vcvt/gen/vcvt-scalar-x4.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qs8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-vadd/gen/minmax-scalar-x1.c",
    "src/qs8-vaddc/gen/minmax-scalar-x1.c",
    "src/qs8-vmul/gen/minmax-fp32-scalar-x4.c",
    "src/qs8-vmulc/gen/minmax-fp32-scalar-x4.c",
    "src/qu8-avgpool/9p8x-minmax-scalar-c1.c",
    "src/qu8-avgpool/9x-minmax-scalar-c1.c",
    "src/qu8-dwconv/gen/up1x9-minmax-fp32-scalar-fmagic.c",
    "src/qu8-dwconv/gen/up1x25-minmax-fp32-scalar-fmagic.c",
    "src/qu8-f32-vcvt/gen/vcvt-scalar-x4.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qu8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-vadd/gen/minmax-scalar-x1.c",
    "src/qu8-vaddc/gen/minmax-scalar-x1.c",
    "src/qu8-vmul/gen/minmax-fp32-scalar-x4.c",
    "src/qu8-vmulc/gen/minmax-fp32-scalar-x4.c",
    "src/s8-ibilinear/gen/scalar-c1.c",
    "src/s8-maxpool/9p8x-minmax-scalar-c1.c",
    "src/s8-vclamp/scalar-x4.c",
    "src/u8-ibilinear/gen/scalar-c1.c",
    "src/u8-maxpool/9p8x-minmax-scalar-c1.c",
    "src/u8-rmax/scalar.c",
    "src/u8-vclamp/scalar-x4.c",
    "src/xx-fill/scalar-x16.c",
    "src/xx-pad/scalar.c",
    "src/x8-transposec/gen/2x4-scalar-int.c",
    "src/x8-zip/xm-scalar.c",
    "src/x8-zip/x2-scalar.c",
    "src/x8-zip/x3-scalar.c",
    "src/x8-zip/x4-scalar.c",
    "src/x16-transposec/gen/2x4-scalar-int.c",
    "src/x32-packx/x2-scalar.c",
    "src/x32-packx/x3-scalar.c",
    "src/x32-packx/x4-scalar.c",
    "src/x32-transposec/gen/2x4-scalar-int.c",
    "src/x32-unpool/scalar.c",
    "src/x32-zip/xm-scalar.c",
    "src/x32-zip/x2-scalar.c",
    "src/x32-zip/x3-scalar.c",
    "src/x32-zip/x4-scalar.c",
]

PROD_SCALAR_WASM_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-scalar-x1.c",
    "src/f32-argmaxpool/4x-scalar-c1.c",
    "src/f32-argmaxpool/9p8x-scalar-c1.c",
    "src/f32-argmaxpool/9x-scalar-c1.c",
    "src/f32-avgpool/9p8x-minmax-scalar-c1.c",
    "src/f32-avgpool/9x-minmax-scalar-c1.c",
    "src/f32-conv-hwc/3x3s2p0p1c3x4-scalar-1x1.c",
    "src/f32-conv-hwc/3x3s2p1c3x4-scalar-1x1.c",
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-scalar-1x1.c",
    "src/f32-dwconv/gen/up1x3-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x3-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x4-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x4-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x9-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x9-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x25-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x25-scalar-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-2x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc5.c",
    "src/f32-f16-vcvt/gen/vcvt-scalar-bitcast-x4.c",
    "src/f32-gavgpool-cw/scalar-x1.c",
    "src/f32-gavgpool/7p7x-minmax-scalar-c1.c",
    "src/f32-gavgpool/7x-minmax-scalar-c1.c",
    "src/f32-gemm/gen/1x4-scalar.c",
    "src/f32-gemm/gen/2x4-minmax-scalar.c",
    "src/f32-gemm/gen/2x4-relu-scalar.c",
    "src/f32-gemm/gen/2x4-scalar.c",
    "src/f32-gemm/gen/4x2-scalar.c",
    "src/f32-gemm/gen/4x4-scalar.c",
    "src/f32-ibilinear-chw/gen/scalar-p4.c",
    "src/f32-ibilinear/gen/scalar-c2.c",
    "src/f32-igemm/gen/1x4-scalar.c",
    "src/f32-igemm/gen/2x4-minmax-scalar.c",
    "src/f32-igemm/gen/2x4-relu-scalar.c",
    "src/f32-igemm/gen/2x4-scalar.c",
    "src/f32-igemm/gen/4x2-scalar.c",
    "src/f32-igemm/gen/4x4-scalar.c",
    "src/f32-maxpool/9p8x-minmax-scalar-c1.c",
    "src/f32-pavgpool/9p8x-minmax-scalar-c1.c",
    "src/f32-pavgpool/9x-minmax-scalar-c1.c",
    "src/f32-prelu/gen/scalar-2x4.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x1.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x1.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4-acc2.c",
    "src/f32-rmax/scalar.c",
    "src/f32-spmm/gen/8x1-minmax-scalar.c",
    "src/f32-spmm/gen/8x2-minmax-scalar.c",
    "src/f32-spmm/gen/8x4-minmax-scalar.c",
    "src/f32-vbinary/gen/vadd-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vdiv-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vdivc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vmax-scalar-x8.c",
    "src/f32-vbinary/gen/vmaxc-scalar-x8.c",
    "src/f32-vbinary/gen/vmin-scalar-x8.c",
    "src/f32-vbinary/gen/vminc-scalar-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vrsubc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vsqrdiff-scalar-x8.c",
    "src/f32-vbinary/gen/vsqrdiffc-scalar-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-scalar-x8.c",
    "src/f32-vclamp/gen/vclamp-scalar-x4.c",
    "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x2.c",
    "src/f32-vhswish/gen/vhswish-scalar-x4.c",
    "src/f32-vlrelu/gen/vlrelu-scalar-x4.c",
    "src/f32-vmulcaddc/gen/c1-minmax-scalar-2x.c",
    "src/f32-vrelu/gen/vrelu-scalar-x8.c",
    "src/f32-vrnd/gen/vrndd-scalar-libm-x4.c",
    "src/f32-vrnd/gen/vrndne-scalar-libm-x4.c",
    "src/f32-vrnd/gen/vrndu-scalar-libm-x4.c",
    "src/f32-vrnd/gen/vrndz-scalar-libm-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x2.c",
    "src/f32-vsqrt/gen/scalar-sqrt-x1.c",
    "src/f32-vunary/gen/vabs-scalar-x4.c",
    "src/f32-vunary/gen/vneg-scalar-x4.c",
    "src/f32-vunary/gen/vsqr-scalar-x4.c",
    "src/qc8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
    "src/qc8-dwconv/gen/up2x3-minmax-fp32-scalar-imagic.c",
    "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
    "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qc8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qc8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qc8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
    "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
    "src/qs8-f32-vcvt/gen/vcvt-scalar-x1.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c4.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c4.c",
    "src/qs8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-vadd/gen/minmax-scalar-x4.c",
    "src/qs8-vaddc/gen/minmax-scalar-x4.c",
    "src/qs8-vcvt/gen/vcvt-scalar-x1.c",
    "src/qs8-vcvt/gen/vcvt-scalar-x4.c",
    "src/qs8-vlrelu/gen/vlrelu-scalar-andxor-x4.c",
    "src/qs8-vlrelu/gen/vlrelu-scalar-select-x4.c",
    "src/qs8-vmul/gen/minmax-fp32-scalar-x4.c",
    "src/qs8-vmulc/gen/minmax-fp32-scalar-x4.c",
    "src/qu8-avgpool/9p8x-minmax-scalar-c1.c",
    "src/qu8-avgpool/9x-minmax-scalar-c1.c",
    "src/qu8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
    "src/qu8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
    "src/qu8-f32-vcvt/gen/vcvt-scalar-x1.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c4.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c4.c",
    "src/qu8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-vadd/gen/minmax-scalar-x4.c",
    "src/qu8-vaddc/gen/minmax-scalar-x4.c",
    "src/qu8-vcvt/gen/vcvt-scalar-x1.c",
    "src/qu8-vcvt/gen/vcvt-scalar-x4.c",
    "src/qu8-vlrelu/gen/vlrelu-scalar-andxor-x4.c",
    "src/qu8-vlrelu/gen/vlrelu-scalar-select-x4.c",
    "src/qu8-vmul/gen/minmax-fp32-scalar-x4.c",
    "src/qu8-vmulc/gen/minmax-fp32-scalar-x4.c",
    "src/s8-ibilinear/gen/scalar-c1.c",
    "src/s8-maxpool/9p8x-minmax-scalar-c1.c",
    "src/s8-vclamp/scalar-x4.c",
    "src/u8-ibilinear/gen/scalar-c1.c",
    "src/u8-maxpool/9p8x-minmax-scalar-c1.c",
    "src/u8-rmax/scalar.c",
    "src/u8-vclamp/scalar-x4.c",
    "src/xx-fill/scalar-x16.c",
    "src/xx-pad/scalar.c",
    "src/x8-transposec/gen/2x4-scalar-int.c",
    "src/x8-zip/xm-scalar.c",
    "src/x8-zip/x2-scalar.c",
    "src/x8-zip/x3-scalar.c",
    "src/x8-zip/x4-scalar.c",
    "src/x16-transposec/gen/2x4-scalar-int.c",
    "src/x32-packx/x2-scalar.c",
    "src/x32-packx/x3-scalar.c",
    "src/x32-packx/x4-scalar.c",
    "src/x32-transposec/gen/2x4-scalar-int.c",
    "src/x32-unpool/scalar.c",
    "src/x32-zip/xm-scalar.c",
    "src/x32-zip/x2-scalar.c",
    "src/x32-zip/x3-scalar.c",
    "src/x32-zip/x4-scalar.c",
]

PROD_SCALAR_RISCV_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-scalar-x4.c",
    "src/f32-argmaxpool/4x-scalar-c1.c",
    "src/f32-argmaxpool/9p8x-scalar-c1.c",
    "src/f32-argmaxpool/9x-scalar-c1.c",
    "src/f32-avgpool/9p8x-minmax-scalar-c1.c",
    "src/f32-avgpool/9x-minmax-scalar-c1.c",
    "src/f32-conv-hwc/3x3s2p0p1c3x4-scalar-1x1.c",
    "src/f32-conv-hwc/3x3s2p1c3x4-scalar-1x1.c",
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-scalar-1x1.c",
    "src/f32-dwconv/gen/up1x3-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x3-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x4-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x4-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x9-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x9-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x25-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x25-scalar-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-2x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc5.c",
    "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x2.c",
    "src/f32-gavgpool-cw/scalar-x1.c",
    "src/f32-gavgpool/7p7x-minmax-scalar-c1.c",
    "src/f32-gavgpool/7x-minmax-scalar-c1.c",
    "src/f32-gemm/gen/1x4-minmax-scalar.c",
    "src/f32-gemm/gen/1x4-relu-scalar.c",
    "src/f32-gemm/gen/1x4-scalar.c",
    "src/f32-gemm/gen/4x2-minmax-scalar.c",
    "src/f32-gemm/gen/4x2-scalar.c",
    "src/f32-gemm/gen/4x4-minmax-scalar.c",
    "src/f32-gemm/gen/4x4-relu-scalar.c",
    "src/f32-gemm/gen/4x4-scalar.c",
    "src/f32-ibilinear-chw/gen/scalar-p4.c",
    "src/f32-ibilinear/gen/scalar-c2.c",
    "src/f32-igemm/gen/1x4-minmax-scalar.c",
    "src/f32-igemm/gen/1x4-relu-scalar.c",
    "src/f32-igemm/gen/1x4-scalar.c",
    "src/f32-igemm/gen/4x2-minmax-scalar.c",
    "src/f32-igemm/gen/4x2-scalar.c",
    "src/f32-igemm/gen/4x4-minmax-scalar.c",
    "src/f32-igemm/gen/4x4-relu-scalar.c",
    "src/f32-igemm/gen/4x4-scalar.c",
    "src/f32-maxpool/9p8x-minmax-scalar-c1.c",
    "src/f32-pavgpool/9p8x-minmax-scalar-c1.c",
    "src/f32-pavgpool/9x-minmax-scalar-c1.c",
    "src/f32-prelu/gen/scalar-2x4.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-lrintf-x4.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-lrintf-x4.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4-acc2.c",
    "src/f32-rmax/scalar.c",
    "src/f32-spmm/gen/8x1-minmax-scalar.c",
    "src/f32-spmm/gen/8x2-minmax-scalar.c",
    "src/f32-spmm/gen/8x4-minmax-scalar.c",
    "src/f32-vbinary/gen/vadd-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vdiv-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vdivc-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vmax-scalar-x8.c",
    "src/f32-vbinary/gen/vmaxc-scalar-x8.c",
    "src/f32-vbinary/gen/vmin-scalar-x8.c",
    "src/f32-vbinary/gen/vminc-scalar-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vrsubc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vsqrdiff-scalar-x8.c",
    "src/f32-vbinary/gen/vsqrdiffc-scalar-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-scalar-x8.c",
    "src/f32-vclamp/gen/vclamp-scalar-x4.c",
    "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x4.c",
    "src/f32-vhswish/gen/vhswish-scalar-x4.c",
    "src/f32-vlrelu/gen/vlrelu-scalar-x4.c",
    "src/f32-vmulcaddc/gen/c1-minmax-scalar-2x.c",
    "src/f32-vrelu/gen/vrelu-scalar-x8.c",
    "src/f32-vrnd/gen/vrndd-scalar-libm-x1.c",
    "src/f32-vrnd/gen/vrndne-scalar-libm-x1.c",
    "src/f32-vrnd/gen/vrndu-scalar-libm-x1.c",
    "src/f32-vrnd/gen/vrndz-scalar-libm-x1.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x2.c",
    "src/f32-vsqrt/gen/scalar-sqrt-x1.c",
    "src/f32-vunary/gen/vabs-scalar-x4.c",
    "src/f32-vunary/gen/vneg-scalar-x4.c",
    "src/f32-vunary/gen/vsqr-scalar-x4.c",
    "src/qc8-dwconv/gen/up2x3-minmax-fp32-scalar-lrintf.c",
    "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
    "src/qc8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
    "src/qc8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qc8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qc8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qc8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
    "src/qs8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
    "src/qs8-f32-vcvt/gen/vcvt-scalar-x4.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qs8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-vadd/gen/minmax-scalar-x4.c",
    "src/qs8-vaddc/gen/minmax-scalar-x4.c",
    "src/qs8-vcvt/gen/vcvt-scalar-x4.c",
    "src/qs8-vlrelu/gen/vlrelu-scalar-andxor-x4.c",
    "src/qs8-vmul/gen/minmax-fp32-scalar-x4.c",
    "src/qs8-vmulc/gen/minmax-fp32-scalar-x4.c",
    "src/qu8-avgpool/9p8x-minmax-scalar-c1.c",
    "src/qu8-avgpool/9x-minmax-scalar-c1.c",
    "src/qu8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
    "src/qu8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
    "src/qu8-f32-vcvt/gen/vcvt-scalar-x4.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qu8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-vadd/gen/minmax-scalar-x4.c",
    "src/qu8-vaddc/gen/minmax-scalar-x4.c",
    "src/qu8-vcvt/gen/vcvt-scalar-x4.c",
    "src/qu8-vlrelu/gen/vlrelu-scalar-andxor-x4.c",
    "src/qu8-vmul/gen/minmax-fp32-scalar-x4.c",
    "src/qu8-vmulc/gen/minmax-fp32-scalar-x4.c",
    "src/s8-ibilinear/gen/scalar-c1.c",
    "src/s8-maxpool/9p8x-minmax-scalar-c1.c",
    "src/s8-vclamp/scalar-x4.c",
    "src/u8-ibilinear/gen/scalar-c1.c",
    "src/u8-maxpool/9p8x-minmax-scalar-c1.c",
    "src/u8-rmax/scalar.c",
    "src/u8-vclamp/scalar-x4.c",
    "src/xx-fill/scalar-x16.c",
    "src/xx-pad/scalar.c",
    "src/x8-transposec/gen/2x4-scalar-int.c",
    "src/x8-zip/xm-scalar.c",
    "src/x8-zip/x2-scalar.c",
    "src/x8-zip/x3-scalar.c",
    "src/x8-zip/x4-scalar.c",
    "src/x16-transposec/gen/2x4-scalar-int.c",
    "src/x32-packx/x2-scalar.c",
    "src/x32-packx/x3-scalar.c",
    "src/x32-packx/x4-scalar.c",
    "src/x32-transposec/gen/2x4-scalar-int.c",
    "src/x32-unpool/scalar.c",
    "src/x32-zip/xm-scalar.c",
    "src/x32-zip/x2-scalar.c",
    "src/x32-zip/x3-scalar.c",
    "src/x32-zip/x4-scalar.c",
]

ALL_SCALAR_MICROKERNEL_SRCS = [
    "src/cs16-bfly4/gen/scalar-x1.c",
    "src/cs16-bfly4/gen/scalar-x2.c",
    "src/cs16-bfly4/gen/scalar-x3.c",
    "src/cs16-bfly4/gen/scalar-x4.c",
    "src/cs16-bfly4/samples1-scalar.c",
    "src/cs16-fftr/gen/scalar-x1.c",
    "src/cs16-fftr/gen/scalar-x2.c",
    "src/cs16-fftr/gen/scalar-x3.c",
    "src/cs16-fftr/gen/scalar-x4.c",
    "src/cs16-vsquareabs/gen/scalar-x1.c",
    "src/cs16-vsquareabs/gen/scalar-x2.c",
    "src/cs16-vsquareabs/gen/scalar-x3.c",
    "src/cs16-vsquareabs/gen/scalar-x4.c",
    "src/f16-f32-vcvt/gen/vcvt-scalar-x1.c",
    "src/f16-f32-vcvt/gen/vcvt-scalar-x2.c",
    "src/f16-f32-vcvt/gen/vcvt-scalar-x3.c",
    "src/f16-f32-vcvt/gen/vcvt-scalar-x4.c",
    "src/f32-argmaxpool/4x-scalar-c1.c",
    "src/f32-argmaxpool/9p8x-scalar-c1.c",
    "src/f32-argmaxpool/9x-scalar-c1.c",
    "src/f32-avgpool/9p8x-minmax-scalar-c1.c",
    "src/f32-avgpool/9x-minmax-scalar-c1.c",
    "src/f32-conv-hwc/3x3s2p0p1c3x4-scalar-1x1.c",
    "src/f32-conv-hwc/3x3s2p1c3x4-scalar-1x1.c",
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-scalar-1x1.c",
    "src/f32-dwconv/gen/up1x3-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x3-minmax-scalar.c",
    "src/f32-dwconv/gen/up1x3-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x3-scalar.c",
    "src/f32-dwconv/gen/up1x4-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x4-minmax-scalar.c",
    "src/f32-dwconv/gen/up1x4-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x4-scalar.c",
    "src/f32-dwconv/gen/up1x9-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x9-minmax-scalar.c",
    "src/f32-dwconv/gen/up1x9-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x9-scalar.c",
    "src/f32-dwconv/gen/up1x25-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x25-minmax-scalar.c",
    "src/f32-dwconv/gen/up1x25-scalar-acc2.c",
    "src/f32-dwconv/gen/up1x25-scalar.c",
    "src/f32-dwconv/gen/up2x3-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up2x3-minmax-scalar.c",
    "src/f32-dwconv/gen/up2x3-scalar-acc2.c",
    "src/f32-dwconv/gen/up2x3-scalar.c",
    "src/f32-dwconv/gen/up2x4-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up2x4-minmax-scalar.c",
    "src/f32-dwconv/gen/up2x4-scalar-acc2.c",
    "src/f32-dwconv/gen/up2x4-scalar.c",
    "src/f32-dwconv/gen/up2x9-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up2x9-minmax-scalar.c",
    "src/f32-dwconv/gen/up2x9-scalar-acc2.c",
    "src/f32-dwconv/gen/up2x9-scalar.c",
    "src/f32-dwconv/gen/up2x25-minmax-scalar-acc2.c",
    "src/f32-dwconv/gen/up2x25-minmax-scalar.c",
    "src/f32-dwconv/gen/up2x25-scalar-acc2.c",
    "src/f32-dwconv/gen/up2x25-scalar.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-1x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-1x1-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-1x1-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-1x1.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-2x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-2x1.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-3x1.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-4x1.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-5x1.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-scalar-6x1.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-1x1.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-2x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-2x1.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-3x1.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-scalar-4x1.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-1x1.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-2x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-2x1-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-2x1.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-3x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-scalar-3x1.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-1x1.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-2x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-2x1-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-2x1.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-3x1-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-scalar-3x1.c",
    "src/f32-f16-vcvt/gen/vcvt-scalar-bitcast-x1.c",
    "src/f32-f16-vcvt/gen/vcvt-scalar-bitcast-x2.c",
    "src/f32-f16-vcvt/gen/vcvt-scalar-bitcast-x3.c",
    "src/f32-f16-vcvt/gen/vcvt-scalar-bitcast-x4.c",
    "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x1.c",
    "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x2.c",
    "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x3.c",
    "src/f32-f16-vcvt/gen/vcvt-scalar-fabsf-x4.c",
    "src/f32-gavgpool-cw/scalar-x1.c",
    "src/f32-gavgpool/7p7x-minmax-scalar-c1.c",
    "src/f32-gavgpool/7x-minmax-scalar-c1.c",
    "src/f32-gemm/gen-inc/1x4inc-minmax-scalar.c",
    "src/f32-gemm/gen-inc/2x4inc-minmax-scalar.c",
    "src/f32-gemm/gen-inc/4x4inc-minmax-scalar.c",
    "src/f32-gemm/gen/1x4-minmax-scalar.c",
    "src/f32-gemm/gen/1x4-relu-scalar.c",
    "src/f32-gemm/gen/1x4-scalar.c",
    "src/f32-gemm/gen/2x4-minmax-scalar.c",
    "src/f32-gemm/gen/2x4-relu-scalar.c",
    "src/f32-gemm/gen/2x4-scalar.c",
    "src/f32-gemm/gen/4x2-minmax-scalar.c",
    "src/f32-gemm/gen/4x2-relu-scalar.c",
    "src/f32-gemm/gen/4x2-scalar.c",
    "src/f32-gemm/gen/4x4-minmax-scalar.c",
    "src/f32-gemm/gen/4x4-relu-scalar.c",
    "src/f32-gemm/gen/4x4-scalar.c",
    "src/f32-ibilinear-chw/gen/scalar-p1.c",
    "src/f32-ibilinear-chw/gen/scalar-p2.c",
    "src/f32-ibilinear-chw/gen/scalar-p4.c",
    "src/f32-ibilinear/gen/scalar-c1.c",
    "src/f32-ibilinear/gen/scalar-c2.c",
    "src/f32-ibilinear/gen/scalar-c4.c",
    "src/f32-igemm/gen/1x4-minmax-scalar.c",
    "src/f32-igemm/gen/1x4-relu-scalar.c",
    "src/f32-igemm/gen/1x4-scalar.c",
    "src/f32-igemm/gen/2x4-minmax-scalar.c",
    "src/f32-igemm/gen/2x4-relu-scalar.c",
    "src/f32-igemm/gen/2x4-scalar.c",
    "src/f32-igemm/gen/4x2-minmax-scalar.c",
    "src/f32-igemm/gen/4x2-relu-scalar.c",
    "src/f32-igemm/gen/4x2-scalar.c",
    "src/f32-igemm/gen/4x4-minmax-scalar.c",
    "src/f32-igemm/gen/4x4-relu-scalar.c",
    "src/f32-igemm/gen/4x4-scalar.c",
    "src/f32-maxpool/9p8x-minmax-scalar-c1.c",
    "src/f32-pavgpool/9p8x-minmax-scalar-c1.c",
    "src/f32-pavgpool/9x-minmax-scalar-c1.c",
    "src/f32-ppmm/gen/2x4-minmax-scalar.c",
    "src/f32-ppmm/gen/3x3-minmax-scalar.c",
    "src/f32-ppmm/gen/4x2-minmax-scalar.c",
    "src/f32-ppmm/gen/4x4-minmax-scalar.c",
    "src/f32-prelu/gen/scalar-2x1.c",
    "src/f32-prelu/gen/scalar-2x4.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-fmagic-x1.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-fmagic-x2.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-fmagic-x3.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-fmagic-x4.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x1.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x2.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x3.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-imagic-x4.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-lrintf-x1.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-lrintf-x2.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-lrintf-x3.c",
    "src/f32-qs8-vcvt/gen/vcvt-scalar-lrintf-x4.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-fmagic-x1.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-fmagic-x2.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-fmagic-x3.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-fmagic-x4.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x1.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x2.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x3.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-imagic-x4.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-lrintf-x1.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-lrintf-x2.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-lrintf-x3.c",
    "src/f32-qu8-vcvt/gen/vcvt-scalar-lrintf-x4.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x1.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x2-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x2.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x4-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x4-acc4.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-lut64-p2-x4.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x1.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x2-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x2.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4-acc4.c",
    "src/f32-raddstoreexpminusmax/gen/scalar-rr2-p5-x4.c",
    "src/f32-rmax/scalar.c",
    "src/f32-spmm/gen/1x1-minmax-scalar-pipelined.c",
    "src/f32-spmm/gen/1x1-minmax-scalar.c",
    "src/f32-spmm/gen/2x1-minmax-scalar-pipelined.c",
    "src/f32-spmm/gen/2x1-minmax-scalar.c",
    "src/f32-spmm/gen/4x1-minmax-scalar-pipelined.c",
    "src/f32-spmm/gen/4x1-minmax-scalar.c",
    "src/f32-spmm/gen/8x1-minmax-scalar-pipelined.c",
    "src/f32-spmm/gen/8x1-minmax-scalar.c",
    "src/f32-spmm/gen/8x2-minmax-scalar.c",
    "src/f32-spmm/gen/8x4-minmax-scalar.c",
    "src/f32-vbinary/gen/vadd-minmax-scalar-x1.c",
    "src/f32-vbinary/gen/vadd-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vadd-minmax-scalar-x4.c",
    "src/f32-vbinary/gen/vadd-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vadd-relu-scalar-x1.c",
    "src/f32-vbinary/gen/vadd-relu-scalar-x2.c",
    "src/f32-vbinary/gen/vadd-relu-scalar-x4.c",
    "src/f32-vbinary/gen/vadd-relu-scalar-x8.c",
    "src/f32-vbinary/gen/vadd-scalar-x1.c",
    "src/f32-vbinary/gen/vadd-scalar-x2.c",
    "src/f32-vbinary/gen/vadd-scalar-x4.c",
    "src/f32-vbinary/gen/vadd-scalar-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-scalar-x1.c",
    "src/f32-vbinary/gen/vaddc-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vaddc-minmax-scalar-x4.c",
    "src/f32-vbinary/gen/vaddc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vaddc-relu-scalar-x1.c",
    "src/f32-vbinary/gen/vaddc-relu-scalar-x2.c",
    "src/f32-vbinary/gen/vaddc-relu-scalar-x4.c",
    "src/f32-vbinary/gen/vaddc-relu-scalar-x8.c",
    "src/f32-vbinary/gen/vaddc-scalar-x1.c",
    "src/f32-vbinary/gen/vaddc-scalar-x2.c",
    "src/f32-vbinary/gen/vaddc-scalar-x4.c",
    "src/f32-vbinary/gen/vaddc-scalar-x8.c",
    "src/f32-vbinary/gen/vdiv-minmax-scalar-x1.c",
    "src/f32-vbinary/gen/vdiv-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vdiv-minmax-scalar-x4.c",
    "src/f32-vbinary/gen/vdiv-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vdiv-relu-scalar-x1.c",
    "src/f32-vbinary/gen/vdiv-relu-scalar-x2.c",
    "src/f32-vbinary/gen/vdiv-relu-scalar-x4.c",
    "src/f32-vbinary/gen/vdiv-relu-scalar-x8.c",
    "src/f32-vbinary/gen/vdiv-scalar-x1.c",
    "src/f32-vbinary/gen/vdiv-scalar-x2.c",
    "src/f32-vbinary/gen/vdiv-scalar-x4.c",
    "src/f32-vbinary/gen/vdiv-scalar-x8.c",
    "src/f32-vbinary/gen/vdivc-minmax-scalar-x1.c",
    "src/f32-vbinary/gen/vdivc-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vdivc-minmax-scalar-x4.c",
    "src/f32-vbinary/gen/vdivc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vdivc-relu-scalar-x1.c",
    "src/f32-vbinary/gen/vdivc-relu-scalar-x2.c",
    "src/f32-vbinary/gen/vdivc-relu-scalar-x4.c",
    "src/f32-vbinary/gen/vdivc-relu-scalar-x8.c",
    "src/f32-vbinary/gen/vdivc-scalar-x1.c",
    "src/f32-vbinary/gen/vdivc-scalar-x2.c",
    "src/f32-vbinary/gen/vdivc-scalar-x4.c",
    "src/f32-vbinary/gen/vdivc-scalar-x8.c",
    "src/f32-vbinary/gen/vmax-scalar-x1.c",
    "src/f32-vbinary/gen/vmax-scalar-x2.c",
    "src/f32-vbinary/gen/vmax-scalar-x4.c",
    "src/f32-vbinary/gen/vmax-scalar-x8.c",
    "src/f32-vbinary/gen/vmaxc-scalar-x1.c",
    "src/f32-vbinary/gen/vmaxc-scalar-x2.c",
    "src/f32-vbinary/gen/vmaxc-scalar-x4.c",
    "src/f32-vbinary/gen/vmaxc-scalar-x8.c",
    "src/f32-vbinary/gen/vmin-scalar-x1.c",
    "src/f32-vbinary/gen/vmin-scalar-x2.c",
    "src/f32-vbinary/gen/vmin-scalar-x4.c",
    "src/f32-vbinary/gen/vmin-scalar-x8.c",
    "src/f32-vbinary/gen/vminc-scalar-x1.c",
    "src/f32-vbinary/gen/vminc-scalar-x2.c",
    "src/f32-vbinary/gen/vminc-scalar-x4.c",
    "src/f32-vbinary/gen/vminc-scalar-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-scalar-x1.c",
    "src/f32-vbinary/gen/vmul-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vmul-minmax-scalar-x4.c",
    "src/f32-vbinary/gen/vmul-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vmul-relu-scalar-x1.c",
    "src/f32-vbinary/gen/vmul-relu-scalar-x2.c",
    "src/f32-vbinary/gen/vmul-relu-scalar-x4.c",
    "src/f32-vbinary/gen/vmul-relu-scalar-x8.c",
    "src/f32-vbinary/gen/vmul-scalar-x1.c",
    "src/f32-vbinary/gen/vmul-scalar-x2.c",
    "src/f32-vbinary/gen/vmul-scalar-x4.c",
    "src/f32-vbinary/gen/vmul-scalar-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-scalar-x1.c",
    "src/f32-vbinary/gen/vmulc-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vmulc-minmax-scalar-x4.c",
    "src/f32-vbinary/gen/vmulc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vmulc-relu-scalar-x1.c",
    "src/f32-vbinary/gen/vmulc-relu-scalar-x2.c",
    "src/f32-vbinary/gen/vmulc-relu-scalar-x4.c",
    "src/f32-vbinary/gen/vmulc-relu-scalar-x8.c",
    "src/f32-vbinary/gen/vmulc-scalar-x1.c",
    "src/f32-vbinary/gen/vmulc-scalar-x2.c",
    "src/f32-vbinary/gen/vmulc-scalar-x4.c",
    "src/f32-vbinary/gen/vmulc-scalar-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-scalar-x1.c",
    "src/f32-vbinary/gen/vrdivc-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vrdivc-minmax-scalar-x4.c",
    "src/f32-vbinary/gen/vrdivc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vrdivc-relu-scalar-x1.c",
    "src/f32-vbinary/gen/vrdivc-relu-scalar-x2.c",
    "src/f32-vbinary/gen/vrdivc-relu-scalar-x4.c",
    "src/f32-vbinary/gen/vrdivc-relu-scalar-x8.c",
    "src/f32-vbinary/gen/vrdivc-scalar-x1.c",
    "src/f32-vbinary/gen/vrdivc-scalar-x2.c",
    "src/f32-vbinary/gen/vrdivc-scalar-x4.c",
    "src/f32-vbinary/gen/vrdivc-scalar-x8.c",
    "src/f32-vbinary/gen/vrsubc-minmax-scalar-x1.c",
    "src/f32-vbinary/gen/vrsubc-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vrsubc-minmax-scalar-x4.c",
    "src/f32-vbinary/gen/vrsubc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vrsubc-relu-scalar-x1.c",
    "src/f32-vbinary/gen/vrsubc-relu-scalar-x2.c",
    "src/f32-vbinary/gen/vrsubc-relu-scalar-x4.c",
    "src/f32-vbinary/gen/vrsubc-relu-scalar-x8.c",
    "src/f32-vbinary/gen/vrsubc-scalar-x1.c",
    "src/f32-vbinary/gen/vrsubc-scalar-x2.c",
    "src/f32-vbinary/gen/vrsubc-scalar-x4.c",
    "src/f32-vbinary/gen/vrsubc-scalar-x8.c",
    "src/f32-vbinary/gen/vsqrdiff-scalar-x1.c",
    "src/f32-vbinary/gen/vsqrdiff-scalar-x2.c",
    "src/f32-vbinary/gen/vsqrdiff-scalar-x4.c",
    "src/f32-vbinary/gen/vsqrdiff-scalar-x8.c",
    "src/f32-vbinary/gen/vsqrdiffc-scalar-x1.c",
    "src/f32-vbinary/gen/vsqrdiffc-scalar-x2.c",
    "src/f32-vbinary/gen/vsqrdiffc-scalar-x4.c",
    "src/f32-vbinary/gen/vsqrdiffc-scalar-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-scalar-x1.c",
    "src/f32-vbinary/gen/vsub-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vsub-minmax-scalar-x4.c",
    "src/f32-vbinary/gen/vsub-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vsub-relu-scalar-x1.c",
    "src/f32-vbinary/gen/vsub-relu-scalar-x2.c",
    "src/f32-vbinary/gen/vsub-relu-scalar-x4.c",
    "src/f32-vbinary/gen/vsub-relu-scalar-x8.c",
    "src/f32-vbinary/gen/vsub-scalar-x1.c",
    "src/f32-vbinary/gen/vsub-scalar-x2.c",
    "src/f32-vbinary/gen/vsub-scalar-x4.c",
    "src/f32-vbinary/gen/vsub-scalar-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-scalar-x1.c",
    "src/f32-vbinary/gen/vsubc-minmax-scalar-x2.c",
    "src/f32-vbinary/gen/vsubc-minmax-scalar-x4.c",
    "src/f32-vbinary/gen/vsubc-minmax-scalar-x8.c",
    "src/f32-vbinary/gen/vsubc-relu-scalar-x1.c",
    "src/f32-vbinary/gen/vsubc-relu-scalar-x2.c",
    "src/f32-vbinary/gen/vsubc-relu-scalar-x4.c",
    "src/f32-vbinary/gen/vsubc-relu-scalar-x8.c",
    "src/f32-vbinary/gen/vsubc-scalar-x1.c",
    "src/f32-vbinary/gen/vsubc-scalar-x2.c",
    "src/f32-vbinary/gen/vsubc-scalar-x4.c",
    "src/f32-vbinary/gen/vsubc-scalar-x8.c",
    "src/f32-vclamp/gen/vclamp-scalar-x1.c",
    "src/f32-vclamp/gen/vclamp-scalar-x2.c",
    "src/f32-vclamp/gen/vclamp-scalar-x4.c",
    "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x1.c",
    "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x2.c",
    "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x3.c",
    "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x4.c",
    "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x5.c",
    "src/f32-velu/gen/velu-scalar-rr2-lut16-p3-x6.c",
    "src/f32-velu/gen/velu-scalar-rr2-p6-x1.c",
    "src/f32-velu/gen/velu-scalar-rr2-p6-x2.c",
    "src/f32-velu/gen/velu-scalar-rr2-p6-x3.c",
    "src/f32-velu/gen/velu-scalar-rr2-p6-x4.c",
    "src/f32-velu/gen/velu-scalar-rr2-p6-x5.c",
    "src/f32-velu/gen/velu-scalar-rr2-p6-x6.c",
    "src/f32-vhswish/gen/vhswish-scalar-x1.c",
    "src/f32-vhswish/gen/vhswish-scalar-x2.c",
    "src/f32-vhswish/gen/vhswish-scalar-x4.c",
    "src/f32-vlrelu/gen/vlrelu-scalar-x1.c",
    "src/f32-vlrelu/gen/vlrelu-scalar-x2.c",
    "src/f32-vlrelu/gen/vlrelu-scalar-x4.c",
    "src/f32-vmulcaddc/gen/c1-minmax-scalar-2x.c",
    "src/f32-vmulcaddc/gen/c2-minmax-scalar-2x.c",
    "src/f32-vmulcaddc/gen/c4-minmax-scalar-2x.c",
    "src/f32-vrelu/gen/vrelu-scalar-x1.c",
    "src/f32-vrelu/gen/vrelu-scalar-x2.c",
    "src/f32-vrelu/gen/vrelu-scalar-x4.c",
    "src/f32-vrelu/gen/vrelu-scalar-x8.c",
    "src/f32-vrnd/gen/vrndd-scalar-libm-x1.c",
    "src/f32-vrnd/gen/vrndd-scalar-libm-x2.c",
    "src/f32-vrnd/gen/vrndd-scalar-libm-x4.c",
    "src/f32-vrnd/gen/vrndne-scalar-libm-x1.c",
    "src/f32-vrnd/gen/vrndne-scalar-libm-x2.c",
    "src/f32-vrnd/gen/vrndne-scalar-libm-x4.c",
    "src/f32-vrnd/gen/vrndu-scalar-libm-x1.c",
    "src/f32-vrnd/gen/vrndu-scalar-libm-x2.c",
    "src/f32-vrnd/gen/vrndu-scalar-libm-x4.c",
    "src/f32-vrnd/gen/vrndz-scalar-libm-x1.c",
    "src/f32-vrnd/gen/vrndz-scalar-libm-x2.c",
    "src/f32-vrnd/gen/vrndz-scalar-libm-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x1.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x2.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut64-p2-div-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut2048-p1-div-x1.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut2048-p1-div-x2.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-lut2048-p1-div-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-p5-div-x1.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-p5-div-x2.c",
    "src/f32-vsigmoid/gen/vsigmoid-scalar-rr2-p5-div-x4.c",
    "src/f32-vsqrt/gen/scalar-sqrt-x1.c",
    "src/f32-vsqrt/gen/scalar-sqrt-x2.c",
    "src/f32-vsqrt/gen/scalar-sqrt-x4.c",
    "src/f32-vunary/gen/vabs-scalar-x1.c",
    "src/f32-vunary/gen/vabs-scalar-x2.c",
    "src/f32-vunary/gen/vabs-scalar-x4.c",
    "src/f32-vunary/gen/vneg-scalar-x1.c",
    "src/f32-vunary/gen/vneg-scalar-x2.c",
    "src/f32-vunary/gen/vneg-scalar-x4.c",
    "src/f32-vunary/gen/vsqr-scalar-x1.c",
    "src/f32-vunary/gen/vsqr-scalar-x2.c",
    "src/f32-vunary/gen/vsqr-scalar-x4.c",
    "src/math/cvt-f32-f16-scalar-bitcast.c",
    "src/math/cvt-f32-f16-scalar-fabsf.c",
    "src/math/expminus-f32-scalar-rr2-lut64-p2.c",
    "src/math/expminus-f32-scalar-rr2-lut2048-p1.c",
    "src/math/expminus-f32-scalar-rr2-p5.c",
    "src/math/expm1minus-f32-scalar-rr2-lut4-p4.c",
    "src/math/expm1minus-f32-scalar-rr2-lut8-p3.c",
    "src/math/expm1minus-f32-scalar-rr2-lut8-p4.c",
    "src/math/expm1minus-f32-scalar-rr2-lut16-p3.c",
    "src/math/expm1minus-f32-scalar-rr2-lut16-p4.c",
    "src/math/expm1minus-f32-scalar-rr2-p5.c",
    "src/math/expm1minus-f32-scalar-rr2-p6.c",
    "src/math/roundd-scalar-addsub.c",
    "src/math/roundd-scalar-cvt.c",
    "src/math/roundd-scalar-floor.c",
    "src/math/roundne-scalar-addsub.c",
    "src/math/roundne-scalar-nearbyint.c",
    "src/math/roundne-scalar-rint.c",
    "src/math/roundu-scalar-addsub.c",
    "src/math/roundu-scalar-ceil.c",
    "src/math/roundu-scalar-cvt.c",
    "src/math/roundz-scalar-addsub.c",
    "src/math/roundz-scalar-cvt.c",
    "src/math/roundz-scalar-trunc.c",
    "src/math/sigmoid-f32-scalar-rr2-lut64-p2-div.c",
    "src/math/sigmoid-f32-scalar-rr2-lut2048-p1-div.c",
    "src/math/sigmoid-f32-scalar-rr2-p5-div.c",
    "src/math/sqrt-u32-scalar-bitmanip.c",
    "src/math/sqrt-u32-scalar-clz-binsearch.c",
    "src/math/sqrt-u32-scalar-clz-newton.c",
    "src/math/sqrt-u32-scalar-cvti32-sqrt-lrint.c",
    "src/math/sqrt-u32-scalar-cvti64-sqrt-lrint.c",
    "src/math/sqrt-u32-scalar-cvti64-sqrtf-lrintf.c",
    "src/math/sqrt-u32-scalar-cvtu32-sqrt-lrint.c",
    "src/math/sqrt-u32-scalar-cvtu32-sqrtf-lrintf.c",
    "src/math/sqrt-u32-scalar-hashemian.c",
    "src/math/sqrt-u32-scalar-tflm.c",
    "src/math/sqrt-u64-scalar-cvtu32-sqrt-cvtsatu32f64.c",
    "src/math/sqrt-u64-scalar-cvtu32-sqrt-llrint.c",
    "src/math/sqrt-u64-scalar-cvtu64-sqrt-llrint.c",
    "src/qc8-dwconv/gen/up1x3-minmax-fp32-scalar-fmagic.c",
    "src/qc8-dwconv/gen/up1x9-minmax-fp32-scalar-fmagic.c",
    "src/qc8-dwconv/gen/up1x9-minmax-fp32-scalar-imagic.c",
    "src/qc8-dwconv/gen/up1x9-minmax-fp32-scalar-lrintf.c",
    "src/qc8-dwconv/gen/up1x25-minmax-fp32-scalar-fmagic.c",
    "src/qc8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
    "src/qc8-dwconv/gen/up1x25-minmax-fp32-scalar-lrintf.c",
    "src/qc8-dwconv/gen/up2x3-minmax-fp32-scalar-imagic.c",
    "src/qc8-dwconv/gen/up2x3-minmax-fp32-scalar-lrintf.c",
    "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-fmagic.c",
    "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
    "src/qc8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
    "src/qc8-dwconv/gen/up2x25-minmax-fp32-scalar-fmagic.c",
    "src/qc8-dwconv/gen/up2x25-minmax-fp32-scalar-imagic.c",
    "src/qc8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
    "src/qc8-dwconv/gen/up4x9-minmax-fp32-scalar-fmagic.c",
    "src/qc8-dwconv/gen/up4x9-minmax-fp32-scalar-imagic.c",
    "src/qc8-dwconv/gen/up4x9-minmax-fp32-scalar-lrintf.c",
    "src/qc8-dwconv/gen/up4x25-minmax-fp32-scalar-fmagic.c",
    "src/qc8-dwconv/gen/up4x25-minmax-fp32-scalar-imagic.c",
    "src/qc8-dwconv/gen/up4x25-minmax-fp32-scalar-lrintf.c",
    "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qc8-gemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
    "src/qc8-gemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
    "src/qc8-gemm/gen/1x4-minmax-fp32-scalar-imagic.c",
    "src/qc8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qc8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qc8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qc8-gemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
    "src/qc8-gemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
    "src/qc8-gemm/gen/2x4-minmax-fp32-scalar-imagic.c",
    "src/qc8-gemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
    "src/qc8-gemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
    "src/qc8-gemm/gen/3x2-minmax-fp32-scalar-imagic.c",
    "src/qc8-gemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
    "src/qc8-gemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
    "src/qc8-gemm/gen/3x4-minmax-fp32-scalar-imagic.c",
    "src/qc8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qc8-gemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
    "src/qc8-gemm/gen/4x2-minmax-fp32-scalar-imagic.c",
    "src/qc8-gemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
    "src/qc8-gemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
    "src/qc8-gemm/gen/4x4-minmax-fp32-scalar-imagic.c",
    "src/qc8-gemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
    "src/qc8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qc8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qc8-igemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
    "src/qc8-igemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
    "src/qc8-igemm/gen/1x4-minmax-fp32-scalar-imagic.c",
    "src/qc8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qc8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qc8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qc8-igemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
    "src/qc8-igemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
    "src/qc8-igemm/gen/2x4-minmax-fp32-scalar-imagic.c",
    "src/qc8-igemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
    "src/qc8-igemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
    "src/qc8-igemm/gen/3x2-minmax-fp32-scalar-imagic.c",
    "src/qc8-igemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
    "src/qc8-igemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
    "src/qc8-igemm/gen/3x4-minmax-fp32-scalar-imagic.c",
    "src/qc8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qc8-igemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
    "src/qc8-igemm/gen/4x2-minmax-fp32-scalar-imagic.c",
    "src/qc8-igemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
    "src/qc8-igemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
    "src/qc8-igemm/gen/4x4-minmax-fp32-scalar-imagic.c",
    "src/qc8-igemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-dwconv/gen/up1x9-minmax-fp32-scalar-fmagic.c",
    "src/qs8-dwconv/gen/up1x9-minmax-fp32-scalar-imagic.c",
    "src/qs8-dwconv/gen/up1x9-minmax-fp32-scalar-lrintf.c",
    "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-fmagic.c",
    "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
    "src/qs8-dwconv/gen/up1x25-minmax-fp32-scalar-lrintf.c",
    "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-fmagic.c",
    "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
    "src/qs8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
    "src/qs8-dwconv/gen/up2x25-minmax-fp32-scalar-fmagic.c",
    "src/qs8-dwconv/gen/up2x25-minmax-fp32-scalar-imagic.c",
    "src/qs8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
    "src/qs8-dwconv/gen/up4x9-minmax-fp32-scalar-fmagic.c",
    "src/qs8-dwconv/gen/up4x9-minmax-fp32-scalar-imagic.c",
    "src/qs8-dwconv/gen/up4x9-minmax-fp32-scalar-lrintf.c",
    "src/qs8-dwconv/gen/up4x25-minmax-fp32-scalar-fmagic.c",
    "src/qs8-dwconv/gen/up4x25-minmax-fp32-scalar-imagic.c",
    "src/qs8-dwconv/gen/up4x25-minmax-fp32-scalar-lrintf.c",
    "src/qs8-f32-vcvt/gen/vcvt-scalar-x1.c",
    "src/qs8-f32-vcvt/gen/vcvt-scalar-x2.c",
    "src/qs8-f32-vcvt/gen/vcvt-scalar-x3.c",
    "src/qs8-f32-vcvt/gen/vcvt-scalar-x4.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c1.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c2.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c4.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c2.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c4.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c1.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c2.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c4.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c1.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c2.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c4.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c2.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c4.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c1.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c2.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c4.c",
    "src/qs8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-gemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
    "src/qs8-gemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
    "src/qs8-gemm/gen/1x4-minmax-fp32-scalar-imagic.c",
    "src/qs8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-gemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
    "src/qs8-gemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
    "src/qs8-gemm/gen/2x4-minmax-fp32-scalar-imagic.c",
    "src/qs8-gemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-gemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-gemm/gen/3x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-gemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
    "src/qs8-gemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
    "src/qs8-gemm/gen/3x4-minmax-fp32-scalar-imagic.c",
    "src/qs8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-gemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-gemm/gen/4x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-gemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
    "src/qs8-gemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
    "src/qs8-gemm/gen/4x4-minmax-fp32-scalar-imagic.c",
    "src/qs8-gemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-igemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
    "src/qs8-igemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
    "src/qs8-igemm/gen/1x4-minmax-fp32-scalar-imagic.c",
    "src/qs8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-igemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
    "src/qs8-igemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
    "src/qs8-igemm/gen/2x4-minmax-fp32-scalar-imagic.c",
    "src/qs8-igemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-igemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-igemm/gen/3x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-igemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
    "src/qs8-igemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
    "src/qs8-igemm/gen/3x4-minmax-fp32-scalar-imagic.c",
    "src/qs8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-igemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
    "src/qs8-igemm/gen/4x2-minmax-fp32-scalar-imagic.c",
    "src/qs8-igemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
    "src/qs8-igemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
    "src/qs8-igemm/gen/4x4-minmax-fp32-scalar-imagic.c",
    "src/qs8-igemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
    "src/qs8-requantization/fp32-scalar-fmagic.c",
    "src/qs8-requantization/fp32-scalar-lrintf.c",
    "src/qs8-requantization/gemmlowp-scalar.c",
    "src/qs8-requantization/rndna-scalar-signed64.c",
    "src/qs8-requantization/rndna-scalar-unsigned32.c",
    "src/qs8-requantization/rndna-scalar-unsigned64.c",
    "src/qs8-requantization/rndnu-scalar.c",
    "src/qs8-vadd/gen/minmax-scalar-x1.c",
    "src/qs8-vadd/gen/minmax-scalar-x2.c",
    "src/qs8-vadd/gen/minmax-scalar-x4.c",
    "src/qs8-vaddc/gen/minmax-scalar-x1.c",
    "src/qs8-vaddc/gen/minmax-scalar-x2.c",
    "src/qs8-vaddc/gen/minmax-scalar-x4.c",
    "src/qs8-vcvt/gen/vcvt-scalar-x1.c",
    "src/qs8-vcvt/gen/vcvt-scalar-x2.c",
    "src/qs8-vcvt/gen/vcvt-scalar-x4.c",
    "src/qs8-vlrelu/gen/vlrelu-scalar-andxor-x1.c",
    "src/qs8-vlrelu/gen/vlrelu-scalar-andxor-x2.c",
    "src/qs8-vlrelu/gen/vlrelu-scalar-andxor-x4.c",
    "src/qs8-vlrelu/gen/vlrelu-scalar-select-x1.c",
    "src/qs8-vlrelu/gen/vlrelu-scalar-select-x2.c",
    "src/qs8-vlrelu/gen/vlrelu-scalar-select-x4.c",
    "src/qs8-vmul/gen/minmax-fp32-scalar-x1.c",
    "src/qs8-vmul/gen/minmax-fp32-scalar-x2.c",
    "src/qs8-vmul/gen/minmax-fp32-scalar-x4.c",
    "src/qs8-vmulc/gen/minmax-fp32-scalar-x1.c",
    "src/qs8-vmulc/gen/minmax-fp32-scalar-x2.c",
    "src/qs8-vmulc/gen/minmax-fp32-scalar-x4.c",
    "src/qu8-avgpool/9p8x-minmax-scalar-c1.c",
    "src/qu8-avgpool/9x-minmax-scalar-c1.c",
    "src/qu8-dwconv/gen/up1x9-minmax-fp32-scalar-fmagic.c",
    "src/qu8-dwconv/gen/up1x9-minmax-fp32-scalar-imagic.c",
    "src/qu8-dwconv/gen/up1x9-minmax-fp32-scalar-lrintf.c",
    "src/qu8-dwconv/gen/up1x25-minmax-fp32-scalar-fmagic.c",
    "src/qu8-dwconv/gen/up1x25-minmax-fp32-scalar-imagic.c",
    "src/qu8-dwconv/gen/up1x25-minmax-fp32-scalar-lrintf.c",
    "src/qu8-dwconv/gen/up2x9-minmax-fp32-scalar-fmagic.c",
    "src/qu8-dwconv/gen/up2x9-minmax-fp32-scalar-imagic.c",
    "src/qu8-dwconv/gen/up2x9-minmax-fp32-scalar-lrintf.c",
    "src/qu8-dwconv/gen/up2x25-minmax-fp32-scalar-fmagic.c",
    "src/qu8-dwconv/gen/up2x25-minmax-fp32-scalar-imagic.c",
    "src/qu8-dwconv/gen/up2x25-minmax-fp32-scalar-lrintf.c",
    "src/qu8-dwconv/gen/up4x9-minmax-fp32-scalar-fmagic.c",
    "src/qu8-dwconv/gen/up4x9-minmax-fp32-scalar-imagic.c",
    "src/qu8-dwconv/gen/up4x9-minmax-fp32-scalar-lrintf.c",
    "src/qu8-dwconv/gen/up4x25-minmax-fp32-scalar-fmagic.c",
    "src/qu8-dwconv/gen/up4x25-minmax-fp32-scalar-imagic.c",
    "src/qu8-dwconv/gen/up4x25-minmax-fp32-scalar-lrintf.c",
    "src/qu8-f32-vcvt/gen/vcvt-scalar-x1.c",
    "src/qu8-f32-vcvt/gen/vcvt-scalar-x2.c",
    "src/qu8-f32-vcvt/gen/vcvt-scalar-x3.c",
    "src/qu8-f32-vcvt/gen/vcvt-scalar-x4.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c1.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c2.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-fmagic-c4.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c2.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-imagic-c4.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c1.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c2.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-scalar-lrintf-c4.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c1.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c2.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-fmagic-c4.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c1.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c2.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-imagic-c4.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c1.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c2.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-scalar-lrintf-c4.c",
    "src/qu8-gemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-gemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-gemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
    "src/qu8-gemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
    "src/qu8-gemm/gen/1x4-minmax-fp32-scalar-imagic.c",
    "src/qu8-gemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-gemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-gemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-gemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
    "src/qu8-gemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
    "src/qu8-gemm/gen/2x4-minmax-fp32-scalar-imagic.c",
    "src/qu8-gemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-gemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-gemm/gen/3x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-gemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
    "src/qu8-gemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
    "src/qu8-gemm/gen/3x4-minmax-fp32-scalar-imagic.c",
    "src/qu8-gemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-gemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-gemm/gen/4x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-gemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
    "src/qu8-gemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
    "src/qu8-gemm/gen/4x4-minmax-fp32-scalar-imagic.c",
    "src/qu8-gemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-igemm/gen/1x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-igemm/gen/1x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-igemm/gen/1x2-minmax-fp32-scalar-lrintf.c",
    "src/qu8-igemm/gen/1x4-minmax-fp32-scalar-fmagic.c",
    "src/qu8-igemm/gen/1x4-minmax-fp32-scalar-imagic.c",
    "src/qu8-igemm/gen/1x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-igemm/gen/2x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-igemm/gen/2x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-igemm/gen/2x2-minmax-fp32-scalar-lrintf.c",
    "src/qu8-igemm/gen/2x4-minmax-fp32-scalar-fmagic.c",
    "src/qu8-igemm/gen/2x4-minmax-fp32-scalar-imagic.c",
    "src/qu8-igemm/gen/2x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-igemm/gen/3x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-igemm/gen/3x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-igemm/gen/3x2-minmax-fp32-scalar-lrintf.c",
    "src/qu8-igemm/gen/3x4-minmax-fp32-scalar-fmagic.c",
    "src/qu8-igemm/gen/3x4-minmax-fp32-scalar-imagic.c",
    "src/qu8-igemm/gen/3x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-igemm/gen/4x2-minmax-fp32-scalar-fmagic.c",
    "src/qu8-igemm/gen/4x2-minmax-fp32-scalar-imagic.c",
    "src/qu8-igemm/gen/4x2-minmax-fp32-scalar-lrintf.c",
    "src/qu8-igemm/gen/4x4-minmax-fp32-scalar-fmagic.c",
    "src/qu8-igemm/gen/4x4-minmax-fp32-scalar-imagic.c",
    "src/qu8-igemm/gen/4x4-minmax-fp32-scalar-lrintf.c",
    "src/qu8-requantization/fp32-scalar-fmagic.c",
    "src/qu8-requantization/fp32-scalar-lrintf.c",
    "src/qu8-requantization/gemmlowp-scalar.c",
    "src/qu8-requantization/rndna-scalar-signed64.c",
    "src/qu8-requantization/rndna-scalar-unsigned32.c",
    "src/qu8-requantization/rndna-scalar-unsigned64.c",
    "src/qu8-vadd/gen/minmax-scalar-x1.c",
    "src/qu8-vadd/gen/minmax-scalar-x2.c",
    "src/qu8-vadd/gen/minmax-scalar-x4.c",
    "src/qu8-vaddc/gen/minmax-scalar-x1.c",
    "src/qu8-vaddc/gen/minmax-scalar-x2.c",
    "src/qu8-vaddc/gen/minmax-scalar-x4.c",
    "src/qu8-vcvt/gen/vcvt-scalar-x1.c",
    "src/qu8-vcvt/gen/vcvt-scalar-x2.c",
    "src/qu8-vcvt/gen/vcvt-scalar-x4.c",
    "src/qu8-vlrelu/gen/vlrelu-scalar-andxor-x1.c",
    "src/qu8-vlrelu/gen/vlrelu-scalar-andxor-x2.c",
    "src/qu8-vlrelu/gen/vlrelu-scalar-andxor-x4.c",
    "src/qu8-vlrelu/gen/vlrelu-scalar-select-x1.c",
    "src/qu8-vlrelu/gen/vlrelu-scalar-select-x2.c",
    "src/qu8-vlrelu/gen/vlrelu-scalar-select-x4.c",
    "src/qu8-vmul/gen/minmax-fp32-scalar-x1.c",
    "src/qu8-vmul/gen/minmax-fp32-scalar-x2.c",
    "src/qu8-vmul/gen/minmax-fp32-scalar-x4.c",
    "src/qu8-vmulc/gen/minmax-fp32-scalar-x1.c",
    "src/qu8-vmulc/gen/minmax-fp32-scalar-x2.c",
    "src/qu8-vmulc/gen/minmax-fp32-scalar-x4.c",
    "src/s8-ibilinear/gen/scalar-c1.c",
    "src/s8-ibilinear/gen/scalar-c2.c",
    "src/s8-ibilinear/gen/scalar-c4.c",
    "src/s8-maxpool/9p8x-minmax-scalar-c1.c",
    "src/s8-vclamp/scalar-x4.c",
    "src/s16-rmaxabs/gen/scalar-x1.c",
    "src/s16-rmaxabs/gen/scalar-x2.c",
    "src/s16-rmaxabs/gen/scalar-x3.c",
    "src/s16-rmaxabs/gen/scalar-x4.c",
    "src/s16-vlshift/gen/scalar-x1.c",
    "src/s16-vlshift/gen/scalar-x2.c",
    "src/s16-vlshift/gen/scalar-x3.c",
    "src/s16-vlshift/gen/scalar-x4.c",
    "src/s16-window/gen/scalar-x1.c",
    "src/s16-window/gen/scalar-x2.c",
    "src/s16-window/gen/scalar-x3.c",
    "src/s16-window/gen/scalar-x4.c",
    "src/u8-ibilinear/gen/scalar-c1.c",
    "src/u8-ibilinear/gen/scalar-c2.c",
    "src/u8-ibilinear/gen/scalar-c4.c",
    "src/u8-lut32norm/scalar.c",
    "src/u8-maxpool/9p8x-minmax-scalar-c1.c",
    "src/u8-rmax/scalar.c",
    "src/u8-vclamp/scalar-x4.c",
    "src/u32-filterbank-accumulate/gen/scalar-x1.c",
    "src/u32-filterbank-subtract/scalar-x2.c",
    "src/u32-vlog/gen/scalar-x1.c",
    "src/u32-vlog/gen/scalar-x2.c",
    "src/u32-vlog/gen/scalar-x3.c",
    "src/u32-vlog/gen/scalar-x4.c",
    "src/u64-u32-vsqrtshift/scalar-cvtu32-sqrt-cvtu32f64-x1.c",
    "src/xx-copy/memcpy.c",
    "src/xx-fill/scalar-x16.c",
    "src/xx-pad/scalar.c",
    "src/xx-transpose/1x1-memcpy.c",
    "src/x8-lut/gen/lut-scalar-x1.c",
    "src/x8-lut/gen/lut-scalar-x2.c",
    "src/x8-lut/gen/lut-scalar-x4.c",
    "src/x8-lut/gen/lut-scalar-x8.c",
    "src/x8-lut/gen/lut-scalar-x16.c",
    "src/x8-transposec/gen/1x2-scalar-int.c",
    "src/x8-transposec/gen/1x4-scalar-int.c",
    "src/x8-transposec/gen/2x1-scalar-int.c",
    "src/x8-transposec/gen/2x2-scalar-int.c",
    "src/x8-transposec/gen/2x4-scalar-int.c",
    "src/x8-transposec/gen/4x1-scalar-int.c",
    "src/x8-transposec/gen/4x2-scalar-int.c",
    "src/x8-transposec/gen/4x4-scalar-int.c",
    "src/x8-zip/xm-scalar.c",
    "src/x8-zip/x2-scalar.c",
    "src/x8-zip/x3-scalar.c",
    "src/x8-zip/x4-scalar.c",
    "src/x16-transposec/gen/1x2-scalar-int.c",
    "src/x16-transposec/gen/1x4-scalar-int.c",
    "src/x16-transposec/gen/2x1-scalar-int.c",
    "src/x16-transposec/gen/2x2-scalar-int.c",
    "src/x16-transposec/gen/2x4-scalar-int.c",
    "src/x16-transposec/gen/4x1-scalar-int.c",
    "src/x16-transposec/gen/4x2-scalar-int.c",
    "src/x16-transposec/gen/4x4-scalar-int.c",
    "src/x24-transposec/gen/1x2-scalar.c",
    "src/x24-transposec/gen/1x4-scalar.c",
    "src/x24-transposec/gen/2x1-scalar.c",
    "src/x24-transposec/gen/2x2-scalar.c",
    "src/x24-transposec/gen/2x4-scalar.c",
    "src/x24-transposec/gen/4x1-scalar.c",
    "src/x24-transposec/gen/4x2-scalar.c",
    "src/x24-transposec/gen/4x4-scalar.c",
    "src/x32-packx/x2-scalar.c",
    "src/x32-packx/x3-scalar.c",
    "src/x32-packx/x4-scalar.c",
    "src/x32-transposec/gen/1x2-scalar-float.c",
    "src/x32-transposec/gen/1x2-scalar-int.c",
    "src/x32-transposec/gen/1x4-scalar-float.c",
    "src/x32-transposec/gen/1x4-scalar-int.c",
    "src/x32-transposec/gen/2x1-scalar-float.c",
    "src/x32-transposec/gen/2x1-scalar-int.c",
    "src/x32-transposec/gen/2x2-scalar-float.c",
    "src/x32-transposec/gen/2x2-scalar-int.c",
    "src/x32-transposec/gen/2x4-scalar-float.c",
    "src/x32-transposec/gen/2x4-scalar-int.c",
    "src/x32-transposec/gen/4x1-scalar-float.c",
    "src/x32-transposec/gen/4x1-scalar-int.c",
    "src/x32-transposec/gen/4x2-scalar-float.c",
    "src/x32-transposec/gen/4x2-scalar-int.c",
    "src/x32-transposec/gen/4x4-scalar-float.c",
    "src/x32-transposec/gen/4x4-scalar-int.c",
    "src/x32-unpool/scalar.c",
    "src/x32-zip/xm-scalar.c",
    "src/x32-zip/x2-scalar.c",
    "src/x32-zip/x3-scalar.c",
    "src/x32-zip/x4-scalar.c",
    "src/x64-transposec/gen/1x2-scalar-float.c",
    "src/x64-transposec/gen/1x2-scalar-int.c",
    "src/x64-transposec/gen/2x1-scalar-float.c",
    "src/x64-transposec/gen/2x1-scalar-int.c",
    "src/x64-transposec/gen/2x2-scalar-float.c",
    "src/x64-transposec/gen/2x2-scalar-int.c",
    "src/x64-transposec/gen/4x1-scalar-float.c",
    "src/x64-transposec/gen/4x1-scalar-int.c",
    "src/x64-transposec/gen/4x2-scalar-float.c",
    "src/x64-transposec/gen/4x2-scalar-int.c",
]

ALL_WASM_MICROKERNEL_SRCS = [
    "src/f32-avgpool/9p8x-minmax-wasm-c1.c",
    "src/f32-avgpool/9x-minmax-wasm-c1.c",
    "src/f32-dwconv/gen/up1x3-minmax-wasm-acc2.c",
    "src/f32-dwconv/gen/up1x3-minmax-wasm.c",
    "src/f32-dwconv/gen/up1x4-minmax-wasm-acc2.c",
    "src/f32-dwconv/gen/up1x4-minmax-wasm.c",
    "src/f32-dwconv/gen/up1x9-minmax-wasm-acc2.c",
    "src/f32-dwconv/gen/up1x9-minmax-wasm.c",
    "src/f32-dwconv/gen/up1x25-minmax-wasm-acc2.c",
    "src/f32-dwconv/gen/up1x25-minmax-wasm.c",
    "src/f32-dwconv/gen/up2x3-minmax-wasm-acc2.c",
    "src/f32-dwconv/gen/up2x3-minmax-wasm.c",
    "src/f32-dwconv/gen/up2x4-minmax-wasm-acc2.c",
    "src/f32-dwconv/gen/up2x4-minmax-wasm.c",
    "src/f32-dwconv/gen/up2x9-minmax-wasm-acc2.c",
    "src/f32-dwconv/gen/up2x9-minmax-wasm.c",
    "src/f32-dwconv/gen/up2x25-minmax-wasm-acc2.c",
    "src/f32-dwconv/gen/up2x25-minmax-wasm.c",
    "src/f32-gavgpool/7p7x-minmax-wasm-c1.c",
    "src/f32-gavgpool/7x-minmax-wasm-c1.c",
    "src/f32-gemm/gen-inc/1x4inc-minmax-wasm.c",
    "src/f32-gemm/gen-inc/2x4inc-minmax-wasm.c",
    "src/f32-gemm/gen-inc/4x4inc-minmax-wasm.c",
    "src/f32-gemm/gen/1x4-minmax-wasm.c",
    "src/f32-gemm/gen/1x4-relu-wasm.c",
    "src/f32-gemm/gen/2x4-minmax-wasm.c",
    "src/f32-gemm/gen/2x4-relu-wasm.c",
    "src/f32-gemm/gen/4x2-minmax-wasm.c",
    "src/f32-gemm/gen/4x2-relu-wasm.c",
    "src/f32-gemm/gen/4x4-minmax-wasm.c",
    "src/f32-gemm/gen/4x4-relu-wasm.c",
    "src/f32-igemm/gen/1x4-minmax-wasm.c",
    "src/f32-igemm/gen/1x4-relu-wasm.c",
    "src/f32-igemm/gen/2x4-minmax-wasm.c",
    "src/f32-igemm/gen/2x4-relu-wasm.c",
    "src/f32-igemm/gen/4x2-minmax-wasm.c",
    "src/f32-igemm/gen/4x2-relu-wasm.c",
    "src/f32-igemm/gen/4x4-minmax-wasm.c",
    "src/f32-igemm/gen/4x4-relu-wasm.c",
    "src/f32-maxpool/9p8x-minmax-wasm-c1.c",
    "src/f32-pavgpool/9p8x-minmax-wasm-c1.c",
    "src/f32-pavgpool/9x-minmax-wasm-c1.c",
    "src/f32-prelu/gen/wasm-2x1.c",
    "src/f32-prelu/gen/wasm-2x4.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasm-fmagic-x1.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasm-fmagic-x2.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasm-fmagic-x3.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasm-fmagic-x4.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasm-fmagic-x1.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasm-fmagic-x2.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasm-fmagic-x3.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasm-fmagic-x4.c",
    "src/f32-vbinary/gen/vadd-minmax-wasm-x1.c",
    "src/f32-vbinary/gen/vadd-minmax-wasm-x2.c",
    "src/f32-vbinary/gen/vadd-minmax-wasm-x4.c",
    "src/f32-vbinary/gen/vadd-minmax-wasm-x8.c",
    "src/f32-vbinary/gen/vadd-relu-wasm-x1.c",
    "src/f32-vbinary/gen/vadd-relu-wasm-x2.c",
    "src/f32-vbinary/gen/vadd-relu-wasm-x4.c",
    "src/f32-vbinary/gen/vadd-relu-wasm-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-wasm-x1.c",
    "src/f32-vbinary/gen/vaddc-minmax-wasm-x2.c",
    "src/f32-vbinary/gen/vaddc-minmax-wasm-x4.c",
    "src/f32-vbinary/gen/vaddc-minmax-wasm-x8.c",
    "src/f32-vbinary/gen/vaddc-relu-wasm-x1.c",
    "src/f32-vbinary/gen/vaddc-relu-wasm-x2.c",
    "src/f32-vbinary/gen/vaddc-relu-wasm-x4.c",
    "src/f32-vbinary/gen/vaddc-relu-wasm-x8.c",
    "src/f32-vbinary/gen/vdiv-minmax-wasm-x1.c",
    "src/f32-vbinary/gen/vdiv-minmax-wasm-x2.c",
    "src/f32-vbinary/gen/vdiv-minmax-wasm-x4.c",
    "src/f32-vbinary/gen/vdiv-minmax-wasm-x8.c",
    "src/f32-vbinary/gen/vdiv-relu-wasm-x1.c",
    "src/f32-vbinary/gen/vdiv-relu-wasm-x2.c",
    "src/f32-vbinary/gen/vdiv-relu-wasm-x4.c",
    "src/f32-vbinary/gen/vdiv-relu-wasm-x8.c",
    "src/f32-vbinary/gen/vdivc-minmax-wasm-x1.c",
    "src/f32-vbinary/gen/vdivc-minmax-wasm-x2.c",
    "src/f32-vbinary/gen/vdivc-minmax-wasm-x4.c",
    "src/f32-vbinary/gen/vdivc-minmax-wasm-x8.c",
    "src/f32-vbinary/gen/vdivc-relu-wasm-x1.c",
    "src/f32-vbinary/gen/vdivc-relu-wasm-x2.c",
    "src/f32-vbinary/gen/vdivc-relu-wasm-x4.c",
    "src/f32-vbinary/gen/vdivc-relu-wasm-x8.c",
    "src/f32-vbinary/gen/vmax-wasm-x1.c",
    "src/f32-vbinary/gen/vmax-wasm-x2.c",
    "src/f32-vbinary/gen/vmax-wasm-x4.c",
    "src/f32-vbinary/gen/vmax-wasm-x8.c",
    "src/f32-vbinary/gen/vmaxc-wasm-x1.c",
    "src/f32-vbinary/gen/vmaxc-wasm-x2.c",
    "src/f32-vbinary/gen/vmaxc-wasm-x4.c",
    "src/f32-vbinary/gen/vmaxc-wasm-x8.c",
    "src/f32-vbinary/gen/vmin-wasm-x1.c",
    "src/f32-vbinary/gen/vmin-wasm-x2.c",
    "src/f32-vbinary/gen/vmin-wasm-x4.c",
    "src/f32-vbinary/gen/vmin-wasm-x8.c",
    "src/f32-vbinary/gen/vminc-wasm-x1.c",
    "src/f32-vbinary/gen/vminc-wasm-x2.c",
    "src/f32-vbinary/gen/vminc-wasm-x4.c",
    "src/f32-vbinary/gen/vminc-wasm-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-wasm-x1.c",
    "src/f32-vbinary/gen/vmul-minmax-wasm-x2.c",
    "src/f32-vbinary/gen/vmul-minmax-wasm-x4.c",
    "src/f32-vbinary/gen/vmul-minmax-wasm-x8.c",
    "src/f32-vbinary/gen/vmul-relu-wasm-x1.c",
    "src/f32-vbinary/gen/vmul-relu-wasm-x2.c",
    "src/f32-vbinary/gen/vmul-relu-wasm-x4.c",
    "src/f32-vbinary/gen/vmul-relu-wasm-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-wasm-x1.c",
    "src/f32-vbinary/gen/vmulc-minmax-wasm-x2.c",
    "src/f32-vbinary/gen/vmulc-minmax-wasm-x4.c",
    "src/f32-vbinary/gen/vmulc-minmax-wasm-x8.c",
    "src/f32-vbinary/gen/vmulc-relu-wasm-x1.c",
    "src/f32-vbinary/gen/vmulc-relu-wasm-x2.c",
    "src/f32-vbinary/gen/vmulc-relu-wasm-x4.c",
    "src/f32-vbinary/gen/vmulc-relu-wasm-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-wasm-x1.c",
    "src/f32-vbinary/gen/vrdivc-minmax-wasm-x2.c",
    "src/f32-vbinary/gen/vrdivc-minmax-wasm-x4.c",
    "src/f32-vbinary/gen/vrdivc-minmax-wasm-x8.c",
    "src/f32-vbinary/gen/vrdivc-relu-wasm-x1.c",
    "src/f32-vbinary/gen/vrdivc-relu-wasm-x2.c",
    "src/f32-vbinary/gen/vrdivc-relu-wasm-x4.c",
    "src/f32-vbinary/gen/vrdivc-relu-wasm-x8.c",
    "src/f32-vbinary/gen/vrsubc-minmax-wasm-x1.c",
    "src/f32-vbinary/gen/vrsubc-minmax-wasm-x2.c",
    "src/f32-vbinary/gen/vrsubc-minmax-wasm-x4.c",
    "src/f32-vbinary/gen/vrsubc-minmax-wasm-x8.c",
    "src/f32-vbinary/gen/vrsubc-relu-wasm-x1.c",
    "src/f32-vbinary/gen/vrsubc-relu-wasm-x2.c",
    "src/f32-vbinary/gen/vrsubc-relu-wasm-x4.c",
    "src/f32-vbinary/gen/vrsubc-relu-wasm-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-wasm-x1.c",
    "src/f32-vbinary/gen/vsub-minmax-wasm-x2.c",
    "src/f32-vbinary/gen/vsub-minmax-wasm-x4.c",
    "src/f32-vbinary/gen/vsub-minmax-wasm-x8.c",
    "src/f32-vbinary/gen/vsub-relu-wasm-x1.c",
    "src/f32-vbinary/gen/vsub-relu-wasm-x2.c",
    "src/f32-vbinary/gen/vsub-relu-wasm-x4.c",
    "src/f32-vbinary/gen/vsub-relu-wasm-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-wasm-x1.c",
    "src/f32-vbinary/gen/vsubc-minmax-wasm-x2.c",
    "src/f32-vbinary/gen/vsubc-minmax-wasm-x4.c",
    "src/f32-vbinary/gen/vsubc-minmax-wasm-x8.c",
    "src/f32-vbinary/gen/vsubc-relu-wasm-x1.c",
    "src/f32-vbinary/gen/vsubc-relu-wasm-x2.c",
    "src/f32-vbinary/gen/vsubc-relu-wasm-x4.c",
    "src/f32-vbinary/gen/vsubc-relu-wasm-x8.c",
    "src/f32-vclamp/gen/vclamp-wasm-x1.c",
    "src/f32-vclamp/gen/vclamp-wasm-x2.c",
    "src/f32-vclamp/gen/vclamp-wasm-x4.c",
    "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x1.c",
    "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x2.c",
    "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x3.c",
    "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x4.c",
    "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x5.c",
    "src/f32-velu/gen/velu-wasm-rr2-lut16-p3-x6.c",
    "src/f32-velu/gen/velu-wasm-rr2-p6-x1.c",
    "src/f32-velu/gen/velu-wasm-rr2-p6-x2.c",
    "src/f32-velu/gen/velu-wasm-rr2-p6-x3.c",
    "src/f32-velu/gen/velu-wasm-rr2-p6-x4.c",
    "src/f32-velu/gen/velu-wasm-rr2-p6-x5.c",
    "src/f32-velu/gen/velu-wasm-rr2-p6-x6.c",
    "src/f32-vhswish/gen/vhswish-wasm-x1.c",
    "src/f32-vhswish/gen/vhswish-wasm-x2.c",
    "src/f32-vhswish/gen/vhswish-wasm-x4.c",
    "src/f32-vlrelu/gen/vlrelu-wasm-x1.c",
    "src/f32-vlrelu/gen/vlrelu-wasm-x2.c",
    "src/f32-vlrelu/gen/vlrelu-wasm-x4.c",
    "src/f32-vmulcaddc/gen/c1-minmax-wasm-2x.c",
    "src/f32-vmulcaddc/gen/c2-minmax-wasm-2x.c",
    "src/f32-vmulcaddc/gen/c4-minmax-wasm-2x.c",
    "src/f32-vrelu/gen/vrelu-wasm-x1.c",
    "src/f32-vrelu/gen/vrelu-wasm-x2.c",
    "src/f32-vrelu/gen/vrelu-wasm-x4.c",
    "src/f32-vrelu/gen/vrelu-wasm-x8.c",
    "src/qc8-dwconv/gen/up1x9-minmax-fp32-wasm-fmagic.c",
    "src/qc8-dwconv/gen/up1x25-minmax-fp32-wasm-fmagic.c",
    "src/qc8-dwconv/gen/up2x3-minmax-fp32-wasm-fmagic.c",
    "src/qc8-dwconv/gen/up2x9-minmax-fp32-wasm-fmagic.c",
    "src/qc8-dwconv/gen/up2x25-minmax-fp32-wasm-fmagic.c",
    "src/qc8-dwconv/gen/up4x9-minmax-fp32-wasm-fmagic.c",
    "src/qc8-dwconv/gen/up4x25-minmax-fp32-wasm-fmagic.c",
    "src/qc8-gemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
    "src/qc8-gemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
    "src/qc8-gemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
    "src/qc8-gemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
    "src/qc8-gemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
    "src/qc8-gemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
    "src/qc8-gemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
    "src/qc8-gemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
    "src/qc8-igemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
    "src/qc8-igemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
    "src/qc8-igemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
    "src/qc8-igemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
    "src/qc8-igemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
    "src/qc8-igemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
    "src/qc8-igemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
    "src/qc8-igemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
    "src/qs8-dwconv/gen/up1x9-minmax-fp32-wasm-fmagic.c",
    "src/qs8-dwconv/gen/up1x25-minmax-fp32-wasm-fmagic.c",
    "src/qs8-dwconv/gen/up2x9-minmax-fp32-wasm-fmagic.c",
    "src/qs8-dwconv/gen/up2x25-minmax-fp32-wasm-fmagic.c",
    "src/qs8-dwconv/gen/up4x9-minmax-fp32-wasm-fmagic.c",
    "src/qs8-dwconv/gen/up4x25-minmax-fp32-wasm-fmagic.c",
    "src/qs8-gemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
    "src/qs8-gemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
    "src/qs8-gemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
    "src/qs8-gemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
    "src/qs8-gemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
    "src/qs8-gemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
    "src/qs8-gemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
    "src/qs8-gemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
    "src/qs8-igemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
    "src/qs8-igemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
    "src/qs8-igemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
    "src/qs8-igemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
    "src/qs8-igemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
    "src/qs8-igemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
    "src/qs8-igemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
    "src/qs8-igemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
    "src/qu8-dwconv/gen/up1x9-minmax-fp32-wasm-fmagic.c",
    "src/qu8-dwconv/gen/up1x25-minmax-fp32-wasm-fmagic.c",
    "src/qu8-dwconv/gen/up2x9-minmax-fp32-wasm-fmagic.c",
    "src/qu8-dwconv/gen/up2x25-minmax-fp32-wasm-fmagic.c",
    "src/qu8-dwconv/gen/up4x9-minmax-fp32-wasm-fmagic.c",
    "src/qu8-dwconv/gen/up4x25-minmax-fp32-wasm-fmagic.c",
    "src/qu8-gemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
    "src/qu8-gemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
    "src/qu8-gemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
    "src/qu8-gemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
    "src/qu8-gemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
    "src/qu8-gemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
    "src/qu8-gemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
    "src/qu8-gemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
    "src/qu8-igemm/gen/1x2-minmax-fp32-wasm-fmagic.c",
    "src/qu8-igemm/gen/1x4-minmax-fp32-wasm-fmagic.c",
    "src/qu8-igemm/gen/2x2-minmax-fp32-wasm-fmagic.c",
    "src/qu8-igemm/gen/2x4-minmax-fp32-wasm-fmagic.c",
    "src/qu8-igemm/gen/3x2-minmax-fp32-wasm-fmagic.c",
    "src/qu8-igemm/gen/3x4-minmax-fp32-wasm-fmagic.c",
    "src/qu8-igemm/gen/4x2-minmax-fp32-wasm-fmagic.c",
    "src/qu8-igemm/gen/4x4-minmax-fp32-wasm-fmagic.c",
]

ALL_WASMSIMD_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int16-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int16-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int16-x24.c",
    "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int16-x32.c",
    "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int32-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int32-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int32-x24.c",
    "src/f16-f32-vcvt/gen/vcvt-wasmsimd-int32-x32.c",
    "src/f32-argmaxpool/4x-wasmsimd-c4.c",
    "src/f32-argmaxpool/9p8x-wasmsimd-c4.c",
    "src/f32-argmaxpool/9x-wasmsimd-c4.c",
    "src/f32-avgpool/9p8x-minmax-wasmsimd-arm-c4.c",
    "src/f32-avgpool/9p8x-minmax-wasmsimd-x86-c4.c",
    "src/f32-avgpool/9x-minmax-wasmsimd-arm-c4.c",
    "src/f32-avgpool/9x-minmax-wasmsimd-x86-c4.c",
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-wasmsimd-2x2.c",
    "src/f32-dwconv/gen/up4x3-minmax-wasmsimd-arm-acc2.c",
    "src/f32-dwconv/gen/up4x3-minmax-wasmsimd-arm.c",
    "src/f32-dwconv/gen/up4x3-minmax-wasmsimd-x86-acc2.c",
    "src/f32-dwconv/gen/up4x3-minmax-wasmsimd-x86.c",
    "src/f32-dwconv/gen/up4x3-wasmsimd.c",
    "src/f32-dwconv/gen/up4x4-minmax-wasmsimd-arm-acc2.c",
    "src/f32-dwconv/gen/up4x4-minmax-wasmsimd-arm.c",
    "src/f32-dwconv/gen/up4x4-minmax-wasmsimd-x86-acc2.c",
    "src/f32-dwconv/gen/up4x4-minmax-wasmsimd-x86.c",
    "src/f32-dwconv/gen/up4x4-wasmsimd.c",
    "src/f32-dwconv/gen/up4x9-minmax-wasmsimd-arm-acc2.c",
    "src/f32-dwconv/gen/up4x9-minmax-wasmsimd-arm.c",
    "src/f32-dwconv/gen/up4x9-minmax-wasmsimd-x86-acc2.c",
    "src/f32-dwconv/gen/up4x9-minmax-wasmsimd-x86.c",
    "src/f32-dwconv/gen/up4x9-wasmsimd-acc2.c",
    "src/f32-dwconv/gen/up4x9-wasmsimd.c",
    "src/f32-dwconv/gen/up4x25-minmax-wasmsimd-arm-acc2.c",
    "src/f32-dwconv/gen/up4x25-minmax-wasmsimd-arm.c",
    "src/f32-dwconv/gen/up4x25-minmax-wasmsimd-x86-acc2.c",
    "src/f32-dwconv/gen/up4x25-minmax-wasmsimd-x86.c",
    "src/f32-dwconv/gen/up4x25-wasmsimd.c",
    "src/f32-dwconv/gen/up8x3-minmax-wasmsimd-arm-acc2.c",
    "src/f32-dwconv/gen/up8x3-minmax-wasmsimd-arm.c",
    "src/f32-dwconv/gen/up8x3-minmax-wasmsimd-x86-acc2.c",
    "src/f32-dwconv/gen/up8x3-minmax-wasmsimd-x86.c",
    "src/f32-dwconv/gen/up8x3-wasmsimd.c",
    "src/f32-dwconv/gen/up8x4-minmax-wasmsimd-arm-acc2.c",
    "src/f32-dwconv/gen/up8x4-minmax-wasmsimd-arm.c",
    "src/f32-dwconv/gen/up8x4-minmax-wasmsimd-x86-acc2.c",
    "src/f32-dwconv/gen/up8x4-minmax-wasmsimd-x86.c",
    "src/f32-dwconv/gen/up8x4-wasmsimd.c",
    "src/f32-dwconv/gen/up8x9-minmax-wasmsimd-arm-acc2.c",
    "src/f32-dwconv/gen/up8x9-minmax-wasmsimd-arm.c",
    "src/f32-dwconv/gen/up8x9-minmax-wasmsimd-x86-acc2.c",
    "src/f32-dwconv/gen/up8x9-minmax-wasmsimd-x86.c",
    "src/f32-dwconv/gen/up8x9-wasmsimd-acc2.c",
    "src/f32-dwconv/gen/up8x9-wasmsimd.c",
    "src/f32-dwconv/gen/up8x25-minmax-wasmsimd-arm-acc2.c",
    "src/f32-dwconv/gen/up8x25-minmax-wasmsimd-arm.c",
    "src/f32-dwconv/gen/up8x25-minmax-wasmsimd-x86-acc2.c",
    "src/f32-dwconv/gen/up8x25-minmax-wasmsimd-x86.c",
    "src/f32-dwconv/gen/up8x25-wasmsimd.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-4x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-5x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-loadsplat-6x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-4x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-5x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-arm-splat-6x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-4x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-5x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-loadsplat-6x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-4x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-5x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-wasmsimd-x86-splat-6x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-loadsplat-4x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-arm-splat-4x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-loadsplat-4x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-wasmsimd-x86-splat-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-3x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-4x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-loadsplat-5x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-3x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-4x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-arm-splat-5x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-3x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-4x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-loadsplat-5x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-3x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-4x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-wasmsimd-x86-splat-5x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-loadsplat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-loadsplat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-loadsplat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-loadsplat-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-loadsplat-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-loadsplat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-loadsplat-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-loadsplat-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-loadsplat-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-loadsplat-3x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-splat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-splat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-splat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-splat-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-splat-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-splat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-splat-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-splat-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-splat-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-arm-splat-3x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-loadsplat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-loadsplat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-loadsplat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-loadsplat-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-loadsplat-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-loadsplat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-loadsplat-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-loadsplat-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-loadsplat-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-loadsplat-3x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-splat-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-splat-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-splat-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-splat-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-splat-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-splat-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-splat-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-splat-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-splat-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-wasmsimd-x86-splat-3x4.c",
    "src/f32-f16-vcvt/gen/vcvt-wasmsimd-x8.c",
    "src/f32-f16-vcvt/gen/vcvt-wasmsimd-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-wasmsimd-x24.c",
    "src/f32-f16-vcvt/gen/vcvt-wasmsimd-x32.c",
    "src/f32-gavgpool-cw/wasmsimd-arm-x4.c",
    "src/f32-gavgpool-cw/wasmsimd-x86-x4.c",
    "src/f32-gavgpool/7p7x-minmax-wasmsimd-arm-c4.c",
    "src/f32-gavgpool/7p7x-minmax-wasmsimd-x86-c4.c",
    "src/f32-gavgpool/7x-minmax-wasmsimd-arm-c4.c",
    "src/f32-gavgpool/7x-minmax-wasmsimd-x86-c4.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-wasmsimd-arm-splat.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-wasmsimd-x86-splat.c",
    "src/f32-gemm/gen-inc/1x8s4inc-minmax-wasmsimd-arm.c",
    "src/f32-gemm/gen-inc/1x8s4inc-minmax-wasmsimd-x86.c",
    "src/f32-gemm/gen-inc/3x8inc-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-gemm/gen-inc/3x8inc-minmax-wasmsimd-arm-splat.c",
    "src/f32-gemm/gen-inc/3x8inc-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-gemm/gen-inc/3x8inc-minmax-wasmsimd-x86-splat.c",
    "src/f32-gemm/gen-inc/3x8s4inc-minmax-wasmsimd-arm.c",
    "src/f32-gemm/gen-inc/3x8s4inc-minmax-wasmsimd-x86.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-wasmsimd-arm-splat.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-wasmsimd-x86-splat.c",
    "src/f32-gemm/gen-inc/4x8s4inc-minmax-wasmsimd-arm.c",
    "src/f32-gemm/gen-inc/4x8s4inc-minmax-wasmsimd-x86.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-wasmsimd-arm-splat.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-wasmsimd-x86-splat.c",
    "src/f32-gemm/gen-inc/5x8s4inc-minmax-wasmsimd-arm.c",
    "src/f32-gemm/gen-inc/5x8s4inc-minmax-wasmsimd-x86.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-wasmsimd-arm-splat.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-wasmsimd-x86-splat.c",
    "src/f32-gemm/gen-inc/6x8s4inc-minmax-wasmsimd-arm.c",
    "src/f32-gemm/gen-inc/6x8s4inc-minmax-wasmsimd-x86.c",
    "src/f32-gemm/gen/1x8-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-gemm/gen/1x8-minmax-wasmsimd-arm-splat.c",
    "src/f32-gemm/gen/1x8-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-gemm/gen/1x8-minmax-wasmsimd-x86-splat.c",
    "src/f32-gemm/gen/1x8-relu-wasmsimd-loadsplat.c",
    "src/f32-gemm/gen/1x8-relu-wasmsimd-splat.c",
    "src/f32-gemm/gen/1x8-wasmsimd-loadsplat.c",
    "src/f32-gemm/gen/1x8-wasmsimd-splat.c",
    "src/f32-gemm/gen/1x8s4-minmax-wasmsimd-arm.c",
    "src/f32-gemm/gen/1x8s4-minmax-wasmsimd-x86.c",
    "src/f32-gemm/gen/1x8s4-relu-wasmsimd.c",
    "src/f32-gemm/gen/1x8s4-wasmsimd.c",
    "src/f32-gemm/gen/3x8-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-gemm/gen/3x8-minmax-wasmsimd-arm-splat.c",
    "src/f32-gemm/gen/3x8-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-gemm/gen/3x8-minmax-wasmsimd-x86-splat.c",
    "src/f32-gemm/gen/3x8-relu-wasmsimd-loadsplat.c",
    "src/f32-gemm/gen/3x8-relu-wasmsimd-splat.c",
    "src/f32-gemm/gen/3x8-wasmsimd-loadsplat.c",
    "src/f32-gemm/gen/3x8-wasmsimd-splat.c",
    "src/f32-gemm/gen/3x8s4-minmax-wasmsimd-arm.c",
    "src/f32-gemm/gen/3x8s4-minmax-wasmsimd-x86.c",
    "src/f32-gemm/gen/3x8s4-relu-wasmsimd.c",
    "src/f32-gemm/gen/3x8s4-wasmsimd.c",
    "src/f32-gemm/gen/4x2c4-minmax-wasmsimd-arm.c",
    "src/f32-gemm/gen/4x2c4-minmax-wasmsimd-x86.c",
    "src/f32-gemm/gen/4x2c4-relu-wasmsimd.c",
    "src/f32-gemm/gen/4x2c4-wasmsimd.c",
    "src/f32-gemm/gen/4x8-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-gemm/gen/4x8-minmax-wasmsimd-arm-splat.c",
    "src/f32-gemm/gen/4x8-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-gemm/gen/4x8-minmax-wasmsimd-x86-splat.c",
    "src/f32-gemm/gen/4x8-relu-wasmsimd-loadsplat.c",
    "src/f32-gemm/gen/4x8-relu-wasmsimd-splat.c",
    "src/f32-gemm/gen/4x8-wasmsimd-loadsplat.c",
    "src/f32-gemm/gen/4x8-wasmsimd-splat.c",
    "src/f32-gemm/gen/4x8s4-minmax-wasmsimd-arm.c",
    "src/f32-gemm/gen/4x8s4-minmax-wasmsimd-x86.c",
    "src/f32-gemm/gen/4x8s4-relu-wasmsimd.c",
    "src/f32-gemm/gen/4x8s4-wasmsimd.c",
    "src/f32-gemm/gen/5x8-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-gemm/gen/5x8-minmax-wasmsimd-arm-splat.c",
    "src/f32-gemm/gen/5x8-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-gemm/gen/5x8-minmax-wasmsimd-x86-splat.c",
    "src/f32-gemm/gen/5x8-relu-wasmsimd-loadsplat.c",
    "src/f32-gemm/gen/5x8-relu-wasmsimd-splat.c",
    "src/f32-gemm/gen/5x8-wasmsimd-loadsplat.c",
    "src/f32-gemm/gen/5x8-wasmsimd-splat.c",
    "src/f32-gemm/gen/5x8s4-minmax-wasmsimd-arm.c",
    "src/f32-gemm/gen/5x8s4-minmax-wasmsimd-x86.c",
    "src/f32-gemm/gen/5x8s4-relu-wasmsimd.c",
    "src/f32-gemm/gen/5x8s4-wasmsimd.c",
    "src/f32-gemm/gen/6x8-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-gemm/gen/6x8-minmax-wasmsimd-arm-splat.c",
    "src/f32-gemm/gen/6x8-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-gemm/gen/6x8-minmax-wasmsimd-x86-splat.c",
    "src/f32-gemm/gen/6x8-relu-wasmsimd-loadsplat.c",
    "src/f32-gemm/gen/6x8-relu-wasmsimd-splat.c",
    "src/f32-gemm/gen/6x8-wasmsimd-loadsplat.c",
    "src/f32-gemm/gen/6x8-wasmsimd-splat.c",
    "src/f32-gemm/gen/6x8s4-minmax-wasmsimd-arm.c",
    "src/f32-gemm/gen/6x8s4-minmax-wasmsimd-x86.c",
    "src/f32-gemm/gen/6x8s4-relu-wasmsimd.c",
    "src/f32-gemm/gen/6x8s4-wasmsimd.c",
    "src/f32-ibilinear-chw/gen/wasmsimd-p4.c",
    "src/f32-ibilinear-chw/gen/wasmsimd-p8.c",
    "src/f32-ibilinear/gen/wasmsimd-c4.c",
    "src/f32-ibilinear/gen/wasmsimd-c8.c",
    "src/f32-igemm/gen/1x8-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-igemm/gen/1x8-minmax-wasmsimd-arm-splat.c",
    "src/f32-igemm/gen/1x8-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-igemm/gen/1x8-minmax-wasmsimd-x86-splat.c",
    "src/f32-igemm/gen/1x8-relu-wasmsimd-loadsplat.c",
    "src/f32-igemm/gen/1x8-relu-wasmsimd-splat.c",
    "src/f32-igemm/gen/1x8-wasmsimd-loadsplat.c",
    "src/f32-igemm/gen/1x8-wasmsimd-splat.c",
    "src/f32-igemm/gen/1x8s4-minmax-wasmsimd-arm.c",
    "src/f32-igemm/gen/1x8s4-minmax-wasmsimd-x86.c",
    "src/f32-igemm/gen/1x8s4-relu-wasmsimd.c",
    "src/f32-igemm/gen/1x8s4-wasmsimd.c",
    "src/f32-igemm/gen/3x8-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-igemm/gen/3x8-minmax-wasmsimd-arm-splat.c",
    "src/f32-igemm/gen/3x8-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-igemm/gen/3x8-minmax-wasmsimd-x86-splat.c",
    "src/f32-igemm/gen/3x8-relu-wasmsimd-loadsplat.c",
    "src/f32-igemm/gen/3x8-relu-wasmsimd-splat.c",
    "src/f32-igemm/gen/3x8-wasmsimd-loadsplat.c",
    "src/f32-igemm/gen/3x8-wasmsimd-splat.c",
    "src/f32-igemm/gen/3x8s4-minmax-wasmsimd-arm.c",
    "src/f32-igemm/gen/3x8s4-minmax-wasmsimd-x86.c",
    "src/f32-igemm/gen/3x8s4-relu-wasmsimd.c",
    "src/f32-igemm/gen/3x8s4-wasmsimd.c",
    "src/f32-igemm/gen/4x2c4-minmax-wasmsimd-arm.c",
    "src/f32-igemm/gen/4x2c4-minmax-wasmsimd-x86.c",
    "src/f32-igemm/gen/4x2c4-relu-wasmsimd.c",
    "src/f32-igemm/gen/4x2c4-wasmsimd.c",
    "src/f32-igemm/gen/4x8-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-igemm/gen/4x8-minmax-wasmsimd-arm-splat.c",
    "src/f32-igemm/gen/4x8-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-igemm/gen/4x8-minmax-wasmsimd-x86-splat.c",
    "src/f32-igemm/gen/4x8-relu-wasmsimd-loadsplat.c",
    "src/f32-igemm/gen/4x8-relu-wasmsimd-splat.c",
    "src/f32-igemm/gen/4x8-wasmsimd-loadsplat.c",
    "src/f32-igemm/gen/4x8-wasmsimd-splat.c",
    "src/f32-igemm/gen/4x8s4-minmax-wasmsimd-arm.c",
    "src/f32-igemm/gen/4x8s4-minmax-wasmsimd-x86.c",
    "src/f32-igemm/gen/4x8s4-relu-wasmsimd.c",
    "src/f32-igemm/gen/4x8s4-wasmsimd.c",
    "src/f32-igemm/gen/5x8-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-igemm/gen/5x8-minmax-wasmsimd-arm-splat.c",
    "src/f32-igemm/gen/5x8-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-igemm/gen/5x8-minmax-wasmsimd-x86-splat.c",
    "src/f32-igemm/gen/5x8-relu-wasmsimd-loadsplat.c",
    "src/f32-igemm/gen/5x8-relu-wasmsimd-splat.c",
    "src/f32-igemm/gen/5x8-wasmsimd-loadsplat.c",
    "src/f32-igemm/gen/5x8-wasmsimd-splat.c",
    "src/f32-igemm/gen/5x8s4-minmax-wasmsimd-arm.c",
    "src/f32-igemm/gen/5x8s4-minmax-wasmsimd-x86.c",
    "src/f32-igemm/gen/5x8s4-relu-wasmsimd.c",
    "src/f32-igemm/gen/5x8s4-wasmsimd.c",
    "src/f32-igemm/gen/6x8-minmax-wasmsimd-arm-loadsplat.c",
    "src/f32-igemm/gen/6x8-minmax-wasmsimd-arm-splat.c",
    "src/f32-igemm/gen/6x8-minmax-wasmsimd-x86-loadsplat.c",
    "src/f32-igemm/gen/6x8-minmax-wasmsimd-x86-splat.c",
    "src/f32-igemm/gen/6x8-relu-wasmsimd-loadsplat.c",
    "src/f32-igemm/gen/6x8-relu-wasmsimd-splat.c",
    "src/f32-igemm/gen/6x8-wasmsimd-loadsplat.c",
    "src/f32-igemm/gen/6x8-wasmsimd-splat.c",
    "src/f32-igemm/gen/6x8s4-minmax-wasmsimd-arm.c",
    "src/f32-igemm/gen/6x8s4-minmax-wasmsimd-x86.c",
    "src/f32-igemm/gen/6x8s4-relu-wasmsimd.c",
    "src/f32-igemm/gen/6x8s4-wasmsimd.c",
    "src/f32-maxpool/9p8x-minmax-wasmsimd-arm-c4.c",
    "src/f32-maxpool/9p8x-minmax-wasmsimd-x86-c4.c",
    "src/f32-pavgpool/9p8x-minmax-wasmsimd-arm-c4.c",
    "src/f32-pavgpool/9p8x-minmax-wasmsimd-x86-c4.c",
    "src/f32-pavgpool/9x-minmax-wasmsimd-arm-c4.c",
    "src/f32-pavgpool/9x-minmax-wasmsimd-x86-c4.c",
    "src/f32-ppmm/gen/4x8-minmax-wasmsimd-arm-splat.c",
    "src/f32-ppmm/gen/4x8-minmax-wasmsimd-x86-splat.c",
    "src/f32-prelu/gen/wasmsimd-bitselect-1x4.c",
    "src/f32-prelu/gen/wasmsimd-bitselect-1x8.c",
    "src/f32-prelu/gen/wasmsimd-bitselect-1x16.c",
    "src/f32-prelu/gen/wasmsimd-bitselect-2x4.c",
    "src/f32-prelu/gen/wasmsimd-bitselect-2x8.c",
    "src/f32-prelu/gen/wasmsimd-bitselect-2x16.c",
    "src/f32-prelu/gen/wasmsimd-bitselect-4x4.c",
    "src/f32-prelu/gen/wasmsimd-bitselect-4x8.c",
    "src/f32-prelu/gen/wasmsimd-bitselect-4x16.c",
    "src/f32-prelu/gen/wasmsimd-minmax-1x4.c",
    "src/f32-prelu/gen/wasmsimd-minmax-1x8.c",
    "src/f32-prelu/gen/wasmsimd-minmax-1x16.c",
    "src/f32-prelu/gen/wasmsimd-minmax-2x4.c",
    "src/f32-prelu/gen/wasmsimd-minmax-2x8.c",
    "src/f32-prelu/gen/wasmsimd-minmax-2x16.c",
    "src/f32-prelu/gen/wasmsimd-minmax-4x4.c",
    "src/f32-prelu/gen/wasmsimd-minmax-4x8.c",
    "src/f32-prelu/gen/wasmsimd-minmax-4x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasmsimd-cvt-x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasmsimd-cvt-x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasmsimd-cvt-x24.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasmsimd-cvt-x32.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasmsimd-magic-x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasmsimd-magic-x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasmsimd-magic-x24.c",
    "src/f32-qs8-vcvt/gen/vcvt-wasmsimd-magic-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasmsimd-cvt-x8.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasmsimd-cvt-x16.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasmsimd-cvt-x24.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasmsimd-cvt-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasmsimd-magic-x8.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasmsimd-magic-x16.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasmsimd-magic-x24.c",
    "src/f32-qu8-vcvt/gen/vcvt-wasmsimd-magic-x32.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x4.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x8-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x8.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x12-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x12-acc3.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x12.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x16-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x16-acc4.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x16.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x20-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x20-acc5.c",
    "src/f32-raddstoreexpminusmax/gen/wasmsimd-rr2-p5-x20.c",
    "src/f32-rmax/wasmsimd-arm.c",
    "src/f32-rmax/wasmsimd-x86.c",
    "src/f32-spmm/gen/4x1-minmax-wasmsimd-arm-pipelined-x2.c",
    "src/f32-spmm/gen/4x1-minmax-wasmsimd-arm-pipelined.c",
    "src/f32-spmm/gen/4x1-minmax-wasmsimd-arm-x2.c",
    "src/f32-spmm/gen/4x1-minmax-wasmsimd-arm-x4.c",
    "src/f32-spmm/gen/4x1-minmax-wasmsimd-arm.c",
    "src/f32-spmm/gen/4x1-minmax-wasmsimd-x86-pipelined-x2.c",
    "src/f32-spmm/gen/4x1-minmax-wasmsimd-x86-pipelined.c",
    "src/f32-spmm/gen/4x1-minmax-wasmsimd-x86-x2.c",
    "src/f32-spmm/gen/4x1-minmax-wasmsimd-x86-x4.c",
    "src/f32-spmm/gen/4x1-minmax-wasmsimd-x86.c",
    "src/f32-spmm/gen/8x1-minmax-wasmsimd-arm-pipelined-x2.c",
    "src/f32-spmm/gen/8x1-minmax-wasmsimd-arm-pipelined.c",
    "src/f32-spmm/gen/8x1-minmax-wasmsimd-arm-x2.c",
    "src/f32-spmm/gen/8x1-minmax-wasmsimd-arm-x4.c",
    "src/f32-spmm/gen/8x1-minmax-wasmsimd-arm.c",
    "src/f32-spmm/gen/8x1-minmax-wasmsimd-x86-pipelined-x2.c",
    "src/f32-spmm/gen/8x1-minmax-wasmsimd-x86-pipelined.c",
    "src/f32-spmm/gen/8x1-minmax-wasmsimd-x86-x2.c",
    "src/f32-spmm/gen/8x1-minmax-wasmsimd-x86-x4.c",
    "src/f32-spmm/gen/8x1-minmax-wasmsimd-x86.c",
    "src/f32-spmm/gen/16x1-minmax-wasmsimd-arm-pipelined-x2.c",
    "src/f32-spmm/gen/16x1-minmax-wasmsimd-arm-pipelined.c",
    "src/f32-spmm/gen/16x1-minmax-wasmsimd-arm-x2.c",
    "src/f32-spmm/gen/16x1-minmax-wasmsimd-arm-x4.c",
    "src/f32-spmm/gen/16x1-minmax-wasmsimd-arm.c",
    "src/f32-spmm/gen/16x1-minmax-wasmsimd-x86-pipelined-x2.c",
    "src/f32-spmm/gen/16x1-minmax-wasmsimd-x86-pipelined.c",
    "src/f32-spmm/gen/16x1-minmax-wasmsimd-x86-x2.c",
    "src/f32-spmm/gen/16x1-minmax-wasmsimd-x86-x4.c",
    "src/f32-spmm/gen/16x1-minmax-wasmsimd-x86.c",
    "src/f32-spmm/gen/32x1-minmax-wasmsimd-arm-pipelined-x2.c",
    "src/f32-spmm/gen/32x1-minmax-wasmsimd-arm-pipelined.c",
    "src/f32-spmm/gen/32x1-minmax-wasmsimd-arm-x2.c",
    "src/f32-spmm/gen/32x1-minmax-wasmsimd-arm-x4.c",
    "src/f32-spmm/gen/32x1-minmax-wasmsimd-arm.c",
    "src/f32-spmm/gen/32x1-minmax-wasmsimd-x86-pipelined-x2.c",
    "src/f32-spmm/gen/32x1-minmax-wasmsimd-x86-pipelined.c",
    "src/f32-spmm/gen/32x1-minmax-wasmsimd-x86-x2.c",
    "src/f32-spmm/gen/32x1-minmax-wasmsimd-x86-x4.c",
    "src/f32-spmm/gen/32x1-minmax-wasmsimd-x86.c",
    "src/f32-vbinary/gen/vadd-minmax-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vadd-minmax-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vadd-minmax-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vadd-minmax-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vadd-minmax-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vadd-minmax-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vadd-relu-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vadd-relu-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vadd-relu-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vadd-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vadd-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vadd-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vaddc-minmax-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vaddc-minmax-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vaddc-minmax-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vaddc-minmax-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vaddc-relu-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vaddc-relu-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vaddc-relu-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vaddc-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vaddc-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vaddc-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vdiv-minmax-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vdiv-minmax-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vdiv-minmax-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vdiv-minmax-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vdiv-minmax-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vdiv-minmax-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vdiv-relu-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vdiv-relu-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vdiv-relu-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vdiv-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vdiv-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vdiv-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vdivc-minmax-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vdivc-minmax-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vdivc-minmax-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vdivc-minmax-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vdivc-minmax-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vdivc-minmax-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vdivc-relu-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vdivc-relu-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vdivc-relu-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vdivc-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vdivc-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vdivc-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vmax-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vmax-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vmax-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vmax-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vmax-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vmax-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vmaxc-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vmaxc-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vmaxc-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vmaxc-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vmaxc-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vmaxc-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vmin-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vmin-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vmin-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vmin-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vmin-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vmin-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vminc-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vminc-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vminc-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vminc-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vminc-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vminc-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vmul-minmax-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vmul-minmax-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vmul-minmax-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vmul-minmax-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vmul-relu-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vmul-relu-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vmul-relu-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vmul-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vmul-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vmul-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vmulc-minmax-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vmulc-minmax-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vmulc-minmax-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vmulc-minmax-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vmulc-relu-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vmulc-relu-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vmulc-relu-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vmulc-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vmulc-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vmulc-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vrdivc-minmax-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vrdivc-minmax-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vrdivc-minmax-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vrdivc-minmax-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vrdivc-relu-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vrdivc-relu-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vrdivc-relu-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vrdivc-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vrdivc-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vrdivc-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vrsubc-minmax-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vrsubc-minmax-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vrsubc-minmax-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vrsubc-minmax-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vrsubc-minmax-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vrsubc-minmax-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vrsubc-relu-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vrsubc-relu-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vrsubc-relu-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vrsubc-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vrsubc-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vrsubc-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vsqrdiff-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vsqrdiff-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vsqrdiff-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vsqrdiffc-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vsqrdiffc-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vsqrdiffc-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vsub-minmax-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vsub-minmax-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vsub-minmax-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vsub-minmax-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vsub-relu-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vsub-relu-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vsub-relu-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vsub-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vsub-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vsub-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vsubc-minmax-wasmsimd-arm-x4.c",
    "src/f32-vbinary/gen/vsubc-minmax-wasmsimd-arm-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-wasmsimd-arm-x16.c",
    "src/f32-vbinary/gen/vsubc-minmax-wasmsimd-x86-x4.c",
    "src/f32-vbinary/gen/vsubc-minmax-wasmsimd-x86-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-wasmsimd-x86-x16.c",
    "src/f32-vbinary/gen/vsubc-relu-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vsubc-relu-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vsubc-relu-wasmsimd-x16.c",
    "src/f32-vbinary/gen/vsubc-wasmsimd-x4.c",
    "src/f32-vbinary/gen/vsubc-wasmsimd-x8.c",
    "src/f32-vbinary/gen/vsubc-wasmsimd-x16.c",
    "src/f32-vclamp/gen/vclamp-wasmsimd-arm-x4.c",
    "src/f32-vclamp/gen/vclamp-wasmsimd-arm-x8.c",
    "src/f32-vclamp/gen/vclamp-wasmsimd-x86-x4.c",
    "src/f32-vclamp/gen/vclamp-wasmsimd-x86-x8.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-lut16-p3-x4.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-lut16-p3-x8.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-lut16-p3-x12.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-lut16-p3-x16.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-lut16-p3-x20.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-lut16-p3-x24.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x4.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x8.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x12.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x16.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x20.c",
    "src/f32-velu/gen/velu-wasmsimd-arm-rr2-p6-x24.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x4.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x8.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x12.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x16.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x20.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-lut16-p3-x24.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-p6-x4.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-p6-x8.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-p6-x12.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-p6-x16.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-p6-x20.c",
    "src/f32-velu/gen/velu-wasmsimd-x86-rr2-p6-x24.c",
    "src/f32-vhswish/gen/vhswish-wasmsimd-x4.c",
    "src/f32-vhswish/gen/vhswish-wasmsimd-x8.c",
    "src/f32-vhswish/gen/vhswish-wasmsimd-x16.c",
    "src/f32-vlrelu/gen/vlrelu-wasmsimd-bitselect-x4.c",
    "src/f32-vlrelu/gen/vlrelu-wasmsimd-bitselect-x8.c",
    "src/f32-vlrelu/gen/vlrelu-wasmsimd-minmax-x4.c",
    "src/f32-vlrelu/gen/vlrelu-wasmsimd-minmax-x8.c",
    "src/f32-vmulcaddc/gen/c4-minmax-wasmsimd-arm-2x.c",
    "src/f32-vmulcaddc/gen/c4-minmax-wasmsimd-x86-2x.c",
    "src/f32-vmulcaddc/gen/c8-minmax-wasmsimd-arm-2x.c",
    "src/f32-vmulcaddc/gen/c8-minmax-wasmsimd-x86-2x.c",
    "src/f32-vrelu/gen/vrelu-wasmsimd-x4.c",
    "src/f32-vrelu/gen/vrelu-wasmsimd-x8.c",
    "src/f32-vrelu/gen/vrelu-wasmsimd-x16.c",
    "src/f32-vrnd/gen/vrndd-wasmsimd-x4.c",
    "src/f32-vrnd/gen/vrndd-wasmsimd-x8.c",
    "src/f32-vrnd/gen/vrndne-wasmsimd-x4.c",
    "src/f32-vrnd/gen/vrndne-wasmsimd-x8.c",
    "src/f32-vrnd/gen/vrndu-wasmsimd-x4.c",
    "src/f32-vrnd/gen/vrndu-wasmsimd-x8.c",
    "src/f32-vrnd/gen/vrndz-wasmsimd-x4.c",
    "src/f32-vrnd/gen/vrndz-wasmsimd-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-lut64-p2-div-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-lut64-p2-div-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-lut64-p2-div-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-lut64-p2-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-lut64-p2-div-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-lut64-p2-div-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-p5-div-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-p5-div-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-p5-div-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-p5-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-p5-div-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-wasmsimd-rr2-p5-div-x24.c",
    "src/f32-vsqrt/gen/wasmsimd-sqrt-x4.c",
    "src/f32-vsqrt/gen/wasmsimd-sqrt-x8.c",
    "src/f32-vunary/gen/vabs-wasmsimd-x4.c",
    "src/f32-vunary/gen/vabs-wasmsimd-x8.c",
    "src/f32-vunary/gen/vneg-wasmsimd-x4.c",
    "src/f32-vunary/gen/vneg-wasmsimd-x8.c",
    "src/f32-vunary/gen/vsqr-wasmsimd-x4.c",
    "src/f32-vunary/gen/vsqr-wasmsimd-x8.c",
    "src/math/cvt-f16-f32-wasmsimd-int16.c",
    "src/math/cvt-f16-f32-wasmsimd-int32.c",
    "src/math/cvt-f32-f16-wasmsimd.c",
    "src/math/cvt-f32-qs8-wasmsimd.c",
    "src/math/cvt-f32-qu8-wasmsimd.c",
    "src/math/expm1minus-f32-wasmsimd-rr2-lut16-p3-andnot.c",
    "src/math/expm1minus-f32-wasmsimd-rr2-lut16-p3-max.c",
    "src/math/expm1minus-f32-wasmsimd-rr2-p6-andnot.c",
    "src/math/expm1minus-f32-wasmsimd-rr2-p6-max.c",
    "src/math/roundd-wasmsimd-addsub.c",
    "src/math/roundd-wasmsimd-cvt.c",
    "src/math/roundd-wasmsimd-native.c",
    "src/math/roundne-wasmsimd-addsub.c",
    "src/math/roundne-wasmsimd-native.c",
    "src/math/roundu-wasmsimd-addsub.c",
    "src/math/roundu-wasmsimd-cvt.c",
    "src/math/roundu-wasmsimd-native.c",
    "src/math/roundz-wasmsimd-addsub.c",
    "src/math/roundz-wasmsimd-cvt.c",
    "src/math/roundz-wasmsimd-native.c",
    "src/math/sigmoid-f32-wasmsimd-rr2-lut64-p2-div.c",
    "src/math/sigmoid-f32-wasmsimd-rr2-p5-div.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-wasmsimd-mul16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-wasmsimd-mul16.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-wasmsimd-mul16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-wasmsimd-mul16.c",
    "src/qc8-dwconv/gen/up24x9-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qc8-dwconv/gen/up24x9-minmax-fp32-wasmsimd-mul16.c",
    "src/qc8-dwconv/gen/up24x25-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qc8-dwconv/gen/up24x25-minmax-fp32-wasmsimd-mul16.c",
    "src/qc8-gemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-gemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-gemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-gemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-gemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-gemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qc8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qc8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-wasmsimd-mul16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-wasmsimd-mul16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-wasmsimd-mul16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-wasmsimd-mul16.c",
    "src/qs8-dwconv/gen/up24x9-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qs8-dwconv/gen/up24x9-minmax-fp32-wasmsimd-mul16.c",
    "src/qs8-dwconv/gen/up24x25-minmax-fp32-wasmsimd-mul16-add16.c",
    "src/qs8-dwconv/gen/up24x25-minmax-fp32-wasmsimd-mul16.c",
    "src/qs8-f32-vcvt/gen/vcvt-wasmsimd-x8.c",
    "src/qs8-f32-vcvt/gen/vcvt-wasmsimd-x16.c",
    "src/qs8-f32-vcvt/gen/vcvt-wasmsimd-x24.c",
    "src/qs8-f32-vcvt/gen/vcvt-wasmsimd-x32.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c8.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c16.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c24.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c32.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c8.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c16.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c24.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c32.c",
    "src/qs8-gemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c",
    "src/qs8-gemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c",
    "src/qs8-gemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c",
    "src/qs8-gemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c",
    "src/qs8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c",
    "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c",
    "src/qs8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-wasmsimd-dot16x2.c",
    "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-gemm/gen/4x4c8-xw-minmax-fp32-wasmsimd-dot16x2.c",
    "src/qs8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qs8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qs8-requantization/fp32-wasmsimd.c",
    "src/qs8-requantization/gemmlowp-wasmsimd.c",
    "src/qs8-vadd/gen/minmax-wasmsimd-x8.c",
    "src/qs8-vadd/gen/minmax-wasmsimd-x16.c",
    "src/qs8-vadd/gen/minmax-wasmsimd-x24.c",
    "src/qs8-vadd/gen/minmax-wasmsimd-x32.c",
    "src/qs8-vaddc/gen/minmax-wasmsimd-x8.c",
    "src/qs8-vaddc/gen/minmax-wasmsimd-x16.c",
    "src/qs8-vaddc/gen/minmax-wasmsimd-x24.c",
    "src/qs8-vaddc/gen/minmax-wasmsimd-x32.c",
    "src/qs8-vcvt/gen/vcvt-wasmsimd-x8.c",
    "src/qs8-vcvt/gen/vcvt-wasmsimd-x16.c",
    "src/qs8-vcvt/gen/vcvt-wasmsimd-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-wasmsimd-arm-x16.c",
    "src/qs8-vlrelu/gen/vlrelu-wasmsimd-arm-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-wasmsimd-x86-x8.c",
    "src/qs8-vlrelu/gen/vlrelu-wasmsimd-x86-x16.c",
    "src/qs8-vlrelu/gen/vlrelu-wasmsimd-x86-x32.c",
    "src/qs8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
    "src/qs8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
    "src/qs8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
    "src/qs8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-wasmsimd-mul16.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-wasmsimd-mul16.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-wasmsimd-mul16.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-wasmsimd-mul16.c",
    "src/qu8-dwconv/gen/up24x9-minmax-fp32-wasmsimd-mul16.c",
    "src/qu8-dwconv/gen/up24x25-minmax-fp32-wasmsimd-mul16.c",
    "src/qu8-f32-vcvt/gen/vcvt-wasmsimd-x8.c",
    "src/qu8-f32-vcvt/gen/vcvt-wasmsimd-x16.c",
    "src/qu8-f32-vcvt/gen/vcvt-wasmsimd-x24.c",
    "src/qu8-f32-vcvt/gen/vcvt-wasmsimd-x32.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c8.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c16.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c24.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-wasmsimd-c32.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c8.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c16.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c24.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-wasmsimd-c32.c",
    "src/qu8-gemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-gemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-gemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/1x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/2x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/3x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/4x4c2-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld64.c",
    "src/qu8-igemm/gen/4x4c8-minmax-fp32-wasmsimd-dot16x2-ld128.c",
    "src/qu8-requantization/fp32-wasmsimd.c",
    "src/qu8-requantization/gemmlowp-wasmsimd.c",
    "src/qu8-vadd/gen/minmax-wasmsimd-x8.c",
    "src/qu8-vadd/gen/minmax-wasmsimd-x16.c",
    "src/qu8-vadd/gen/minmax-wasmsimd-x32.c",
    "src/qu8-vaddc/gen/minmax-wasmsimd-x8.c",
    "src/qu8-vaddc/gen/minmax-wasmsimd-x16.c",
    "src/qu8-vaddc/gen/minmax-wasmsimd-x32.c",
    "src/qu8-vcvt/gen/vcvt-wasmsimd-x8.c",
    "src/qu8-vcvt/gen/vcvt-wasmsimd-x16.c",
    "src/qu8-vcvt/gen/vcvt-wasmsimd-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-wasmsimd-arm-x16.c",
    "src/qu8-vlrelu/gen/vlrelu-wasmsimd-arm-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-wasmsimd-x86-x8.c",
    "src/qu8-vlrelu/gen/vlrelu-wasmsimd-x86-x16.c",
    "src/qu8-vlrelu/gen/vlrelu-wasmsimd-x86-x32.c",
    "src/qu8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
    "src/qu8-vmul/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
    "src/qu8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x8.c",
    "src/qu8-vmulc/gen/minmax-fp32-wasmsimd-mul32-ld64-x16.c",
    "src/s8-ibilinear/gen/wasmsimd-dot16x2-c8.c",
    "src/s8-ibilinear/gen/wasmsimd-dot16x2-c16.c",
    "src/s8-ibilinear/gen/wasmsimd-mul32-c8.c",
    "src/s8-ibilinear/gen/wasmsimd-mul32-c16.c",
    "src/s8-maxpool/9p8x-minmax-wasmsimd-c16.c",
    "src/s8-vclamp/wasmsimd-x64.c",
    "src/u8-ibilinear/gen/wasmsimd-dot16x2-c8.c",
    "src/u8-ibilinear/gen/wasmsimd-dot16x2-c16.c",
    "src/u8-ibilinear/gen/wasmsimd-mul32-c8.c",
    "src/u8-ibilinear/gen/wasmsimd-mul32-c16.c",
    "src/u8-maxpool/9p8x-minmax-wasmsimd-c16.c",
    "src/u8-vclamp/wasmsimd-x64.c",
    "src/xx-fill/wasmsimd-x64.c",
    "src/xx-pad/wasmsimd.c",
    "src/x8-lut/gen/lut-wasmsimd-x16.c",
    "src/x8-lut/gen/lut-wasmsimd-x32.c",
    "src/x8-lut/gen/lut-wasmsimd-x48.c",
    "src/x8-lut/gen/lut-wasmsimd-x64.c",
    "src/x8-transposec/gen/16x16-reuse-mov-wasmsimd.c",
    "src/x8-transposec/gen/16x16-reuse-switch-wasmsimd.c",
    "src/x16-transposec/gen/8x8-multi-mov-wasmsimd.c",
    "src/x16-transposec/gen/8x8-multi-switch-wasmsimd.c",
    "src/x16-transposec/gen/8x8-reuse-mov-wasmsimd.c",
    "src/x16-transposec/gen/8x8-reuse-multi-wasmsimd.c",
    "src/x16-transposec/gen/8x8-reuse-switch-wasmsimd.c",
    "src/x32-packx/x4-wasmsimd.c",
    "src/x32-transposec/gen/4x4-multi-mov-wasmsimd.c",
    "src/x32-transposec/gen/4x4-multi-multi-wasmsimd.c",
    "src/x32-transposec/gen/4x4-multi-switch-wasmsimd.c",
    "src/x32-transposec/gen/4x4-reuse-mov-wasmsimd.c",
    "src/x32-transposec/gen/4x4-reuse-multi-wasmsimd.c",
    "src/x32-transposec/gen/4x4-reuse-switch-wasmsimd.c",
    "src/x32-unpool/wasmsimd.c",
    "src/x32-zip/xm-wasmsimd.c",
    "src/x32-zip/x2-wasmsimd.c",
    "src/x32-zip/x3-wasmsimd.c",
    "src/x32-zip/x4-wasmsimd.c",
]

ALL_WASMRELAXEDSIMD_MICROKERNEL_SRCS = [
    "src/f32-dwconv/gen/up4x3-minmax-wasmrelaxedsimd-acc2.c",
    "src/f32-dwconv/gen/up4x3-minmax-wasmrelaxedsimd-fma-acc2.c",
    "src/f32-dwconv/gen/up4x3-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up4x3-minmax-wasmrelaxedsimd.c",
    "src/f32-dwconv/gen/up4x3-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up4x4-minmax-wasmrelaxedsimd-acc2.c",
    "src/f32-dwconv/gen/up4x4-minmax-wasmrelaxedsimd-fma-acc2.c",
    "src/f32-dwconv/gen/up4x4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up4x4-minmax-wasmrelaxedsimd.c",
    "src/f32-dwconv/gen/up4x4-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up4x9-minmax-wasmrelaxedsimd-acc2.c",
    "src/f32-dwconv/gen/up4x9-minmax-wasmrelaxedsimd-fma-acc2.c",
    "src/f32-dwconv/gen/up4x9-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up4x9-minmax-wasmrelaxedsimd.c",
    "src/f32-dwconv/gen/up4x9-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up4x25-minmax-wasmrelaxedsimd-acc2.c",
    "src/f32-dwconv/gen/up4x25-minmax-wasmrelaxedsimd-fma-acc2.c",
    "src/f32-dwconv/gen/up4x25-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up4x25-minmax-wasmrelaxedsimd.c",
    "src/f32-dwconv/gen/up4x25-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up8x3-minmax-wasmrelaxedsimd-acc2.c",
    "src/f32-dwconv/gen/up8x3-minmax-wasmrelaxedsimd-fma-acc2.c",
    "src/f32-dwconv/gen/up8x3-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up8x3-minmax-wasmrelaxedsimd.c",
    "src/f32-dwconv/gen/up8x3-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up8x4-minmax-wasmrelaxedsimd-acc2.c",
    "src/f32-dwconv/gen/up8x4-minmax-wasmrelaxedsimd-fma-acc2.c",
    "src/f32-dwconv/gen/up8x4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up8x4-minmax-wasmrelaxedsimd.c",
    "src/f32-dwconv/gen/up8x4-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up8x9-minmax-wasmrelaxedsimd-acc2.c",
    "src/f32-dwconv/gen/up8x9-minmax-wasmrelaxedsimd-fma-acc2.c",
    "src/f32-dwconv/gen/up8x9-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up8x9-minmax-wasmrelaxedsimd.c",
    "src/f32-dwconv/gen/up8x9-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up8x25-minmax-wasmrelaxedsimd-acc2.c",
    "src/f32-dwconv/gen/up8x25-minmax-wasmrelaxedsimd-fma-acc2.c",
    "src/f32-dwconv/gen/up8x25-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-dwconv/gen/up8x25-minmax-wasmrelaxedsimd.c",
    "src/f32-dwconv/gen/up8x25-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-gemm/gen-inc/1x8s4inc-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen-inc/1x8s4inc-minmax-wasmrelaxedsimd.c",
    "src/f32-gemm/gen-inc/3x8inc-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen-inc/3x8inc-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen-inc/3x8inc-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-gemm/gen-inc/3x8inc-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-gemm/gen-inc/3x8s4inc-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen-inc/3x8s4inc-minmax-wasmrelaxedsimd.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-gemm/gen-inc/4x8s4inc-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen-inc/4x8s4inc-minmax-wasmrelaxedsimd.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-gemm/gen-inc/5x8s4inc-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen-inc/5x8s4inc-minmax-wasmrelaxedsimd.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-gemm/gen-inc/6x8s4inc-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen-inc/6x8s4inc-minmax-wasmrelaxedsimd.c",
    "src/f32-gemm/gen/1x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/1x8-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/1x8-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-gemm/gen/1x8-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-gemm/gen/1x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/1x8-relu-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/1x8-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/1x8-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/1x8s4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/1x8s4-minmax-wasmrelaxedsimd.c",
    "src/f32-gemm/gen/1x8s4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/1x8s4-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/3x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/3x8-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/3x8-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-gemm/gen/3x8-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-gemm/gen/3x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/3x8-relu-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/3x8-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/3x8-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/3x8s4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/3x8s4-minmax-wasmrelaxedsimd.c",
    "src/f32-gemm/gen/3x8s4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/3x8s4-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/4x2c4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/4x2c4-minmax-wasmrelaxedsimd.c",
    "src/f32-gemm/gen/4x2c4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/4x2c4-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/4x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/4x8-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/4x8-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-gemm/gen/4x8-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-gemm/gen/4x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/4x8-relu-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/4x8-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/4x8-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/4x8s4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/4x8s4-minmax-wasmrelaxedsimd.c",
    "src/f32-gemm/gen/4x8s4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/4x8s4-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/5x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/5x8-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/5x8-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-gemm/gen/5x8-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-gemm/gen/5x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/5x8-relu-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/5x8-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/5x8-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/5x8s4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/5x8s4-minmax-wasmrelaxedsimd.c",
    "src/f32-gemm/gen/5x8s4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/5x8s4-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/6x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/6x8-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/6x8-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-gemm/gen/6x8-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-gemm/gen/6x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/6x8-relu-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/6x8-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-gemm/gen/6x8-wasmrelaxedsimd-fma-splat.c",
    "src/f32-gemm/gen/6x8s4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/6x8s4-minmax-wasmrelaxedsimd.c",
    "src/f32-gemm/gen/6x8s4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-gemm/gen/6x8s4-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/1x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/1x8-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/1x8-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-igemm/gen/1x8-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-igemm/gen/1x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/1x8-relu-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/1x8-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/1x8-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/1x8s4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/1x8s4-minmax-wasmrelaxedsimd.c",
    "src/f32-igemm/gen/1x8s4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/1x8s4-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/3x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/3x8-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/3x8-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-igemm/gen/3x8-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-igemm/gen/3x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/3x8-relu-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/3x8-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/3x8-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/3x8s4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/3x8s4-minmax-wasmrelaxedsimd.c",
    "src/f32-igemm/gen/3x8s4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/3x8s4-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/4x2c4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/4x2c4-minmax-wasmrelaxedsimd.c",
    "src/f32-igemm/gen/4x2c4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/4x2c4-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/4x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/4x8-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/4x8-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-igemm/gen/4x8-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-igemm/gen/4x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/4x8-relu-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/4x8-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/4x8-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/4x8s4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/4x8s4-minmax-wasmrelaxedsimd.c",
    "src/f32-igemm/gen/4x8s4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/4x8s4-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/5x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/5x8-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/5x8-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-igemm/gen/5x8-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-igemm/gen/5x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/5x8-relu-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/5x8-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/5x8-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/5x8s4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/5x8s4-minmax-wasmrelaxedsimd.c",
    "src/f32-igemm/gen/5x8s4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/5x8s4-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/6x8-minmax-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/6x8-minmax-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/6x8-minmax-wasmrelaxedsimd-loadsplat.c",
    "src/f32-igemm/gen/6x8-minmax-wasmrelaxedsimd-splat.c",
    "src/f32-igemm/gen/6x8-relu-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/6x8-relu-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/6x8-wasmrelaxedsimd-fma-loadsplat.c",
    "src/f32-igemm/gen/6x8-wasmrelaxedsimd-fma-splat.c",
    "src/f32-igemm/gen/6x8s4-minmax-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/6x8s4-minmax-wasmrelaxedsimd.c",
    "src/f32-igemm/gen/6x8s4-relu-wasmrelaxedsimd-fma.c",
    "src/f32-igemm/gen/6x8s4-wasmrelaxedsimd-fma.c",
    "src/f32-vmulcaddc/gen/c4-minmax-wasmrelaxedsimd-fma-2x.c",
    "src/f32-vmulcaddc/gen/c4-minmax-wasmrelaxedsimd-2x.c",
    "src/f32-vmulcaddc/gen/c8-minmax-wasmrelaxedsimd-fma-2x.c",
    "src/f32-vmulcaddc/gen/c8-minmax-wasmrelaxedsimd-2x.c",
    "src/qs8-vcvt/gen/vcvt-wasmrelaxedsimd-x8.c",
    "src/qs8-vcvt/gen/vcvt-wasmrelaxedsimd-x16.c",
    "src/qs8-vcvt/gen/vcvt-wasmrelaxedsimd-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-wasmrelaxedsimd-arm-x16.c",
    "src/qs8-vlrelu/gen/vlrelu-wasmrelaxedsimd-arm-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-wasmrelaxedsimd-x86-x8.c",
    "src/qs8-vlrelu/gen/vlrelu-wasmrelaxedsimd-x86-x16.c",
    "src/qs8-vlrelu/gen/vlrelu-wasmrelaxedsimd-x86-x32.c",
    "src/qu8-vcvt/gen/vcvt-wasmrelaxedsimd-x8.c",
    "src/qu8-vcvt/gen/vcvt-wasmrelaxedsimd-x16.c",
    "src/qu8-vcvt/gen/vcvt-wasmrelaxedsimd-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-wasmrelaxedsimd-arm-x16.c",
    "src/qu8-vlrelu/gen/vlrelu-wasmrelaxedsimd-arm-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-wasmrelaxedsimd-x86-x8.c",
    "src/qu8-vlrelu/gen/vlrelu-wasmrelaxedsimd-x86-x16.c",
    "src/qu8-vlrelu/gen/vlrelu-wasmrelaxedsimd-x86-x32.c",
]

PROD_ARMSIMD32_MICROKERNEL_SRCS = [
    "src/qc8-gemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qc8-gemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qc8-igemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qc8-igemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qs8-gemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qs8-gemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qs8-igemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qs8-igemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qs8-vcvt/gen/vcvt-armsimd32-x8.c",
    "src/qs8-vlrelu/gen/vlrelu-armsimd32-x4.c",
    "src/qu8-gemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qu8-gemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qu8-igemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qu8-igemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qu8-vcvt/gen/vcvt-armsimd32-x8.c",
    "src/qu8-vlrelu/gen/vlrelu-armsimd32-x4.c",
]

ALL_ARMSIMD32_MICROKERNEL_SRCS = [
    "src/qc8-gemm/gen/1x1c4-minmax-fp32-armsimd32.c",
    "src/qc8-gemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qc8-gemm/gen/2x1c4-minmax-fp32-armsimd32.c",
    "src/qc8-gemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qc8-igemm/gen/1x1c4-minmax-fp32-armsimd32.c",
    "src/qc8-igemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qc8-igemm/gen/2x1c4-minmax-fp32-armsimd32.c",
    "src/qc8-igemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qs8-gemm/gen/1x1c4-minmax-fp32-armsimd32.c",
    "src/qs8-gemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qs8-gemm/gen/2x1c4-minmax-fp32-armsimd32.c",
    "src/qs8-gemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qs8-igemm/gen/1x1c4-minmax-fp32-armsimd32.c",
    "src/qs8-igemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qs8-igemm/gen/2x1c4-minmax-fp32-armsimd32.c",
    "src/qs8-igemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qs8-vcvt/gen/vcvt-armsimd32-x4.c",
    "src/qs8-vcvt/gen/vcvt-armsimd32-x8.c",
    "src/qs8-vlrelu/gen/vlrelu-armsimd32-x4.c",
    "src/qs8-vlrelu/gen/vlrelu-armsimd32-x8.c",
    "src/qu8-gemm/gen/1x1c4-minmax-fp32-armsimd32.c",
    "src/qu8-gemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qu8-gemm/gen/2x1c4-minmax-fp32-armsimd32.c",
    "src/qu8-gemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qu8-igemm/gen/1x1c4-minmax-fp32-armsimd32.c",
    "src/qu8-igemm/gen/1x2c4-minmax-fp32-armsimd32.c",
    "src/qu8-igemm/gen/2x1c4-minmax-fp32-armsimd32.c",
    "src/qu8-igemm/gen/2x2c4-minmax-fp32-armsimd32.c",
    "src/qu8-vcvt/gen/vcvt-armsimd32-x4.c",
    "src/qu8-vcvt/gen/vcvt-armsimd32-x8.c",
    "src/qu8-vlrelu/gen/vlrelu-armsimd32-x4.c",
    "src/qu8-vlrelu/gen/vlrelu-armsimd32-x8.c",
]

PROD_NEON_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-neon-int16-x16.c",
    "src/f32-argmaxpool/4x-neon-c4.c",
    "src/f32-argmaxpool/9p8x-neon-c4.c",
    "src/f32-argmaxpool/9x-neon-c4.c",
    "src/f32-avgpool/9p8x-minmax-neon-c4.c",
    "src/f32-avgpool/9x-minmax-neon-c4.c",
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-neon-2x2.c",
    "src/f32-dwconv/gen/up8x3-minmax-neon.c",
    "src/f32-dwconv/gen/up8x4-minmax-neon.c",
    "src/f32-dwconv/gen/up8x9-minmax-neon.c",
    "src/f32-dwconv/gen/up8x25-minmax-neon-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4.c",
    "src/f32-f16-vcvt/gen/vcvt-neon-x8.c",
    "src/f32-gavgpool-cw/neon-x4.c",
    "src/f32-gavgpool/7p7x-minmax-neon-c4.c",
    "src/f32-gavgpool/7x-minmax-neon-c4.c",
    "src/f32-gemm/gen/1x8-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen/4x2-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen/4x8-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen/4x8-minmax-neon-lane-ld128.c",
    "src/f32-ibilinear-chw/gen/neon-p8.c",
    "src/f32-ibilinear/gen/neon-c8.c",
    "src/f32-igemm/gen/1x8-minmax-neon-lane-ld64.c",
    "src/f32-igemm/gen/4x2-minmax-neon-lane-ld64.c",
    "src/f32-igemm/gen/4x8-minmax-neon-lane-ld64.c",
    "src/f32-igemm/gen/4x8-minmax-neon-lane-ld128.c",
    "src/f32-maxpool/9p8x-minmax-neon-c4.c",
    "src/f32-pavgpool/9p8x-minmax-neon-c4.c",
    "src/f32-pavgpool/9x-minmax-neon-c4.c",
    "src/f32-prelu/gen/neon-2x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-neon-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-neon-x32.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x8.c",
    "src/f32-rmax/neon.c",
    "src/f32-spmm/gen/32x1-minmax-neon.c",
    "src/f32-vbinary/gen/vadd-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vmax-neon-x8.c",
    "src/f32-vbinary/gen/vmaxc-neon-x8.c",
    "src/f32-vbinary/gen/vmin-neon-x8.c",
    "src/f32-vbinary/gen/vminc-neon-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vrsubc-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vsqrdiff-neon-x8.c",
    "src/f32-vbinary/gen/vsqrdiffc-neon-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-neon-x8.c",
    "src/f32-vclamp/gen/vclamp-neon-x8.c",
    "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x8.c",
    "src/f32-vhswish/gen/vhswish-neon-x16.c",
    "src/f32-vlrelu/gen/vlrelu-neon-x8.c",
    "src/f32-vmulcaddc/gen/c4-minmax-neon-2x.c",
    "src/f32-vrnd/gen/vrndd-neon-x8.c",
    "src/f32-vrnd/gen/vrndne-neon-x8.c",
    "src/f32-vrnd/gen/vrndu-neon-x8.c",
    "src/f32-vrnd/gen/vrndz-neon-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x8.c",
    "src/f32-vunary/gen/vabs-neon-x8.c",
    "src/f32-vunary/gen/vneg-neon-x8.c",
    "src/f32-vunary/gen/vsqr-neon-x8.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mla8-ld64.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-neon-mla8-ld128.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mla8-ld64.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mla8-ld64.c",
    "src/qc8-gemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-gemm/gen/1x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qc8-gemm/gen/2x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qc8-igemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-igemm/gen/1x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qc8-igemm/gen/2x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qs8-dwconv/gen/up8x25-minmax-rndnu-neon-mla8-ld64.c",
    "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mla8-ld64.c",
    "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mla8-ld64.c",
    "src/qs8-f32-vcvt/gen/vcvt-neon-x32.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-rndnu-neon-c8.c",
    "src/qs8-gavgpool/gen/7x-minmax-rndnu-neon-c8.c",
    "src/qs8-gemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-gemm/gen/1x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-gemm/gen/2x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/1x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/2x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-vadd/gen/minmax-neon-ld64-x16.c",
    "src/qs8-vadd/gen/minmax-neon-ld64-x32.c",
    "src/qs8-vaddc/gen/minmax-neon-ld64-x16.c",
    "src/qs8-vaddc/gen/minmax-neon-ld64-x32.c",
    "src/qs8-vcvt/gen/vcvt-neon-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-neon-x32.c",
    "src/qs8-vmul/gen/minmax-rndnu-neon-ld64-x16.c",
    "src/qs8-vmulc/gen/minmax-rndnu-neon-ld64-x16.c",
    "src/qu8-avgpool/9p8x-minmax-neon-c8.c",
    "src/qu8-avgpool/9x-minmax-neon-c8.c",
    "src/qu8-dwconv/gen/up8x25-minmax-rndnu-neon-mul8.c",
    "src/qu8-dwconv/gen/up16x9-minmax-rndnu-neon-mul8.c",
    "src/qu8-f32-vcvt/gen/vcvt-neon-x32.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-rndnu-neon-c8.c",
    "src/qu8-gavgpool/gen/7x-minmax-rndnu-neon-c8.c",
    "src/qu8-gemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/3x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/3x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-vadd/gen/minmax-neon-ld64-x16.c",
    "src/qu8-vadd/gen/minmax-neon-ld64-x32.c",
    "src/qu8-vaddc/gen/minmax-neon-ld64-x16.c",
    "src/qu8-vaddc/gen/minmax-neon-ld64-x32.c",
    "src/qu8-vcvt/gen/vcvt-neon-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-neon-x32.c",
    "src/qu8-vmul/gen/minmax-rndnu-neon-ld64-x16.c",
    "src/qu8-vmulc/gen/minmax-rndnu-neon-ld64-x16.c",
    "src/s8-ibilinear/gen/neon-c8.c",
    "src/s8-ibilinear/gen/neon-c16.c",
    "src/s8-maxpool/9p8x-minmax-neon-c16.c",
    "src/s8-vclamp/neon-x64.c",
    "src/u8-ibilinear/gen/neon-c8.c",
    "src/u8-ibilinear/gen/neon-c16.c",
    "src/u8-maxpool/9p8x-minmax-neon-c16.c",
    "src/u8-rmax/neon.c",
    "src/u8-vclamp/neon-x64.c",
    "src/xx-fill/neon-x64.c",
    "src/xx-pad/neon.c",
    "src/x8-transposec/gen/16x16-reuse-dec-zip-neon.c",
    "src/x8-zip/xm-neon.c",
    "src/x8-zip/x2-neon.c",
    "src/x8-zip/x3-neon.c",
    "src/x8-zip/x4-neon.c",
    "src/x16-transposec/gen/8x8-reuse-dec-zip-neon.c",
    "src/x32-packx/x4-neon-st4.c",
    "src/x32-transposec/gen/4x4-reuse-dec-zip-neon.c",
    "src/x32-unpool/neon.c",
    "src/x32-zip/xm-neon.c",
    "src/x32-zip/x2-neon.c",
    "src/x32-zip/x3-neon.c",
    "src/x32-zip/x4-neon.c",
]

ALL_NEON_MICROKERNEL_SRCS = [
    "src/cs16-bfly4/samples1-neon.c",
    "src/cs16-vsquareabs/gen/neon-mlal-ld128-x4.c",
    "src/cs16-vsquareabs/gen/neon-mlal-ld128-x8.c",
    "src/cs16-vsquareabs/gen/neon-mlal-ld128-x12.c",
    "src/cs16-vsquareabs/gen/neon-mlal-ld128-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-neon-int16-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-neon-int16-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-neon-int16-x24.c",
    "src/f16-f32-vcvt/gen/vcvt-neon-int16-x32.c",
    "src/f16-f32-vcvt/gen/vcvt-neon-int32-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-neon-int32-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-neon-int32-x24.c",
    "src/f16-f32-vcvt/gen/vcvt-neon-int32-x32.c",
    "src/f32-argmaxpool/4x-neon-c4.c",
    "src/f32-argmaxpool/9p8x-neon-c4.c",
    "src/f32-argmaxpool/9x-neon-c4.c",
    "src/f32-avgpool/9p8x-minmax-neon-c4.c",
    "src/f32-avgpool/9x-minmax-neon-c4.c",
    "src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neon-2x1.c",
    "src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neon-2x2.c",
    "src/f32-conv-hwc/gen/3x3s2p0p1c3x8-neon-2x1.c",
    "src/f32-conv-hwc/gen/3x3s2p0p1c3x8-neon-2x2.c",
    "src/f32-conv-hwc/gen/3x3s2p1c3x4-neon-2x1.c",
    "src/f32-conv-hwc/gen/3x3s2p1c3x4-neon-2x2.c",
    "src/f32-conv-hwc/gen/3x3s2p1c3x8-neon-2x1.c",
    "src/f32-conv-hwc/gen/3x3s2p1c3x8-neon-2x2.c",
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-neon-2x2.c",
    "src/f32-dwconv/gen/up4x3-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up4x3-minmax-neon.c",
    "src/f32-dwconv/gen/up4x4-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up4x4-minmax-neon.c",
    "src/f32-dwconv/gen/up4x9-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up4x9-minmax-neon.c",
    "src/f32-dwconv/gen/up4x25-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up4x25-minmax-neon.c",
    "src/f32-dwconv/gen/up8x3-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up8x3-minmax-neon.c",
    "src/f32-dwconv/gen/up8x4-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up8x4-minmax-neon.c",
    "src/f32-dwconv/gen/up8x9-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up8x9-minmax-neon.c",
    "src/f32-dwconv/gen/up8x25-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up8x25-minmax-neon.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-4x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-5x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-6x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neon-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-3x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-4x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neon-5x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neon-3x4.c",
    "src/f32-f16-vcvt/gen/vcvt-neon-x8.c",
    "src/f32-f16-vcvt/gen/vcvt-neon-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-neon-x24.c",
    "src/f32-f16-vcvt/gen/vcvt-neon-x32.c",
    "src/f32-gavgpool-cw/neon-x4.c",
    "src/f32-gavgpool/7p7x-minmax-neon-c4.c",
    "src/f32-gavgpool/7x-minmax-neon-c4.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-neon-dup-ld64.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen-inc/1x8s4inc-minmax-neon.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-neon-dup-ld64.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-neon-dup-ld128.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-neon-lane-ld128.c",
    "src/f32-gemm/gen-inc/4x8s4inc-minmax-neon.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-neon-dup-ld64.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-neon-dup-ld128.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-neon-lane-ld128.c",
    "src/f32-gemm/gen-inc/6x8s4inc-minmax-neon.c",
    "src/f32-gemm/gen-inc/8x8s4inc-minmax-neon.c",
    "src/f32-gemm/gen/1x8-minmax-neon-dup-ld64.c",
    "src/f32-gemm/gen/1x8-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen/1x8s4-minmax-neon.c",
    "src/f32-gemm/gen/4x2-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen/4x8-minmax-neon-dup-ld64.c",
    "src/f32-gemm/gen/4x8-minmax-neon-dup-ld128.c",
    "src/f32-gemm/gen/4x8-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen/4x8-minmax-neon-lane-ld128.c",
    "src/f32-gemm/gen/4x8s4-minmax-neon.c",
    "src/f32-gemm/gen/5x8-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen/6x2-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen/6x8-minmax-neon-dup-ld64.c",
    "src/f32-gemm/gen/6x8-minmax-neon-dup-ld128.c",
    "src/f32-gemm/gen/6x8-minmax-neon-lane-ld64.c",
    "src/f32-gemm/gen/6x8-minmax-neon-lane-ld128.c",
    "src/f32-gemm/gen/6x8s4-minmax-neon.c",
    "src/f32-gemm/gen/8x8s4-minmax-neon.c",
    "src/f32-ibilinear-chw/gen/neon-p4.c",
    "src/f32-ibilinear-chw/gen/neon-p8.c",
    "src/f32-ibilinear-chw/gen/neon-p16.c",
    "src/f32-ibilinear/gen/neon-c4.c",
    "src/f32-ibilinear/gen/neon-c8.c",
    "src/f32-igemm/gen/1x8-minmax-neon-dup-ld64.c",
    "src/f32-igemm/gen/1x8-minmax-neon-lane-ld64.c",
    "src/f32-igemm/gen/1x8s4-minmax-neon.c",
    "src/f32-igemm/gen/4x2-minmax-neon-lane-ld64.c",
    "src/f32-igemm/gen/4x4-minmax-neon-lane-ld64.c",
    "src/f32-igemm/gen/4x8-minmax-neon-dup-ld64.c",
    "src/f32-igemm/gen/4x8-minmax-neon-dup-ld128.c",
    "src/f32-igemm/gen/4x8-minmax-neon-lane-ld64.c",
    "src/f32-igemm/gen/4x8-minmax-neon-lane-ld128.c",
    "src/f32-igemm/gen/4x8s4-minmax-neon.c",
    "src/f32-igemm/gen/6x2-minmax-neon-lane-ld64.c",
    "src/f32-igemm/gen/6x8-minmax-neon-dup-ld64.c",
    "src/f32-igemm/gen/6x8-minmax-neon-dup-ld128.c",
    "src/f32-igemm/gen/6x8-minmax-neon-lane-ld64.c",
    "src/f32-igemm/gen/6x8-minmax-neon-lane-ld128.c",
    "src/f32-igemm/gen/6x8s4-minmax-neon.c",
    "src/f32-igemm/gen/8x8s4-minmax-neon.c",
    "src/f32-maxpool/9p8x-minmax-neon-c4.c",
    "src/f32-pavgpool/9p8x-minmax-neon-c4.c",
    "src/f32-pavgpool/9x-minmax-neon-c4.c",
    "src/f32-ppmm/gen/4x8-minmax-neon.c",
    "src/f32-ppmm/gen/8x8-minmax-neon.c",
    "src/f32-prelu/gen/neon-1x4.c",
    "src/f32-prelu/gen/neon-1x8.c",
    "src/f32-prelu/gen/neon-1x16.c",
    "src/f32-prelu/gen/neon-2x4.c",
    "src/f32-prelu/gen/neon-2x8.c",
    "src/f32-prelu/gen/neon-2x16.c",
    "src/f32-prelu/gen/neon-4x4.c",
    "src/f32-prelu/gen/neon-4x8.c",
    "src/f32-prelu/gen/neon-4x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-neon-x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-neon-x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-neon-x24.c",
    "src/f32-qs8-vcvt/gen/vcvt-neon-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-neon-x8.c",
    "src/f32-qu8-vcvt/gen/vcvt-neon-x16.c",
    "src/f32-qu8-vcvt/gen/vcvt-neon-x24.c",
    "src/f32-qu8-vcvt/gen/vcvt-neon-x32.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x4.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x8-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x8.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x12-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x12-acc3.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x12.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x16-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x16-acc4.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x16.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x20-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x20-acc5.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-lut64-p2-x20.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x4.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x8-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x8.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x12-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x12-acc3.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x12.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x16-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x16-acc4.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x16.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x20-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x20-acc5.c",
    "src/f32-raddstoreexpminusmax/gen/neon-rr2-p5-x20.c",
    "src/f32-rmax/neon.c",
    "src/f32-spmm/gen/4x1-minmax-neon-pipelined.c",
    "src/f32-spmm/gen/4x1-minmax-neon-x2.c",
    "src/f32-spmm/gen/4x1-minmax-neon.c",
    "src/f32-spmm/gen/8x1-minmax-neon-pipelined.c",
    "src/f32-spmm/gen/8x1-minmax-neon-x2.c",
    "src/f32-spmm/gen/8x1-minmax-neon.c",
    "src/f32-spmm/gen/12x1-minmax-neon.c",
    "src/f32-spmm/gen/16x1-minmax-neon-pipelined.c",
    "src/f32-spmm/gen/16x1-minmax-neon-x2.c",
    "src/f32-spmm/gen/16x1-minmax-neon.c",
    "src/f32-spmm/gen/32x1-minmax-neon-pipelined.c",
    "src/f32-spmm/gen/32x1-minmax-neon-x2.c",
    "src/f32-spmm/gen/32x1-minmax-neon.c",
    "src/f32-vbinary/gen/vadd-minmax-neon-x4.c",
    "src/f32-vbinary/gen/vadd-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-neon-x4.c",
    "src/f32-vbinary/gen/vaddc-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vmax-neon-x4.c",
    "src/f32-vbinary/gen/vmax-neon-x8.c",
    "src/f32-vbinary/gen/vmaxc-neon-x4.c",
    "src/f32-vbinary/gen/vmaxc-neon-x8.c",
    "src/f32-vbinary/gen/vmin-neon-x4.c",
    "src/f32-vbinary/gen/vmin-neon-x8.c",
    "src/f32-vbinary/gen/vminc-neon-x4.c",
    "src/f32-vbinary/gen/vminc-neon-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-neon-x4.c",
    "src/f32-vbinary/gen/vmul-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-neon-x4.c",
    "src/f32-vbinary/gen/vmulc-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vrsubc-minmax-neon-x4.c",
    "src/f32-vbinary/gen/vrsubc-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vsqrdiff-neon-x4.c",
    "src/f32-vbinary/gen/vsqrdiff-neon-x8.c",
    "src/f32-vbinary/gen/vsqrdiffc-neon-x4.c",
    "src/f32-vbinary/gen/vsqrdiffc-neon-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-neon-x4.c",
    "src/f32-vbinary/gen/vsub-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-neon-x4.c",
    "src/f32-vbinary/gen/vsubc-minmax-neon-x8.c",
    "src/f32-vclamp/gen/vclamp-neon-x4.c",
    "src/f32-vclamp/gen/vclamp-neon-x8.c",
    "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x4.c",
    "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x8.c",
    "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x12.c",
    "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x16.c",
    "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x20.c",
    "src/f32-velu/gen/velu-neon-rr2-lut16-p3-x24.c",
    "src/f32-velu/gen/velu-neon-rr2-p6-x4.c",
    "src/f32-velu/gen/velu-neon-rr2-p6-x8.c",
    "src/f32-velu/gen/velu-neon-rr2-p6-x12.c",
    "src/f32-velu/gen/velu-neon-rr2-p6-x16.c",
    "src/f32-velu/gen/velu-neon-rr2-p6-x20.c",
    "src/f32-velu/gen/velu-neon-rr2-p6-x24.c",
    "src/f32-vhswish/gen/vhswish-neon-x4.c",
    "src/f32-vhswish/gen/vhswish-neon-x8.c",
    "src/f32-vhswish/gen/vhswish-neon-x16.c",
    "src/f32-vlrelu/gen/vlrelu-neon-x4.c",
    "src/f32-vlrelu/gen/vlrelu-neon-x8.c",
    "src/f32-vmulcaddc/gen/c4-minmax-neon-2x.c",
    "src/f32-vmulcaddc/gen/c8-minmax-neon-2x.c",
    "src/f32-vrelu/gen/vrelu-neon-x4.c",
    "src/f32-vrelu/gen/vrelu-neon-x8.c",
    "src/f32-vrnd/gen/vrndd-neon-x4.c",
    "src/f32-vrnd/gen/vrndd-neon-x8.c",
    "src/f32-vrnd/gen/vrndne-neon-x4.c",
    "src/f32-vrnd/gen/vrndne-neon-x8.c",
    "src/f32-vrnd/gen/vrndu-neon-x4.c",
    "src/f32-vrnd/gen/vrndu-neon-x8.c",
    "src/f32-vrnd/gen/vrndz-neon-x4.c",
    "src/f32-vrnd/gen/vrndz-neon-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut64-p2-nr2recps-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-lut2048-p1-nr2recps-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neon-rr2-p5-nr2recps-x24.c",
    "src/f32-vunary/gen/vabs-neon-x4.c",
    "src/f32-vunary/gen/vabs-neon-x8.c",
    "src/f32-vunary/gen/vneg-neon-x4.c",
    "src/f32-vunary/gen/vneg-neon-x8.c",
    "src/f32-vunary/gen/vsqr-neon-x4.c",
    "src/f32-vunary/gen/vsqr-neon-x8.c",
    "src/math/cvt-f16-f32-neon-int16.c",
    "src/math/cvt-f16-f32-neon-int32.c",
    "src/math/cvt-f32-f16-neon.c",
    "src/math/cvt-f32-qs8-neon.c",
    "src/math/cvt-f32-qu8-neon.c",
    "src/math/expm1minus-f32-neon-rr2-lut16-p3.c",
    "src/math/expm1minus-f32-neon-rr2-p6.c",
    "src/math/roundd-neon-addsub.c",
    "src/math/roundd-neon-cvt.c",
    "src/math/roundne-neon-addsub.c",
    "src/math/roundu-neon-addsub.c",
    "src/math/roundu-neon-cvt.c",
    "src/math/roundz-neon-addsub.c",
    "src/math/roundz-neon-cvt.c",
    "src/math/sigmoid-f32-neon-rr2-lut64-p2-nr2recps.c",
    "src/math/sigmoid-f32-neon-rr2-lut2048-p1-nr2recps.c",
    "src/math/sigmoid-f32-neon-rr2-p5-nr2recps.c",
    "src/math/sqrt-neon-nr1rsqrts.c",
    "src/math/sqrt-neon-nr2rsqrts.c",
    "src/math/sqrt-neon-nr3rsqrts.c",
    "src/qc8-dwconv/gen/up8x3-minmax-fp32-neon-mla8-ld64.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-neon-mla8-ld64.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-neon-mul8-ld64.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-neon-mul16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mla8-ld64.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mul8-ld64.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-neon-mul16.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-neon-mla8-ld64.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-neon-mla8-ld128.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mla8-ld64.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mla8-ld128.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mul8-ld64.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mul8-ld128.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neon-mul16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mla8-ld64.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mla8-ld128.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mul8-ld64.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mul8-ld128.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neon-mul16.c",
    "src/qc8-dwconv/gen/up24x9-minmax-fp32-neon-mul16.c",
    "src/qc8-dwconv/gen/up24x25-minmax-fp32-neon-mul16.c",
    "src/qc8-dwconv/gen/up32x9-minmax-fp32-neon-mul16.c",
    "src/qc8-dwconv/gen/up32x25-minmax-fp32-neon-mul16.c",
    "src/qc8-gemm/gen/1x8-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-dup.c",
    "src/qc8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-ld1r.c",
    "src/qc8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-ld2r.c",
    "src/qc8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-ld4r.c",
    "src/qc8-gemm/gen/1x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qc8-gemm/gen/1x8c4-minmax-fp32-neon-mlal-dup.c",
    "src/qc8-gemm/gen/1x8c4-minmax-fp32-neon-mlal-ld1r.c",
    "src/qc8-gemm/gen/1x8c4-minmax-fp32-neon-mlal-ld2r.c",
    "src/qc8-gemm/gen/1x8c4s2-minmax-fp32-neon-mlal.c",
    "src/qc8-gemm/gen/1x8c8-minmax-fp32-neon-mlal.c",
    "src/qc8-gemm/gen/1x16-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-gemm/gen/2x8-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/2x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-dup.c",
    "src/qc8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-ld1r.c",
    "src/qc8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-ld2r.c",
    "src/qc8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-ld4r.c",
    "src/qc8-gemm/gen/2x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qc8-gemm/gen/2x8c4-minmax-fp32-neon-mlal-dup.c",
    "src/qc8-gemm/gen/2x8c4-minmax-fp32-neon-mlal-ld1r.c",
    "src/qc8-gemm/gen/2x8c4-minmax-fp32-neon-mlal-ld2r.c",
    "src/qc8-gemm/gen/2x8c4s2-minmax-fp32-neon-mlal.c",
    "src/qc8-gemm/gen/2x8c8-minmax-fp32-neon-mlal.c",
    "src/qc8-gemm/gen/2x16-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/2x16-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-gemm/gen/3x8-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/3x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-gemm/gen/3x16-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/3x16-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-gemm/gen/4x8-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/4x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-gemm/gen/4x16-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-gemm/gen/6x8-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/6x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-gemm/gen/6x16-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/6x16-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-igemm/gen/1x8-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-dup.c",
    "src/qc8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-ld1r.c",
    "src/qc8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-ld2r.c",
    "src/qc8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-ld4r.c",
    "src/qc8-igemm/gen/1x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qc8-igemm/gen/1x8c4-minmax-fp32-neon-mlal-dup.c",
    "src/qc8-igemm/gen/1x8c4-minmax-fp32-neon-mlal-ld1r.c",
    "src/qc8-igemm/gen/1x8c4-minmax-fp32-neon-mlal-ld2r.c",
    "src/qc8-igemm/gen/1x8c4s2-minmax-fp32-neon-mlal.c",
    "src/qc8-igemm/gen/1x8c8-minmax-fp32-neon-mlal.c",
    "src/qc8-igemm/gen/1x16-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-igemm/gen/2x8-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/2x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-dup.c",
    "src/qc8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-ld1r.c",
    "src/qc8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-ld2r.c",
    "src/qc8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-ld4r.c",
    "src/qc8-igemm/gen/2x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qc8-igemm/gen/2x8c4-minmax-fp32-neon-mlal-dup.c",
    "src/qc8-igemm/gen/2x8c4-minmax-fp32-neon-mlal-ld1r.c",
    "src/qc8-igemm/gen/2x8c4-minmax-fp32-neon-mlal-ld2r.c",
    "src/qc8-igemm/gen/2x8c4s2-minmax-fp32-neon-mlal.c",
    "src/qc8-igemm/gen/2x8c8-minmax-fp32-neon-mlal.c",
    "src/qc8-igemm/gen/2x16-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/2x16-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-igemm/gen/3x8-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/3x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-igemm/gen/3x16-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/3x16-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-igemm/gen/4x8-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/4x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-igemm/gen/4x16-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-igemm/gen/6x8-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/6x8-minmax-fp32-neon-mlal-lane.c",
    "src/qc8-igemm/gen/6x16-minmax-fp32-neon-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/6x16-minmax-fp32-neon-mlal-lane.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-neon-mul16.c",
    "src/qs8-dwconv/gen/up8x9-minmax-rndnu-neon-mla8-ld64.c",
    "src/qs8-dwconv/gen/up8x9-minmax-rndnu-neon-mul8-ld64.c",
    "src/qs8-dwconv/gen/up8x9-minmax-rndnu-neon-mul16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-neon-mul16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-rndnu-neon-mla8-ld64.c",
    "src/qs8-dwconv/gen/up8x25-minmax-rndnu-neon-mul8-ld64.c",
    "src/qs8-dwconv/gen/up8x25-minmax-rndnu-neon-mul16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-neon-mul16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mla8-ld64.c",
    "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mla8-ld128.c",
    "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mul8-ld64.c",
    "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mul8-ld128.c",
    "src/qs8-dwconv/gen/up16x9-minmax-rndnu-neon-mul16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-neon-mul16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mla8-ld64.c",
    "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mla8-ld128.c",
    "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mul8-ld64.c",
    "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mul8-ld128.c",
    "src/qs8-dwconv/gen/up16x25-minmax-rndnu-neon-mul16.c",
    "src/qs8-dwconv/gen/up24x9-minmax-fp32-neon-mul16.c",
    "src/qs8-dwconv/gen/up24x9-minmax-rndnu-neon-mul16.c",
    "src/qs8-dwconv/gen/up24x25-minmax-fp32-neon-mul16.c",
    "src/qs8-dwconv/gen/up24x25-minmax-rndnu-neon-mul16.c",
    "src/qs8-dwconv/gen/up32x9-minmax-fp32-neon-mul16.c",
    "src/qs8-dwconv/gen/up32x9-minmax-rndnu-neon-mul16.c",
    "src/qs8-dwconv/gen/up32x25-minmax-fp32-neon-mul16.c",
    "src/qs8-dwconv/gen/up32x25-minmax-rndnu-neon-mul16.c",
    "src/qs8-f32-vcvt/gen/vcvt-neon-x8.c",
    "src/qs8-f32-vcvt/gen/vcvt-neon-x16.c",
    "src/qs8-f32-vcvt/gen/vcvt-neon-x24.c",
    "src/qs8-f32-vcvt/gen/vcvt-neon-x32.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neon-c8.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neon-c16.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neon-c24.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neon-c32.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-rndnu-neon-c8.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-rndnu-neon-c16.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-rndnu-neon-c24.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-rndnu-neon-c32.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-neon-c8.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-neon-c16.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-neon-c24.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-neon-c32.c",
    "src/qs8-gavgpool/gen/7x-minmax-rndnu-neon-c8.c",
    "src/qs8-gavgpool/gen/7x-minmax-rndnu-neon-c16.c",
    "src/qs8-gavgpool/gen/7x-minmax-rndnu-neon-c24.c",
    "src/qs8-gavgpool/gen/7x-minmax-rndnu-neon-c32.c",
    "src/qs8-gemm/gen/1x8-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-gemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-gemm/gen/1x8-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-dup.c",
    "src/qs8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/1x8c2-minmax-fp32-neon-mlal-ld4r.c",
    "src/qs8-gemm/gen/1x8c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/1x8c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/1x8c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/1x8c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-gemm/gen/1x8c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/1x8c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/1x8c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/1x8c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-gemm/gen/1x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qs8-gemm/gen/1x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/1x8c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/1x8c4-minmax-fp32-neon-mlal-dup.c",
    "src/qs8-gemm/gen/1x8c4-minmax-fp32-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/1x8c4-minmax-fp32-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/1x8c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/1x8c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/1x8c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/1x8c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/1x8c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/1x8c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/1x8c4s2-minmax-fp32-neon-mlal.c",
    "src/qs8-gemm/gen/1x8c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/1x8c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/1x8c8-minmax-fp32-neon-mlal.c",
    "src/qs8-gemm/gen/1x8c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/1x8c8-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/1x8c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
    "src/qs8-gemm/gen/1x16-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-gemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-gemm/gen/1x16-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-gemm/gen/1x16c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/1x16c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/1x16c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/1x16c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-gemm/gen/1x16c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/1x16c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/1x16c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/1x16c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-gemm/gen/1x16c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/1x16c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/1x16c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/1x16c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/1x16c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/1x16c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/1x16c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/1x16c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/1x16c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/1x16c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/1x16c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/1x16c8-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/1x16c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/2x8-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-gemm/gen/2x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-gemm/gen/2x8-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-dup.c",
    "src/qs8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/2x8c2-minmax-fp32-neon-mlal-ld4r.c",
    "src/qs8-gemm/gen/2x8c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/2x8c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/2x8c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/2x8c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-gemm/gen/2x8c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/2x8c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/2x8c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/2x8c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-gemm/gen/2x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qs8-gemm/gen/2x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/2x8c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/2x8c4-minmax-fp32-neon-mlal-dup.c",
    "src/qs8-gemm/gen/2x8c4-minmax-fp32-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/2x8c4-minmax-fp32-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/2x8c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/2x8c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/2x8c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/2x8c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/2x8c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/2x8c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/2x8c4s2-minmax-fp32-neon-mlal.c",
    "src/qs8-gemm/gen/2x8c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/2x8c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/2x8c8-minmax-fp32-neon-mlal.c",
    "src/qs8-gemm/gen/2x8c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/2x8c8-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/2x8c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/2x16-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-gemm/gen/2x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-gemm/gen/2x16-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-gemm/gen/2x16c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/2x16c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/2x16c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/2x16c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-gemm/gen/2x16c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/2x16c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/2x16c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/2x16c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-gemm/gen/2x16c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/2x16c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/2x16c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/2x16c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/2x16c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/2x16c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/2x16c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/2x16c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/2x16c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/2x16c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/2x16c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/2x16c8-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/2x16c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/3x8-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-gemm/gen/3x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-gemm/gen/3x8-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-gemm/gen/3x8c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/3x8c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/3x8c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/3x8c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-gemm/gen/3x8c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/3x8c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/3x8c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/3x8c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-gemm/gen/3x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/3x8c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/3x8c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/3x8c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/3x8c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/3x8c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/3x8c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/3x8c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/3x8c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/3x8c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/3x8c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/3x8c8-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/3x8c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/3x16-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-gemm/gen/3x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-gemm/gen/3x16-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-gemm/gen/3x16c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/3x16c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/3x16c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/3x16c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-gemm/gen/3x16c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/3x16c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/3x16c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/3x16c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-gemm/gen/3x16c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/3x16c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/3x16c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/3x16c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/3x16c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/3x16c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/3x16c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/3x16c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/3x16c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/3x16c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/3x16c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/3x16c8-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/3x16c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/4x8-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-gemm/gen/4x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-gemm/gen/4x8-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-gemm/gen/4x8c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/4x8c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/4x8c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/4x8c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-gemm/gen/4x8c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/4x8c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/4x8c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/4x8c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-gemm/gen/4x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/4x8c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/4x8c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/4x8c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/4x8c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/4x8c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/4x8c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/4x8c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/4x8c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/4x8c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/4x8c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/4x8c8-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/4x8c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
    "src/qs8-gemm/gen/4x16-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-gemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-gemm/gen/4x16-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-gemm/gen/4x16c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/4x16c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/4x16c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/4x16c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-gemm/gen/4x16c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/4x16c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/4x16c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/4x16c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-gemm/gen/4x16c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/4x16c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-gemm/gen/4x16c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/4x16c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/4x16c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/4x16c8-minmax-rndnu-neon-mull.c",
    "src/qs8-gemm/gen/4x16c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-gemm/gen/6x8-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-gemm/gen/6x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-gemm/gen/6x16-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-gemm/gen/6x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/1x8-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-igemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/1x8-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-dup.c",
    "src/qs8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/1x8c2-minmax-fp32-neon-mlal-ld4r.c",
    "src/qs8-igemm/gen/1x8c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/1x8c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/1x8c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/1x8c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-igemm/gen/1x8c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/1x8c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/1x8c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/1x8c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-igemm/gen/1x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qs8-igemm/gen/1x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/1x8c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/1x8c4-minmax-fp32-neon-mlal-dup.c",
    "src/qs8-igemm/gen/1x8c4-minmax-fp32-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/1x8c4-minmax-fp32-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/1x8c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/1x8c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/1x8c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/1x8c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/1x8c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/1x8c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/1x8c4s2-minmax-fp32-neon-mlal.c",
    "src/qs8-igemm/gen/1x8c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/1x8c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/1x8c8-minmax-fp32-neon-mlal.c",
    "src/qs8-igemm/gen/1x8c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/1x8c8-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/1x8c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
    "src/qs8-igemm/gen/1x16-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-igemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/1x16-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-igemm/gen/1x16c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/1x16c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/1x16c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/1x16c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-igemm/gen/1x16c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/1x16c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/1x16c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/1x16c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-igemm/gen/1x16c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/1x16c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/1x16c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/1x16c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/1x16c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/1x16c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/1x16c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/1x16c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/1x16c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/1x16c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/1x16c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/1x16c8-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/1x16c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/2x8-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-igemm/gen/2x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/2x8-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-dup.c",
    "src/qs8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/2x8c2-minmax-fp32-neon-mlal-ld4r.c",
    "src/qs8-igemm/gen/2x8c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/2x8c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/2x8c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/2x8c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-igemm/gen/2x8c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/2x8c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/2x8c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/2x8c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-igemm/gen/2x8c2s4-minmax-fp32-neon-mlal.c",
    "src/qs8-igemm/gen/2x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/2x8c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/2x8c4-minmax-fp32-neon-mlal-dup.c",
    "src/qs8-igemm/gen/2x8c4-minmax-fp32-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/2x8c4-minmax-fp32-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/2x8c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/2x8c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/2x8c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/2x8c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/2x8c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/2x8c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/2x8c4s2-minmax-fp32-neon-mlal.c",
    "src/qs8-igemm/gen/2x8c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/2x8c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/2x8c8-minmax-fp32-neon-mlal.c",
    "src/qs8-igemm/gen/2x8c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/2x8c8-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/2x8c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/2x16-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-igemm/gen/2x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/2x16-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-igemm/gen/2x16c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/2x16c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/2x16c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/2x16c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-igemm/gen/2x16c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/2x16c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/2x16c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/2x16c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-igemm/gen/2x16c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/2x16c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/2x16c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/2x16c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/2x16c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/2x16c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/2x16c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/2x16c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/2x16c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/2x16c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/2x16c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/2x16c8-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/2x16c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/3x8-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-igemm/gen/3x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/3x8-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-igemm/gen/3x8c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/3x8c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/3x8c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/3x8c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-igemm/gen/3x8c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/3x8c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/3x8c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/3x8c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-igemm/gen/3x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/3x8c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/3x8c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/3x8c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/3x8c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/3x8c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/3x8c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/3x8c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/3x8c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/3x8c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/3x8c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/3x8c8-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/3x8c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/3x16-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-igemm/gen/3x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/3x16-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-igemm/gen/3x16c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/3x16c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/3x16c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/3x16c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-igemm/gen/3x16c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/3x16c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/3x16c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/3x16c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-igemm/gen/3x16c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/3x16c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/3x16c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/3x16c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/3x16c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/3x16c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/3x16c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/3x16c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/3x16c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/3x16c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/3x16c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/3x16c8-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/3x16c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/4x8-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-igemm/gen/4x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/4x8-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/4x8c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-igemm/gen/4x8c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/4x8c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/4x8c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/4x8c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/4x8c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/4x8c8-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/4x8c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
    "src/qs8-igemm/gen/4x16-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-igemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/4x16-minmax-rndnu-neon-mull-addw-dup.c",
    "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mlal-ld4r.c",
    "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/4x16c2-minmax-rndnu-neon-mull-ld4r.c",
    "src/qs8-igemm/gen/4x16c2s4-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/4x16c2s4-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mlal-dup.c",
    "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mlal-ld1r.c",
    "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mlal-ld2r.c",
    "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mull-dup.c",
    "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mull-ld1r.c",
    "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neon-mull-ld2r.c",
    "src/qs8-igemm/gen/4x16c4s2-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/4x16c4s2-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/4x16c8-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/4x16c8-minmax-rndnu-neon-mull.c",
    "src/qs8-igemm/gen/4x16c16-minmax-rndnu-neon-mlal.c",
    "src/qs8-igemm/gen/6x8-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-igemm/gen/6x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-igemm/gen/6x16-minmax-rndnu-neon-mlal-lane-prfm.c",
    "src/qs8-igemm/gen/6x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qs8-requantization/fp32-neon.c",
    "src/qs8-requantization/gemmlowp-neon.c",
    "src/qs8-requantization/rndna-neon.c",
    "src/qs8-requantization/rndnu-neon-mull.c",
    "src/qs8-requantization/rndnu-neon-qdmulh.c",
    "src/qs8-vadd/gen/minmax-neon-ld64-x8.c",
    "src/qs8-vadd/gen/minmax-neon-ld64-x16.c",
    "src/qs8-vadd/gen/minmax-neon-ld64-x24.c",
    "src/qs8-vadd/gen/minmax-neon-ld64-x32.c",
    "src/qs8-vadd/gen/minmax-neon-ld128-x16.c",
    "src/qs8-vadd/gen/minmax-neon-ld128-x32.c",
    "src/qs8-vaddc/gen/minmax-neon-ld64-x8.c",
    "src/qs8-vaddc/gen/minmax-neon-ld64-x16.c",
    "src/qs8-vaddc/gen/minmax-neon-ld64-x24.c",
    "src/qs8-vaddc/gen/minmax-neon-ld64-x32.c",
    "src/qs8-vaddc/gen/minmax-neon-ld128-x16.c",
    "src/qs8-vaddc/gen/minmax-neon-ld128-x32.c",
    "src/qs8-vcvt/gen/vcvt-neon-x8.c",
    "src/qs8-vcvt/gen/vcvt-neon-x16.c",
    "src/qs8-vcvt/gen/vcvt-neon-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-neon-x8.c",
    "src/qs8-vlrelu/gen/vlrelu-neon-x16.c",
    "src/qs8-vlrelu/gen/vlrelu-neon-x32.c",
    "src/qs8-vmul/gen/minmax-fp32-neon-ld64-x8.c",
    "src/qs8-vmul/gen/minmax-fp32-neon-ld64-x16.c",
    "src/qs8-vmul/gen/minmax-fp32-neon-ld128-x16.c",
    "src/qs8-vmul/gen/minmax-rndnu-neon-ld64-x8.c",
    "src/qs8-vmul/gen/minmax-rndnu-neon-ld64-x16.c",
    "src/qs8-vmul/gen/minmax-rndnu-neon-ld128-x16.c",
    "src/qs8-vmulc/gen/minmax-fp32-neon-ld64-x8.c",
    "src/qs8-vmulc/gen/minmax-fp32-neon-ld64-x16.c",
    "src/qs8-vmulc/gen/minmax-fp32-neon-ld128-x16.c",
    "src/qs8-vmulc/gen/minmax-rndnu-neon-ld64-x8.c",
    "src/qs8-vmulc/gen/minmax-rndnu-neon-ld64-x16.c",
    "src/qs8-vmulc/gen/minmax-rndnu-neon-ld128-x16.c",
    "src/qu8-avgpool/9p8x-minmax-neon-c8.c",
    "src/qu8-avgpool/9x-minmax-neon-c8.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-neon-mul16.c",
    "src/qu8-dwconv/gen/up8x9-minmax-rndnu-neon-mul8.c",
    "src/qu8-dwconv/gen/up8x9-minmax-rndnu-neon-mul16.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-neon-mul16.c",
    "src/qu8-dwconv/gen/up8x25-minmax-rndnu-neon-mul8.c",
    "src/qu8-dwconv/gen/up8x25-minmax-rndnu-neon-mul16.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-neon-mul16.c",
    "src/qu8-dwconv/gen/up16x9-minmax-rndnu-neon-mul8.c",
    "src/qu8-dwconv/gen/up16x9-minmax-rndnu-neon-mul16.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-neon-mul16.c",
    "src/qu8-dwconv/gen/up16x25-minmax-rndnu-neon-mul8.c",
    "src/qu8-dwconv/gen/up16x25-minmax-rndnu-neon-mul16.c",
    "src/qu8-dwconv/gen/up24x9-minmax-fp32-neon-mul16.c",
    "src/qu8-dwconv/gen/up24x9-minmax-rndnu-neon-mul8.c",
    "src/qu8-dwconv/gen/up24x9-minmax-rndnu-neon-mul16.c",
    "src/qu8-dwconv/gen/up24x25-minmax-fp32-neon-mul16.c",
    "src/qu8-dwconv/gen/up24x25-minmax-rndnu-neon-mul8.c",
    "src/qu8-dwconv/gen/up24x25-minmax-rndnu-neon-mul16.c",
    "src/qu8-dwconv/gen/up32x9-minmax-fp32-neon-mul16.c",
    "src/qu8-dwconv/gen/up32x9-minmax-rndnu-neon-mul8.c",
    "src/qu8-dwconv/gen/up32x9-minmax-rndnu-neon-mul16.c",
    "src/qu8-dwconv/gen/up32x25-minmax-fp32-neon-mul16.c",
    "src/qu8-dwconv/gen/up32x25-minmax-rndnu-neon-mul8.c",
    "src/qu8-dwconv/gen/up32x25-minmax-rndnu-neon-mul16.c",
    "src/qu8-f32-vcvt/gen/vcvt-neon-x8.c",
    "src/qu8-f32-vcvt/gen/vcvt-neon-x16.c",
    "src/qu8-f32-vcvt/gen/vcvt-neon-x24.c",
    "src/qu8-f32-vcvt/gen/vcvt-neon-x32.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neon-c8.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neon-c16.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neon-c24.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neon-c32.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-rndnu-neon-c8.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-rndnu-neon-c16.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-rndnu-neon-c24.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-rndnu-neon-c32.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-neon-c8.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-neon-c16.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-neon-c24.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-neon-c32.c",
    "src/qu8-gavgpool/gen/7x-minmax-rndnu-neon-c8.c",
    "src/qu8-gavgpool/gen/7x-minmax-rndnu-neon-c16.c",
    "src/qu8-gavgpool/gen/7x-minmax-rndnu-neon-c24.c",
    "src/qu8-gavgpool/gen/7x-minmax-rndnu-neon-c32.c",
    "src/qu8-gemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
    "src/qu8-gemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
    "src/qu8-gemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/2x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/2x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/3x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/3x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/4x8-minmax-fp32-neon-mlal-lane.c",
    "src/qu8-gemm/gen/4x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
    "src/qu8-gemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/6x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-gemm/gen/6x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/1x8-minmax-fp32-neon-mlal-lane.c",
    "src/qu8-igemm/gen/1x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/1x16-minmax-fp32-neon-mlal-lane.c",
    "src/qu8-igemm/gen/1x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/2x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/2x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/3x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/3x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/4x8-minmax-fp32-neon-mlal-lane.c",
    "src/qu8-igemm/gen/4x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/4x16-minmax-fp32-neon-mlal-lane.c",
    "src/qu8-igemm/gen/4x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/6x8-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-igemm/gen/6x16-minmax-rndnu-neon-mlal-lane.c",
    "src/qu8-requantization/fp32-neon.c",
    "src/qu8-requantization/gemmlowp-neon.c",
    "src/qu8-requantization/rndna-neon.c",
    "src/qu8-vadd/gen/minmax-neon-ld64-x8.c",
    "src/qu8-vadd/gen/minmax-neon-ld64-x16.c",
    "src/qu8-vadd/gen/minmax-neon-ld64-x32.c",
    "src/qu8-vadd/gen/minmax-neon-ld128-x16.c",
    "src/qu8-vaddc/gen/minmax-neon-ld64-x8.c",
    "src/qu8-vaddc/gen/minmax-neon-ld64-x16.c",
    "src/qu8-vaddc/gen/minmax-neon-ld64-x32.c",
    "src/qu8-vaddc/gen/minmax-neon-ld128-x16.c",
    "src/qu8-vcvt/gen/vcvt-neon-x8.c",
    "src/qu8-vcvt/gen/vcvt-neon-x16.c",
    "src/qu8-vcvt/gen/vcvt-neon-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-neon-x8.c",
    "src/qu8-vlrelu/gen/vlrelu-neon-x16.c",
    "src/qu8-vlrelu/gen/vlrelu-neon-x32.c",
    "src/qu8-vmul/gen/minmax-fp32-neon-ld64-x8.c",
    "src/qu8-vmul/gen/minmax-fp32-neon-ld64-x16.c",
    "src/qu8-vmul/gen/minmax-fp32-neon-ld128-x16.c",
    "src/qu8-vmul/gen/minmax-rndnu-neon-ld64-x8.c",
    "src/qu8-vmul/gen/minmax-rndnu-neon-ld64-x16.c",
    "src/qu8-vmul/gen/minmax-rndnu-neon-ld128-x16.c",
    "src/qu8-vmulc/gen/minmax-fp32-neon-ld64-x8.c",
    "src/qu8-vmulc/gen/minmax-fp32-neon-ld64-x16.c",
    "src/qu8-vmulc/gen/minmax-fp32-neon-ld128-x16.c",
    "src/qu8-vmulc/gen/minmax-rndnu-neon-ld64-x8.c",
    "src/qu8-vmulc/gen/minmax-rndnu-neon-ld64-x16.c",
    "src/qu8-vmulc/gen/minmax-rndnu-neon-ld128-x16.c",
    "src/s8-ibilinear/gen/neon-c8.c",
    "src/s8-ibilinear/gen/neon-c16.c",
    "src/s8-maxpool/2p2x-minmax-neon-c16.c",
    "src/s8-maxpool/4p3x-minmax-neon-c16.c",
    "src/s8-maxpool/9p8x-minmax-neon-c16.c",
    "src/s8-vclamp/neon-x64.c",
    "src/s16-rmaxabs/gen/neon-x8.c",
    "src/s16-rmaxabs/gen/neon-x16.c",
    "src/s16-rmaxabs/gen/neon-x24.c",
    "src/s16-rmaxabs/gen/neon-x32.c",
    "src/s16-vlshift/gen/neon-x8.c",
    "src/s16-vlshift/gen/neon-x16.c",
    "src/s16-vlshift/gen/neon-x24.c",
    "src/s16-vlshift/gen/neon-x32.c",
    "src/s16-window/gen/neon-shift12-x8.c",
    "src/s16-window/gen/neon-shift12-x16.c",
    "src/s16-window/gen/neon-shift12-x24.c",
    "src/s16-window/gen/neon-shift12-x32.c",
    "src/s16-window/gen/neon-shift15-x8.c",
    "src/s16-window/gen/neon-shift15-x16.c",
    "src/s16-window/gen/neon-shift15-x24.c",
    "src/s16-window/gen/neon-shift15-x32.c",
    "src/s16-window/gen/neon-x8.c",
    "src/s16-window/gen/neon-x16.c",
    "src/s16-window/gen/neon-x24.c",
    "src/s16-window/gen/neon-x32.c",
    "src/u8-ibilinear/gen/neon-c8.c",
    "src/u8-ibilinear/gen/neon-c16.c",
    "src/u8-maxpool/9p8x-minmax-neon-c16.c",
    "src/u8-rmax/neon.c",
    "src/u8-vclamp/neon-x64.c",
    "src/u32-filterbank-accumulate/gen/neon-x1.c",
    "src/u32-filterbank-accumulate/gen/neon-x2.c",
    "src/xx-fill/neon-x64.c",
    "src/xx-pad/neon.c",
    "src/x8-transposec/gen/8x8-multi-dec-zip-neon.c",
    "src/x8-transposec/gen/8x8-multi-mov-zip-neon.c",
    "src/x8-transposec/gen/8x8-multi-switch-zip-neon.c",
    "src/x8-transposec/gen/8x8-reuse-dec-zip-neon.c",
    "src/x8-transposec/gen/8x8-reuse-mov-zip-neon.c",
    "src/x8-transposec/gen/8x8-reuse-multi-zip-neon.c",
    "src/x8-transposec/gen/8x8-reuse-switch-zip-neon.c",
    "src/x8-transposec/gen/16x16-reuse-dec-zip-neon.c",
    "src/x8-transposec/gen/16x16-reuse-mov-zip-neon.c",
    "src/x8-transposec/gen/16x16-reuse-switch-zip-neon.c",
    "src/x8-zip/xm-neon.c",
    "src/x8-zip/x2-neon.c",
    "src/x8-zip/x3-neon.c",
    "src/x8-zip/x4-neon.c",
    "src/x16-transposec/gen/4x4-multi-dec-zip-neon.c",
    "src/x16-transposec/gen/4x4-multi-mov-zip-neon.c",
    "src/x16-transposec/gen/4x4-multi-multi-zip-neon.c",
    "src/x16-transposec/gen/4x4-multi-switch-zip-neon.c",
    "src/x16-transposec/gen/4x4-reuse-dec-zip-neon.c",
    "src/x16-transposec/gen/4x4-reuse-mov-zip-neon.c",
    "src/x16-transposec/gen/4x4-reuse-multi-zip-neon.c",
    "src/x16-transposec/gen/4x4-reuse-switch-zip-neon.c",
    "src/x16-transposec/gen/8x8-multi-dec-zip-neon.c",
    "src/x16-transposec/gen/8x8-multi-mov-zip-neon.c",
    "src/x16-transposec/gen/8x8-multi-switch-zip-neon.c",
    "src/x16-transposec/gen/8x8-reuse-dec-zip-neon.c",
    "src/x16-transposec/gen/8x8-reuse-mov-zip-neon.c",
    "src/x16-transposec/gen/8x8-reuse-multi-zip-neon.c",
    "src/x16-transposec/gen/8x8-reuse-switch-zip-neon.c",
    "src/x24-transposec/2x2-neon-tbl.c",
    "src/x32-packx/x4-neon-st4.c",
    "src/x32-transposec/gen/2x2-multi-dec-zip-neon.c",
    "src/x32-transposec/gen/2x2-multi-mov-zip-neon.c",
    "src/x32-transposec/gen/2x2-multi-multi-zip-neon.c",
    "src/x32-transposec/gen/2x2-multi-switch-zip-neon.c",
    "src/x32-transposec/gen/2x2-reuse-dec-zip-neon.c",
    "src/x32-transposec/gen/2x2-reuse-mov-zip-neon.c",
    "src/x32-transposec/gen/2x2-reuse-multi-zip-neon.c",
    "src/x32-transposec/gen/2x2-reuse-switch-zip-neon.c",
    "src/x32-transposec/gen/4x4-multi-dec-zip-neon.c",
    "src/x32-transposec/gen/4x4-multi-mov-zip-neon.c",
    "src/x32-transposec/gen/4x4-multi-multi-zip-neon.c",
    "src/x32-transposec/gen/4x4-multi-switch-zip-neon.c",
    "src/x32-transposec/gen/4x4-reuse-dec-zip-neon.c",
    "src/x32-transposec/gen/4x4-reuse-mov-zip-neon.c",
    "src/x32-transposec/gen/4x4-reuse-multi-zip-neon.c",
    "src/x32-transposec/gen/4x4-reuse-switch-zip-neon.c",
    "src/x32-unpool/neon.c",
    "src/x32-zip/xm-neon.c",
    "src/x32-zip/x2-neon.c",
    "src/x32-zip/x3-neon.c",
    "src/x32-zip/x4-neon.c",
]

PROD_NEONFP16_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-neonfp16-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-neonfp16-x16.c",
]

ALL_NEONFP16_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-neonfp16-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-neonfp16-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-neonfp16-x8.c",
    "src/f32-f16-vcvt/gen/vcvt-neonfp16-x16.c",
    "src/math/cvt-f16-f32-neonfp16.c",
    "src/math/cvt-f32-f16-neonfp16.c",
]

PROD_NEONFMA_MICROKERNEL_SRCS = [
    "src/f32-dwconv/gen/up8x3-minmax-neonfma.c",
    "src/f32-dwconv/gen/up8x4-minmax-neonfma.c",
    "src/f32-dwconv/gen/up8x9-minmax-neonfma.c",
    "src/f32-dwconv/gen/up8x25-minmax-neonfma-acc2.c",
    "src/f32-gemm/gen/1x8s4-minmax-neonfma.c",
    "src/f32-gemm/gen/6x8s4-minmax-neonfma.c",
    "src/f32-ibilinear-chw/gen/neonfma-p8.c",
    "src/f32-ibilinear/gen/neonfma-c8.c",
    "src/f32-igemm/gen/1x8s4-minmax-neonfma.c",
    "src/f32-igemm/gen/6x8s4-minmax-neonfma.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x16.c",
    "src/f32-spmm/gen/32x1-minmax-neonfma-pipelined.c",
    "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x16.c",
    "src/f32-velu/gen/velu-neonfma-rr1-p6-x8.c",
    "src/f32-vmulcaddc/gen/c4-minmax-neonfma-2x.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x16.c",
]

ALL_NEONFMA_MICROKERNEL_SRCS = [
    "src/bf16-gemm/gen/1x4c8-minmax-neonfma-shland.c",
    "src/bf16-gemm/gen/2x4c8-minmax-neonfma-shland.c",
    "src/bf16-gemm/gen/3x4c8-minmax-neonfma-shland.c",
    "src/bf16-gemm/gen/4x4c8-minmax-neonfma-shland.c",
    "src/bf16-gemm/gen/5x4c8-minmax-neonfma-shland.c",
    "src/f32-dwconv/gen/up4x3-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up4x3-minmax-neonfma.c",
    "src/f32-dwconv/gen/up4x4-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up4x4-minmax-neonfma.c",
    "src/f32-dwconv/gen/up4x9-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up4x9-minmax-neonfma.c",
    "src/f32-dwconv/gen/up4x25-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up4x25-minmax-neonfma.c",
    "src/f32-dwconv/gen/up8x3-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up8x3-minmax-neonfma.c",
    "src/f32-dwconv/gen/up8x4-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up8x4-minmax-neonfma.c",
    "src/f32-dwconv/gen/up8x9-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up8x9-minmax-neonfma.c",
    "src/f32-dwconv/gen/up8x25-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up8x25-minmax-neonfma.c",
    "src/f32-dwconv/gen/up16x3-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up16x3-minmax-neon.c",
    "src/f32-dwconv/gen/up16x3-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up16x3-minmax-neonfma.c",
    "src/f32-dwconv/gen/up16x4-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up16x4-minmax-neon.c",
    "src/f32-dwconv/gen/up16x4-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up16x4-minmax-neonfma.c",
    "src/f32-dwconv/gen/up16x9-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up16x9-minmax-neon.c",
    "src/f32-dwconv/gen/up16x9-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up16x9-minmax-neonfma.c",
    "src/f32-dwconv/gen/up16x25-minmax-neon-acc2.c",
    "src/f32-dwconv/gen/up16x25-minmax-neon.c",
    "src/f32-dwconv/gen/up16x25-minmax-neonfma-acc2.c",
    "src/f32-dwconv/gen/up16x25-minmax-neonfma.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-neonfma-dup-ld64.c",
    "src/f32-gemm/gen-inc/1x8s4inc-minmax-neonfma.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-neonfma-dup-ld64.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-neonfma-dup-ld128.c",
    "src/f32-gemm/gen-inc/4x8s4inc-minmax-neonfma.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-neonfma-dup-ld64.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-neonfma-dup-ld128.c",
    "src/f32-gemm/gen-inc/6x8s4inc-minmax-neonfma.c",
    "src/f32-gemm/gen-inc/8x8s4inc-minmax-neonfma.c",
    "src/f32-gemm/gen/1x8-minmax-neonfma-dup-ld64.c",
    "src/f32-gemm/gen/1x8s4-minmax-neonfma.c",
    "src/f32-gemm/gen/4x8-minmax-neonfma-dup-ld64.c",
    "src/f32-gemm/gen/4x8-minmax-neonfma-dup-ld128.c",
    "src/f32-gemm/gen/4x8s4-minmax-neonfma.c",
    "src/f32-gemm/gen/6x8-minmax-neonfma-dup-ld64.c",
    "src/f32-gemm/gen/6x8-minmax-neonfma-dup-ld128.c",
    "src/f32-gemm/gen/6x8s4-minmax-neonfma.c",
    "src/f32-gemm/gen/8x8s4-minmax-neonfma.c",
    "src/f32-ibilinear-chw/gen/neonfma-p4.c",
    "src/f32-ibilinear-chw/gen/neonfma-p8.c",
    "src/f32-ibilinear-chw/gen/neonfma-p16.c",
    "src/f32-ibilinear/gen/neonfma-c4.c",
    "src/f32-ibilinear/gen/neonfma-c8.c",
    "src/f32-igemm/gen/1x8-minmax-neonfma-dup-ld64.c",
    "src/f32-igemm/gen/1x8s4-minmax-neonfma.c",
    "src/f32-igemm/gen/4x8-minmax-neonfma-dup-ld64.c",
    "src/f32-igemm/gen/4x8-minmax-neonfma-dup-ld128.c",
    "src/f32-igemm/gen/4x8s4-minmax-neonfma.c",
    "src/f32-igemm/gen/6x8-minmax-neonfma-dup-ld64.c",
    "src/f32-igemm/gen/6x8-minmax-neonfma-dup-ld128.c",
    "src/f32-igemm/gen/6x8s4-minmax-neonfma.c",
    "src/f32-igemm/gen/8x8s4-minmax-neonfma.c",
    "src/f32-ppmm/gen/4x8-minmax-neonfma.c",
    "src/f32-ppmm/gen/8x8-minmax-neonfma.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x4.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x8-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x8.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x12-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x12-acc3.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x12.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x16-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x16-acc4.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x16.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x20-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x20-acc5.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-lut64-p2-x20.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x4.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x8-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x8.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x12-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x12-acc3.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x12.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x16-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x16-acc4.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x16.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x20-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x20-acc5.c",
    "src/f32-raddstoreexpminusmax/gen/neonfma-rr1-p5-x20.c",
    "src/f32-spmm/gen/4x1-minmax-neonfma-pipelined.c",
    "src/f32-spmm/gen/4x1-minmax-neonfma-x2.c",
    "src/f32-spmm/gen/4x1-minmax-neonfma.c",
    "src/f32-spmm/gen/8x1-minmax-neonfma-pipelined.c",
    "src/f32-spmm/gen/8x1-minmax-neonfma-x2.c",
    "src/f32-spmm/gen/8x1-minmax-neonfma.c",
    "src/f32-spmm/gen/12x1-minmax-neonfma.c",
    "src/f32-spmm/gen/16x1-minmax-neonfma-pipelined.c",
    "src/f32-spmm/gen/16x1-minmax-neonfma-x2.c",
    "src/f32-spmm/gen/16x1-minmax-neonfma.c",
    "src/f32-spmm/gen/32x1-minmax-neonfma-pipelined.c",
    "src/f32-spmm/gen/32x1-minmax-neonfma-x2.c",
    "src/f32-spmm/gen/32x1-minmax-neonfma.c",
    "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x4.c",
    "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x8.c",
    "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x12.c",
    "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x16.c",
    "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x20.c",
    "src/f32-velu/gen/velu-neonfma-rr1-lut16-p3-x24.c",
    "src/f32-velu/gen/velu-neonfma-rr1-p6-x4.c",
    "src/f32-velu/gen/velu-neonfma-rr1-p6-x8.c",
    "src/f32-velu/gen/velu-neonfma-rr1-p6-x12.c",
    "src/f32-velu/gen/velu-neonfma-rr1-p6-x16.c",
    "src/f32-velu/gen/velu-neonfma-rr1-p6-x20.c",
    "src/f32-velu/gen/velu-neonfma-rr1-p6-x24.c",
    "src/f32-vmulcaddc/gen/c4-minmax-neonfma-2x.c",
    "src/f32-vmulcaddc/gen/c8-minmax-neonfma-2x.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr1recps1fma-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2fma-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-nr2recps-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr1recps1fma-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2fma-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-nr2recps-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr1recps1fma-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2fma-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-nr2recps-x24.c",
    "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x4.c",
    "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x8.c",
    "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x12.c",
    "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x16.c",
    "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x20.c",
    "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x24.c",
    "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x28.c",
    "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x32.c",
    "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x36.c",
    "src/f32-vsqrt/gen/neonfma-nr1rsqrts1fma1adj-x40.c",
    "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x4.c",
    "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x8.c",
    "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x12.c",
    "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x16.c",
    "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x20.c",
    "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x24.c",
    "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x28.c",
    "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x32.c",
    "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x36.c",
    "src/f32-vsqrt/gen/neonfma-nr2fma1adj-x40.c",
    "src/math/exp-f32-neonfma-rr2-lut64-p2.c",
    "src/math/exp-f32-neonfma-rr2-p5.c",
    "src/math/expminus-f32-neonfma-rr2-lut64-p2.c",
    "src/math/expminus-f32-neonfma-rr2-lut2048-p1.c",
    "src/math/expminus-f32-neonfma-rr2-p5.c",
    "src/math/expm1minus-f32-neonfma-rr1-lut16-p3.c",
    "src/math/expm1minus-f32-neonfma-rr1-p6.c",
    "src/math/sigmoid-f32-neonfma-rr1-lut64-p2-nr1recps1fma.c",
    "src/math/sigmoid-f32-neonfma-rr1-lut64-p2-nr2fma.c",
    "src/math/sigmoid-f32-neonfma-rr1-lut64-p2-nr2recps.c",
    "src/math/sigmoid-f32-neonfma-rr1-lut2048-p1-nr1recps1fma.c",
    "src/math/sigmoid-f32-neonfma-rr1-lut2048-p1-nr2fma.c",
    "src/math/sigmoid-f32-neonfma-rr1-lut2048-p1-nr2recps.c",
    "src/math/sigmoid-f32-neonfma-rr1-p5-nr1recps1fma.c",
    "src/math/sigmoid-f32-neonfma-rr1-p5-nr2fma.c",
    "src/math/sigmoid-f32-neonfma-rr1-p5-nr2recps.c",
    "src/math/sigmoid-f32-neonfma-rr2-lut64-p2-nr1recps1fma.c",
    "src/math/sigmoid-f32-neonfma-rr2-lut64-p2-nr2fma.c",
    "src/math/sigmoid-f32-neonfma-rr2-lut64-p2-nr2recps.c",
    "src/math/sigmoid-f32-neonfma-rr2-lut2048-p1-nr1recps1fma.c",
    "src/math/sigmoid-f32-neonfma-rr2-lut2048-p1-nr2fma.c",
    "src/math/sigmoid-f32-neonfma-rr2-lut2048-p1-nr2recps.c",
    "src/math/sigmoid-f32-neonfma-rr2-p5-nr1recps1fma.c",
    "src/math/sigmoid-f32-neonfma-rr2-p5-nr2fma.c",
    "src/math/sigmoid-f32-neonfma-rr2-p5-nr2recps.c",
    "src/math/sqrt-neonfma-nr1fma.c",
    "src/math/sqrt-neonfma-nr1rsqrts1fma1adj.c",
    "src/math/sqrt-neonfma-nr2fma.c",
    "src/math/sqrt-neonfma-nr2fma1adj.c",
    "src/math/sqrt-neonfma-nr3fma.c",
]

PROD_AARCH64_NEON_MICROKERNEL_SRCS = [
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-neonfma-2x2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4-acc2.c",
    "src/f32-gemm/gen/1x8-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen/6x2-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen/6x8-minmax-neonfma-lane-ld64.c",
    "src/f32-igemm/gen/1x8-minmax-neonfma-lane-ld64.c",
    "src/f32-igemm/gen/6x2-minmax-neonfma-lane-ld64.c",
    "src/f32-igemm/gen/6x8-minmax-neonfma-lane-ld64.c",
    "src/f32-spmm/gen/32x2-minmax-neonfma.c",
    "src/f32-spmm/gen/32x4-minmax-neonfma.c",
    "src/f32-vbinary/gen/vdiv-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vdivc-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-neon-x8.c",
    "src/f32-vsqrt/gen/neon-sqrt-x4.c",
    "src/x8-lut/gen/lut-neon-tbx128x4-x64.c",
    "src/x32-transposec/4x4-aarch64-tbl.c",
]

ALL_AARCH64_NEON_MICROKERNEL_SRCS = [
    "src/bf16-gemm/gen/1x4c8-minmax-neonfma-zip.c",
    "src/bf16-gemm/gen/2x4c8-minmax-neonfma-zip.c",
    "src/bf16-gemm/gen/3x4c8-minmax-neonfma-zip.c",
    "src/bf16-gemm/gen/4x4c8-minmax-neonfma-zip.c",
    "src/bf16-gemm/gen/5x4c8-minmax-neonfma-zip.c",
    "src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neonfma-2x1.c",
    "src/f32-conv-hwc/gen/3x3s2p0p1c3x4-neonfma-2x2.c",
    "src/f32-conv-hwc/gen/3x3s2p0p1c3x8-neonfma-2x1.c",
    "src/f32-conv-hwc/gen/3x3s2p0p1c3x8-neonfma-2x2.c",
    "src/f32-conv-hwc/gen/3x3s2p1c3x4-neonfma-2x1.c",
    "src/f32-conv-hwc/gen/3x3s2p1c3x4-neonfma-2x2.c",
    "src/f32-conv-hwc/gen/3x3s2p1c3x8-neonfma-2x1.c",
    "src/f32-conv-hwc/gen/3x3s2p1c3x8-neonfma-2x2.c",
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-neonfma-2x2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-4x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-5x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-neonfma-6x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-neonfma-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-3x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-4x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-neonfma-5x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-neonfma-3x4.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-neonfma-lane-ld128.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-neonfma-lane-ld128.c",
    "src/f32-gemm/gen/1x8-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen/4x2-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen/4x8-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen/4x8-minmax-neonfma-lane-ld128.c",
    "src/f32-gemm/gen/5x8-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen/6x2-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen/6x8-minmax-neonfma-lane-ld64.c",
    "src/f32-gemm/gen/6x8-minmax-neonfma-lane-ld128.c",
    "src/f32-igemm/gen/1x8-minmax-neonfma-lane-ld64.c",
    "src/f32-igemm/gen/4x2-minmax-neonfma-lane-ld64.c",
    "src/f32-igemm/gen/4x4-minmax-neonfma-lane-ld64.c",
    "src/f32-igemm/gen/4x8-minmax-neonfma-lane-ld64.c",
    "src/f32-igemm/gen/4x8-minmax-neonfma-lane-ld128.c",
    "src/f32-igemm/gen/6x2-minmax-neonfma-lane-ld64.c",
    "src/f32-igemm/gen/6x8-minmax-neonfma-lane-ld64.c",
    "src/f32-igemm/gen/6x8-minmax-neonfma-lane-ld128.c",
    "src/f32-spmm/gen/4x2-minmax-neonfma.c",
    "src/f32-spmm/gen/4x4-minmax-neonfma.c",
    "src/f32-spmm/gen/8x2-minmax-neonfma.c",
    "src/f32-spmm/gen/8x4-minmax-neonfma.c",
    "src/f32-spmm/gen/12x2-minmax-neonfma.c",
    "src/f32-spmm/gen/12x4-minmax-neonfma.c",
    "src/f32-spmm/gen/16x2-minmax-neonfma.c",
    "src/f32-spmm/gen/16x4-minmax-neonfma.c",
    "src/f32-spmm/gen/32x2-minmax-neonfma.c",
    "src/f32-spmm/gen/32x4-minmax-neonfma.c",
    "src/f32-vbinary/gen/vdiv-minmax-neon-x4.c",
    "src/f32-vbinary/gen/vdiv-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vdivc-minmax-neon-x4.c",
    "src/f32-vbinary/gen/vdivc-minmax-neon-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-neon-x4.c",
    "src/f32-vbinary/gen/vrdivc-minmax-neon-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut64-p2-div-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-lut2048-p1-div-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-neonfma-rr1-p5-div-x24.c",
    "src/f32-vsqrt/gen/neon-sqrt-x4.c",
    "src/f32-vsqrt/gen/neon-sqrt-x8.c",
    "src/math/sigmoid-f32-neonfma-rr1-lut64-p2-div.c",
    "src/math/sigmoid-f32-neonfma-rr1-lut2048-p1-div.c",
    "src/math/sigmoid-f32-neonfma-rr1-p5-div.c",
    "src/math/sigmoid-f32-neonfma-rr2-lut64-p2-div.c",
    "src/math/sigmoid-f32-neonfma-rr2-lut2048-p1-div.c",
    "src/math/sigmoid-f32-neonfma-rr2-p5-div.c",
    "src/x8-lut/gen/lut-neon-tbx128x4-x16.c",
    "src/x8-lut/gen/lut-neon-tbx128x4-x32.c",
    "src/x8-lut/gen/lut-neon-tbx128x4-x48.c",
    "src/x8-lut/gen/lut-neon-tbx128x4-x64.c",
    "src/x24-transposec/4x4-aarch64-tbl.c",
    "src/x32-transposec/4x4-aarch64-tbl.c",
]

PROD_NEONV8_MICROKERNEL_SRCS = [
    "src/f32-qs8-vcvt/gen/vcvt-neonv8-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-neonv8-x32.c",
    "src/f32-vrnd/gen/vrndd-neonv8-x8.c",
    "src/f32-vrnd/gen/vrndne-neonv8-x8.c",
    "src/f32-vrnd/gen/vrndu-neonv8-x8.c",
    "src/f32-vrnd/gen/vrndz-neonv8-x8.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mla8-ld64.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-neonv8-mla8-ld128.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mla8-ld64.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mla8-ld64.c",
    "src/qc8-gemm/gen/1x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/1x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-gemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qc8-gemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qc8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-gemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qc8-gemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qc8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/1x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/1x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qc8-igemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qc8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qc8-igemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qc8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
]

ALL_NEONV8_MICROKERNEL_SRCS = [
    "src/f32-qs8-vcvt/gen/vcvt-neonv8-x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-neonv8-x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-neonv8-x24.c",
    "src/f32-qs8-vcvt/gen/vcvt-neonv8-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-neonv8-x8.c",
    "src/f32-qu8-vcvt/gen/vcvt-neonv8-x16.c",
    "src/f32-qu8-vcvt/gen/vcvt-neonv8-x24.c",
    "src/f32-qu8-vcvt/gen/vcvt-neonv8-x32.c",
    "src/f32-vrnd/gen/vrndd-neonv8-x4.c",
    "src/f32-vrnd/gen/vrndd-neonv8-x8.c",
    "src/f32-vrnd/gen/vrndne-neonv8-x4.c",
    "src/f32-vrnd/gen/vrndne-neonv8-x8.c",
    "src/f32-vrnd/gen/vrndu-neonv8-x4.c",
    "src/f32-vrnd/gen/vrndu-neonv8-x8.c",
    "src/f32-vrnd/gen/vrndz-neonv8-x4.c",
    "src/f32-vrnd/gen/vrndz-neonv8-x8.c",
    "src/math/cvt-f32-qs8-neonv8.c",
    "src/math/cvt-f32-qu8-neonv8.c",
    "src/math/roundd-neonv8.c",
    "src/math/roundne-neonv8.c",
    "src/math/roundu-neonv8.c",
    "src/math/roundz-neonv8.c",
    "src/qc8-dwconv/gen/up8x3-minmax-fp32-neonv8-mla8-ld64.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-neonv8-mla8-ld64.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul8-ld64.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mla8-ld64.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul8-ld64.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul16.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-neonv8-mla8-ld64.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-neonv8-mla8-ld128.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mla8-ld64.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mla8-ld128.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul8-ld64.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul8-ld128.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mla8-ld64.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mla8-ld128.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul8-ld64.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul8-ld128.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul16.c",
    "src/qc8-dwconv/gen/up24x9-minmax-fp32-neonv8-mul16.c",
    "src/qc8-dwconv/gen/up24x25-minmax-fp32-neonv8-mul16.c",
    "src/qc8-dwconv/gen/up32x9-minmax-fp32-neonv8-mul16.c",
    "src/qc8-dwconv/gen/up32x25-minmax-fp32-neonv8-mul16.c",
    "src/qc8-gemm/gen/1x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/1x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-dup.c",
    "src/qc8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qc8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qc8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
    "src/qc8-gemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qc8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-dup.c",
    "src/qc8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qc8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qc8-gemm/gen/1x8c4s2-minmax-fp32-neonv8-mlal.c",
    "src/qc8-gemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qc8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-gemm/gen/2x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/2x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-dup.c",
    "src/qc8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qc8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qc8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
    "src/qc8-gemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qc8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-dup.c",
    "src/qc8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qc8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qc8-gemm/gen/2x8c4s2-minmax-fp32-neonv8-mlal.c",
    "src/qc8-gemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qc8-gemm/gen/2x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/2x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-gemm/gen/3x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/3x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-gemm/gen/3x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/3x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-gemm/gen/4x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/4x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-gemm/gen/6x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/6x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-gemm/gen/6x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-gemm/gen/6x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/1x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/1x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-dup.c",
    "src/qc8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qc8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qc8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
    "src/qc8-igemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qc8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-dup.c",
    "src/qc8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qc8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qc8-igemm/gen/1x8c4s2-minmax-fp32-neonv8-mlal.c",
    "src/qc8-igemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qc8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/2x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/2x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-dup.c",
    "src/qc8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qc8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qc8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
    "src/qc8-igemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qc8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-dup.c",
    "src/qc8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qc8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qc8-igemm/gen/2x8c4s2-minmax-fp32-neonv8-mlal.c",
    "src/qc8-igemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qc8-igemm/gen/2x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/2x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/3x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/3x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/3x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/3x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/4x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/4x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/6x8-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/6x8-minmax-fp32-neonv8-mlal-lane.c",
    "src/qc8-igemm/gen/6x16-minmax-fp32-neonv8-mlal-lane-prfm.c",
    "src/qc8-igemm/gen/6x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul16.c",
    "src/qs8-dwconv/gen/up24x9-minmax-fp32-neonv8-mul16.c",
    "src/qs8-dwconv/gen/up24x25-minmax-fp32-neonv8-mul16.c",
    "src/qs8-dwconv/gen/up32x9-minmax-fp32-neonv8-mul16.c",
    "src/qs8-dwconv/gen/up32x25-minmax-fp32-neonv8-mul16.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c8.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c16.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c24.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c32.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-neonv8-c8.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-neonv8-c16.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-neonv8-c24.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-neonv8-c32.c",
    "src/qs8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-dup.c",
    "src/qs8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qs8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qs8-gemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
    "src/qs8-gemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qs8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-dup.c",
    "src/qs8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qs8-gemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qs8-gemm/gen/1x8c4s2-minmax-fp32-neonv8-mlal.c",
    "src/qs8-gemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qs8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qs8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-dup.c",
    "src/qs8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qs8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qs8-gemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
    "src/qs8-gemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qs8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-dup.c",
    "src/qs8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qs8-gemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qs8-gemm/gen/2x8c4s2-minmax-fp32-neonv8-mlal.c",
    "src/qs8-gemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qs8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qs8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-dup.c",
    "src/qs8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qs8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qs8-igemm/gen/1x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
    "src/qs8-igemm/gen/1x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qs8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-dup.c",
    "src/qs8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qs8-igemm/gen/1x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qs8-igemm/gen/1x8c4s2-minmax-fp32-neonv8-mlal.c",
    "src/qs8-igemm/gen/1x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qs8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qs8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-dup.c",
    "src/qs8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qs8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qs8-igemm/gen/2x8c2-minmax-fp32-neonv8-mlal-ld4r.c",
    "src/qs8-igemm/gen/2x8c2s4-minmax-fp32-neonv8-mlal.c",
    "src/qs8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-dup.c",
    "src/qs8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld1r.c",
    "src/qs8-igemm/gen/2x8c4-minmax-fp32-neonv8-mlal-ld2r.c",
    "src/qs8-igemm/gen/2x8c4s2-minmax-fp32-neonv8-mlal.c",
    "src/qs8-igemm/gen/2x8c8-minmax-fp32-neonv8-mlal.c",
    "src/qs8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qs8-vmul/gen/minmax-fp32-neonv8-ld64-x8.c",
    "src/qs8-vmul/gen/minmax-fp32-neonv8-ld64-x16.c",
    "src/qs8-vmul/gen/minmax-fp32-neonv8-ld128-x16.c",
    "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld64-x8.c",
    "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld64-x16.c",
    "src/qs8-vmulc/gen/minmax-fp32-neonv8-ld128-x16.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-neonv8-mul16.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-neonv8-mul16.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-neonv8-mul16.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-neonv8-mul16.c",
    "src/qu8-dwconv/gen/up24x9-minmax-fp32-neonv8-mul16.c",
    "src/qu8-dwconv/gen/up24x25-minmax-fp32-neonv8-mul16.c",
    "src/qu8-dwconv/gen/up32x9-minmax-fp32-neonv8-mul16.c",
    "src/qu8-dwconv/gen/up32x25-minmax-fp32-neonv8-mul16.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c8.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c16.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c24.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-neonv8-c32.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-neonv8-c8.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-neonv8-c16.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-neonv8-c24.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-neonv8-c32.c",
    "src/qu8-gemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qu8-gemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qu8-igemm/gen/1x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qu8-igemm/gen/4x16-minmax-fp32-neonv8-mlal-lane.c",
    "src/qu8-vmul/gen/minmax-fp32-neonv8-ld64-x8.c",
    "src/qu8-vmul/gen/minmax-fp32-neonv8-ld64-x16.c",
    "src/qu8-vmul/gen/minmax-fp32-neonv8-ld128-x16.c",
    "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld64-x8.c",
    "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld64-x16.c",
    "src/qu8-vmulc/gen/minmax-fp32-neonv8-ld128-x16.c",
]

PROD_NEONFP16ARITH_MICROKERNEL_SRCS = [
    "src/f16-avgpool/9p8x-minmax-neonfp16arith-c8.c",
    "src/f16-avgpool/9x-minmax-neonfp16arith-c8.c",
    "src/f16-dwconv/gen/up8x25-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up16x3-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up16x4-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up16x9-minmax-neonfp16arith.c",
    "src/f16-gavgpool-cw/neonfp16arith-x4.c",
    "src/f16-gavgpool/gen/7p7x-minmax-neonfp16arith-c8.c",
    "src/f16-gavgpool/gen/7x-minmax-neonfp16arith-c8.c",
    "src/f16-gemm/gen/1x16-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen/6x16-minmax-neonfp16arith-ld64.c",
    "src/f16-ibilinear-chw/gen/neonfp16arith-p8.c",
    "src/f16-ibilinear/gen/neonfp16arith-c8.c",
    "src/f16-igemm/gen/1x16-minmax-neonfp16arith-ld64.c",
    "src/f16-igemm/gen/6x16-minmax-neonfp16arith-ld64.c",
    "src/f16-maxpool/9p8x-minmax-neonfp16arith-c8.c",
    "src/f16-pavgpool/9p8x-minmax-neonfp16arith-c8.c",
    "src/f16-pavgpool/9x-minmax-neonfp16arith-c8.c",
    "src/f16-prelu/gen/neonfp16arith-2x16.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x40.c",
    "src/f16-rmax/neonfp16arith.c",
    "src/f16-spmm/gen/32x1-minmax-neonfp16arith.c",
    "src/f16-vbinary/gen/vadd-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vaddc-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vmaxc-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vmin-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vminc-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vmul-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vmulc-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vrsubc-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vsqrdiff-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vsqrdiffc-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vsub-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vsubc-minmax-neonfp16arith-x16.c",
    "src/f16-vclamp/gen/vclamp-neonfp16arith-x16.c",
    "src/f16-velu/gen/velu-neonfp16arith-rr1-p3-x16.c",
    "src/f16-vhswish/gen/vhswish-neonfp16arith-x16.c",
    "src/f16-vlrelu/gen/vlrelu-neonfp16arith-x16.c",
    "src/f16-vmulcaddc/gen/c8-minmax-neonfp16arith-2x.c",
    "src/f16-vrnd/gen/vrndd-neonfp16arith-x16.c",
    "src/f16-vrnd/gen/vrndne-neonfp16arith-x16.c",
    "src/f16-vrnd/gen/vrndu-neonfp16arith-x16.c",
    "src/f16-vrnd/gen/vrndz-neonfp16arith-x16.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1fma-x40.c",
    "src/f16-vunary/gen/vabs-neonfp16arith-x16.c",
    "src/f16-vunary/gen/vneg-neonfp16arith-x16.c",
    "src/f16-vunary/gen/vsqr-neonfp16arith-x16.c",
]

ALL_NEONFP16ARITH_MICROKERNEL_SRCS = [
    "src/f16-avgpool/9p8x-minmax-neonfp16arith-c8.c",
    "src/f16-avgpool/9x-minmax-neonfp16arith-c8.c",
    "src/f16-dwconv/gen/up8x3-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up8x3-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up8x4-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up8x4-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up8x9-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up8x9-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up8x25-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up8x25-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up16x3-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up16x3-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up16x4-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up16x4-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up16x9-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up16x9-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up16x25-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up16x25-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up32x3-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up32x3-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up32x4-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up32x4-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up32x9-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up32x9-minmax-neonfp16arith.c",
    "src/f16-dwconv/gen/up32x25-minmax-neonfp16arith-acc2.c",
    "src/f16-dwconv/gen/up32x25-minmax-neonfp16arith.c",
    "src/f16-gavgpool-cw/neonfp16arith-x4.c",
    "src/f16-gavgpool-cw/neonfp16arith-x8.c",
    "src/f16-gavgpool/gen/7p7x-minmax-neonfp16arith-c8.c",
    "src/f16-gavgpool/gen/7p7x-minmax-neonfp16arith-c16.c",
    "src/f16-gavgpool/gen/7p7x-minmax-neonfp16arith-c24.c",
    "src/f16-gavgpool/gen/7p7x-minmax-neonfp16arith-c32.c",
    "src/f16-gavgpool/gen/7x-minmax-neonfp16arith-c8.c",
    "src/f16-gavgpool/gen/7x-minmax-neonfp16arith-c16.c",
    "src/f16-gavgpool/gen/7x-minmax-neonfp16arith-c24.c",
    "src/f16-gavgpool/gen/7x-minmax-neonfp16arith-c32.c",
    "src/f16-gemm/gen-inc/1x8inc-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen-inc/1x16inc-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen-inc/4x8inc-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen-inc/4x16inc-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen-inc/6x8inc-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen-inc/6x16inc-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen-inc/8x8inc-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen-inc/8x16inc-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen/1x8-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen/1x16-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen/4x8-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen/4x16-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen/6x8-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen/6x16-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen/8x8-minmax-neonfp16arith-ld64.c",
    "src/f16-gemm/gen/8x16-minmax-neonfp16arith-ld64.c",
    "src/f16-ibilinear-chw/gen/neonfp16arith-p4.c",
    "src/f16-ibilinear-chw/gen/neonfp16arith-p8.c",
    "src/f16-ibilinear-chw/gen/neonfp16arith-p16.c",
    "src/f16-ibilinear/gen/neonfp16arith-c8.c",
    "src/f16-ibilinear/gen/neonfp16arith-c16.c",
    "src/f16-igemm/gen/1x8-minmax-neonfp16arith-ld64.c",
    "src/f16-igemm/gen/1x16-minmax-neonfp16arith-ld64.c",
    "src/f16-igemm/gen/4x8-minmax-neonfp16arith-ld64.c",
    "src/f16-igemm/gen/4x16-minmax-neonfp16arith-ld64.c",
    "src/f16-igemm/gen/6x8-minmax-neonfp16arith-ld64.c",
    "src/f16-igemm/gen/6x16-minmax-neonfp16arith-ld64.c",
    "src/f16-igemm/gen/8x8-minmax-neonfp16arith-ld64.c",
    "src/f16-igemm/gen/8x16-minmax-neonfp16arith-ld64.c",
    "src/f16-maxpool/9p8x-minmax-neonfp16arith-c8.c",
    "src/f16-pavgpool/9p8x-minmax-neonfp16arith-c8.c",
    "src/f16-pavgpool/9x-minmax-neonfp16arith-c8.c",
    "src/f16-prelu/gen/neonfp16arith-2x8.c",
    "src/f16-prelu/gen/neonfp16arith-2x16.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x32-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x32-acc4.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x32.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x40-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x40-acc5.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x40.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x48-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x48-acc3.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x48.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x64-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x64-acc4.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x64.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x72-acc3.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x72.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x80-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x80-acc5.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x80.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x96-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x96-acc3.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x96-acc6.c",
    "src/f16-raddstoreexpminusmax/gen/neonfp16arith-rr2-p2-x96.c",
    "src/f16-rmax/neonfp16arith.c",
    "src/f16-spmm/gen/8x1-minmax-neonfp16arith-x2.c",
    "src/f16-spmm/gen/8x1-minmax-neonfp16arith.c",
    "src/f16-spmm/gen/16x1-minmax-neonfp16arith-x2.c",
    "src/f16-spmm/gen/16x1-minmax-neonfp16arith.c",
    "src/f16-spmm/gen/24x1-minmax-neonfp16arith-x2.c",
    "src/f16-spmm/gen/24x1-minmax-neonfp16arith.c",
    "src/f16-spmm/gen/32x1-minmax-neonfp16arith-x2.c",
    "src/f16-spmm/gen/32x1-minmax-neonfp16arith.c",
    "src/f16-vbinary/gen/vadd-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vadd-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vaddc-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vaddc-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vmaxc-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vmaxc-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vmin-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vmin-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vminc-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vminc-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vmul-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vmul-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vmulc-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vmulc-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vrsubc-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vrsubc-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vsqrdiff-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vsqrdiff-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vsqrdiffc-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vsqrdiffc-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vsub-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vsub-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vsubc-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vsubc-minmax-neonfp16arith-x16.c",
    "src/f16-vclamp/gen/vclamp-neonfp16arith-x8.c",
    "src/f16-vclamp/gen/vclamp-neonfp16arith-x16.c",
    "src/f16-velu/gen/velu-neonfp16arith-rr1-p3-x8.c",
    "src/f16-velu/gen/velu-neonfp16arith-rr1-p3-x16.c",
    "src/f16-vhswish/gen/vhswish-neonfp16arith-x8.c",
    "src/f16-vhswish/gen/vhswish-neonfp16arith-x16.c",
    "src/f16-vlrelu/gen/vlrelu-neonfp16arith-x8.c",
    "src/f16-vlrelu/gen/vlrelu-neonfp16arith-x16.c",
    "src/f16-vmulcaddc/gen/c8-minmax-neonfp16arith-2x.c",
    "src/f16-vmulcaddc/gen/c16-minmax-neonfp16arith-2x.c",
    "src/f16-vrnd/gen/vrndd-neonfp16arith-x8.c",
    "src/f16-vrnd/gen/vrndd-neonfp16arith-x16.c",
    "src/f16-vrnd/gen/vrndne-neonfp16arith-x8.c",
    "src/f16-vrnd/gen/vrndne-neonfp16arith-x16.c",
    "src/f16-vrnd/gen/vrndu-neonfp16arith-x8.c",
    "src/f16-vrnd/gen/vrndu-neonfp16arith-x16.c",
    "src/f16-vrnd/gen/vrndz-neonfp16arith-x8.c",
    "src/f16-vrnd/gen/vrndz-neonfp16arith-x16.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1fma-x8.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1fma-x16.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1fma-x24.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1fma-x32.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1fma-x40.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1fma-x48.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1fma-x56.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1fma-x64.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1recps-x8.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1recps-x16.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1recps-x24.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1recps-x32.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1recps-x40.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1recps-x48.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1recps-x56.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-nr1recps-x64.c",
    "src/f16-vunary/gen/vabs-neonfp16arith-x8.c",
    "src/f16-vunary/gen/vabs-neonfp16arith-x16.c",
    "src/f16-vunary/gen/vneg-neonfp16arith-x8.c",
    "src/f16-vunary/gen/vneg-neonfp16arith-x16.c",
    "src/f16-vunary/gen/vsqr-neonfp16arith-x8.c",
    "src/f16-vunary/gen/vsqr-neonfp16arith-x16.c",
    "src/math/exp-f16-neonfp16arith-rr2-p3.c",
    "src/math/expminus-f16-neonfp16arith-rr1-p2.c",
    "src/math/expminus-f16-neonfp16arith-rr1-p3.c",
    "src/math/expminus-f16-neonfp16arith-rr2-p2.c",
    "src/math/expminus-f16-neonfp16arith-rr2-p3.c",
    "src/math/expm1minus-f16-neonfp16arith-rr1-p3.c",
    "src/math/expm1minus-f16-neonfp16arith-rr2-p3.c",
    "src/math/sigmoid-f16-neonfp16arith-rr2-p2-nr1fma.c",
    "src/math/sigmoid-f16-neonfp16arith-rr2-p2-nr1recps.c",
    "src/math/sigmoid-f16-neonfp16arith-rr2-p2-recpe.c",
    "src/math/sigmoid-f16-neonfp16arith-rr2-p3-nr1fma.c",
    "src/math/sigmoid-f16-neonfp16arith-rr2-p3-nr1recps.c",
    "src/math/sigmoid-f16-neonfp16arith-rr2-p3-recpe.c",
]

PROD_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS = [
    "src/f16-conv-hwc2chw/3x3s2p1c3x4-neonfp16arith-2x2.c",
    "src/f16-dwconv2d-chw/gen/3x3p1-minmax-neonfp16arith-2x8.c",
    "src/f16-dwconv2d-chw/gen/3x3s2p1-minmax-neonfp16arith-1x4.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-1x4.c",
    "src/f16-dwconv2d-chw/gen/5x5s2p2-minmax-neonfp16arith-1x4.c",
    "src/f16-vbinary/gen/vdiv-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vdivc-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vrdivc-minmax-neonfp16arith-x8.c",
    "src/f16-vsqrt/gen/neonfp16arith-sqrt-x8.c",
]

ALL_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS = [
    "src/f16-conv-hwc2chw/3x3s2p1c3x4-neonfp16arith-2x2.c",
    "src/f16-dwconv2d-chw/gen/3x3p1-minmax-neonfp16arith-1x8-acc2.c",
    "src/f16-dwconv2d-chw/gen/3x3p1-minmax-neonfp16arith-1x8-acc3.c",
    "src/f16-dwconv2d-chw/gen/3x3p1-minmax-neonfp16arith-1x8-acc4.c",
    "src/f16-dwconv2d-chw/gen/3x3p1-minmax-neonfp16arith-1x8.c",
    "src/f16-dwconv2d-chw/gen/3x3p1-minmax-neonfp16arith-2x8-acc2.c",
    "src/f16-dwconv2d-chw/gen/3x3p1-minmax-neonfp16arith-2x8.c",
    "src/f16-dwconv2d-chw/gen/3x3p1-minmax-neonfp16arith-3x8.c",
    "src/f16-dwconv2d-chw/gen/3x3p1-minmax-neonfp16arith-4x8.c",
    "src/f16-dwconv2d-chw/gen/3x3p1-minmax-neonfp16arith-5x8.c",
    "src/f16-dwconv2d-chw/gen/3x3p1-minmax-neonfp16arith-6x8.c",
    "src/f16-dwconv2d-chw/gen/3x3s2p1-minmax-neonfp16arith-1x4-acc2.c",
    "src/f16-dwconv2d-chw/gen/3x3s2p1-minmax-neonfp16arith-1x4-acc3.c",
    "src/f16-dwconv2d-chw/gen/3x3s2p1-minmax-neonfp16arith-1x4-acc4.c",
    "src/f16-dwconv2d-chw/gen/3x3s2p1-minmax-neonfp16arith-1x4.c",
    "src/f16-dwconv2d-chw/gen/3x3s2p1-minmax-neonfp16arith-2x4-acc2.c",
    "src/f16-dwconv2d-chw/gen/3x3s2p1-minmax-neonfp16arith-2x4.c",
    "src/f16-dwconv2d-chw/gen/3x3s2p1-minmax-neonfp16arith-3x4.c",
    "src/f16-dwconv2d-chw/gen/3x3s2p1-minmax-neonfp16arith-4x4.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-1x4-acc2.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-1x4-acc3.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-1x4-acc4.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-1x4-acc5.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-1x4.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-2x4-acc2.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-2x4-acc3.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-2x4.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-3x4-acc2.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-3x4.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-4x4-acc2.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-4x4.c",
    "src/f16-dwconv2d-chw/gen/5x5p2-minmax-neonfp16arith-5x4.c",
    "src/f16-dwconv2d-chw/gen/5x5s2p2-minmax-neonfp16arith-1x4-acc2.c",
    "src/f16-dwconv2d-chw/gen/5x5s2p2-minmax-neonfp16arith-1x4-acc3.c",
    "src/f16-dwconv2d-chw/gen/5x5s2p2-minmax-neonfp16arith-1x4-acc4.c",
    "src/f16-dwconv2d-chw/gen/5x5s2p2-minmax-neonfp16arith-1x4-acc5.c",
    "src/f16-dwconv2d-chw/gen/5x5s2p2-minmax-neonfp16arith-1x4.c",
    "src/f16-dwconv2d-chw/gen/5x5s2p2-minmax-neonfp16arith-2x4-acc2.c",
    "src/f16-dwconv2d-chw/gen/5x5s2p2-minmax-neonfp16arith-2x4-acc3.c",
    "src/f16-dwconv2d-chw/gen/5x5s2p2-minmax-neonfp16arith-2x4.c",
    "src/f16-dwconv2d-chw/gen/5x5s2p2-minmax-neonfp16arith-3x4-acc2.c",
    "src/f16-dwconv2d-chw/gen/5x5s2p2-minmax-neonfp16arith-3x4.c",
    "src/f16-vbinary/gen/vdiv-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vdiv-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vdivc-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vdivc-minmax-neonfp16arith-x16.c",
    "src/f16-vbinary/gen/vrdivc-minmax-neonfp16arith-x8.c",
    "src/f16-vbinary/gen/vrdivc-minmax-neonfp16arith-x16.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-div-x8.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-div-x16.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-div-x24.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-div-x32.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-div-x40.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-div-x48.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-div-x56.c",
    "src/f16-vsigmoid/gen/vsigmoid-neonfp16arith-rr2-p2-div-x64.c",
    "src/f16-vsqrt/gen/neonfp16arith-sqrt-x8.c",
    "src/f16-vsqrt/gen/neonfp16arith-sqrt-x16.c",
    "src/math/sigmoid-f16-neonfp16arith-rr1-p2-div.c",
    "src/math/sigmoid-f16-neonfp16arith-rr1-p3-div.c",
    "src/math/sigmoid-f16-neonfp16arith-rr2-p2-div.c",
    "src/math/sigmoid-f16-neonfp16arith-rr2-p3-div.c",
]

PROD_NEONBF16_MICROKERNEL_SRCS = [
]

ALL_NEONBF16_MICROKERNEL_SRCS = [
    "src/bf16-gemm/gen/1x4c8-minmax-neonbf16-bfdot.c",
    "src/bf16-gemm/gen/1x4c8-minmax-neonbf16-bfmlal.c",
    "src/bf16-gemm/gen/1x8c2-minmax-neonbf16-bfdot-lane-ld128.c",
    "src/bf16-gemm/gen/2x4c8-minmax-neonbf16-bfdot.c",
    "src/bf16-gemm/gen/2x4c8-minmax-neonbf16-bfmlal.c",
    "src/bf16-gemm/gen/3x4c8-minmax-neonbf16-bfdot.c",
    "src/bf16-gemm/gen/3x4c8-minmax-neonbf16-bfmlal.c",
    "src/bf16-gemm/gen/4x4c8-minmax-neonbf16-bfdot.c",
    "src/bf16-gemm/gen/4x4c8-minmax-neonbf16-bfmlal.c",
    "src/bf16-gemm/gen/4x8c2-minmax-neonbf16-bfdot-lane-ld128.c",
    "src/bf16-gemm/gen/5x4c8-minmax-neonbf16-bfdot.c",
    "src/bf16-gemm/gen/5x4c8-minmax-neonbf16-bfmlal.c",
    "src/bf16-gemm/gen/5x8c2-minmax-neonbf16-bfdot-lane-ld128.c",
    "src/bf16-gemm/gen/6x8c2-minmax-neonbf16-bfdot-lane-ld128.c",
]

PROD_AARCH64_NEONBF16_MICROKERNEL_SRCS = [
]

ALL_AARCH64_NEONBF16_MICROKERNEL_SRCS = [
]

PROD_NEONDOT_MICROKERNEL_SRCS = [
    "src/qc8-gemm/gen/1x8c4-minmax-fp32-neondot.c",
    "src/qc8-gemm/gen/1x16c4-minmax-fp32-neondot.c",
    "src/qc8-gemm/gen/4x8c4-minmax-fp32-neondot.c",
    "src/qc8-gemm/gen/4x16c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/1x8c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/1x16c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/4x8c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/4x16c4-minmax-fp32-neondot.c",
    "src/qs8-gemm/gen/1x8c4-minmax-rndnu-neondot.c",
    "src/qs8-gemm/gen/1x16c4-minmax-rndnu-neondot.c",
    "src/qs8-gemm/gen/4x8c4-minmax-rndnu-neondot.c",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/1x8c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/1x16c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/1x8c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/1x16c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/4x8c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/4x16c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/1x8c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/1x16c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/4x8c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/4x16c4-minmax-rndnu-neondot.c",
]

ALL_NEONDOT_MICROKERNEL_SRCS = [
    "src/qc8-gemm/gen/1x8c4-minmax-fp32-neondot.c",
    "src/qc8-gemm/gen/1x16c4-minmax-fp32-neondot.c",
    "src/qc8-gemm/gen/4x8c4-minmax-fp32-neondot.c",
    "src/qc8-gemm/gen/4x16c4-minmax-fp32-neondot.c",
    "src/qc8-gemm/gen/6x8c4-minmax-fp32-neondot.c",
    "src/qc8-gemm/gen/6x16c4-minmax-fp32-neondot.c",
    "src/qc8-gemm/gen/8x8c4-minmax-fp32-neondot.c",
    "src/qc8-gemm/gen/8x16c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/1x8c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/1x16c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/4x8c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/4x16c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/6x8c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/6x16c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/8x8c4-minmax-fp32-neondot.c",
    "src/qc8-igemm/gen/8x16c4-minmax-fp32-neondot.c",
    "src/qs8-gemm/gen/1x8c4-minmax-fp32-neondot.c",
    "src/qs8-gemm/gen/1x8c4-minmax-rndnu-neondot.c",
    "src/qs8-gemm/gen/1x16c4-minmax-rndnu-neondot.c",
    "src/qs8-gemm/gen/4x8c4-minmax-rndnu-neondot.c",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-neondot.c",
    "src/qs8-gemm/gen/6x8c4-minmax-rndnu-neondot.c",
    "src/qs8-gemm/gen/6x16c4-minmax-rndnu-neondot.c",
    "src/qs8-gemm/gen/8x8c4-minmax-rndnu-neondot.c",
    "src/qs8-gemm/gen/8x16c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/1x8c4-minmax-fp32-neondot.c",
    "src/qs8-igemm/gen/1x8c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/1x16c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/4x8c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/4x16c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/6x8c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/6x16c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/8x8c4-minmax-rndnu-neondot.c",
    "src/qs8-igemm/gen/8x16c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/1x8c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/1x16c4-minmax-fp32-neondot.c",
    "src/qu8-gemm/gen/1x16c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/1x32c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/2x8c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/2x16c4-minmax-fp32-neondot.c",
    "src/qu8-gemm/gen/2x16c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/2x32c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/3x8c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/3x16c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/3x32c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/4x8c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/4x16c4-minmax-fp32-neondot.c",
    "src/qu8-gemm/gen/4x16c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/5x8c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/5x16c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/6x8c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/6x16c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/8x8c4-minmax-rndnu-neondot.c",
    "src/qu8-gemm/gen/8x16c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/1x8c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/1x16c4-minmax-fp32-neondot.c",
    "src/qu8-igemm/gen/1x16c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/1x32c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/2x8c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/2x16c4-minmax-fp32-neondot.c",
    "src/qu8-igemm/gen/2x16c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/2x32c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/3x8c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/3x16c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/3x32c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/4x8c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/4x16c4-minmax-fp32-neondot.c",
    "src/qu8-igemm/gen/4x16c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/5x8c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/5x16c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/6x8c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/6x16c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/8x8c4-minmax-rndnu-neondot.c",
    "src/qu8-igemm/gen/8x16c4-minmax-rndnu-neondot.c",
]

PROD_SSE_MICROKERNEL_SRCS = [
    "src/f32-avgpool/9p8x-minmax-sse-c4.c",
    "src/f32-avgpool/9x-minmax-sse-c4.c",
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-sse-2x2.c",
    "src/f32-dwconv/gen/up8x3-minmax-sse.c",
    "src/f32-dwconv/gen/up8x4-minmax-sse.c",
    "src/f32-dwconv/gen/up8x9-minmax-sse.c",
    "src/f32-dwconv/gen/up8x25-minmax-sse.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-2x4.c",
    "src/f32-gavgpool-cw/sse-x4.c",
    "src/f32-gavgpool/7p7x-minmax-sse-c4.c",
    "src/f32-gavgpool/7x-minmax-sse-c4.c",
    "src/f32-gemm/gen/1x8-minmax-sse-load1.c",
    "src/f32-gemm/gen/4x2c4-minmax-sse.c",
    "src/f32-gemm/gen/4x8-minmax-sse-load1.c",
    "src/f32-ibilinear-chw/gen/sse-p8.c",
    "src/f32-ibilinear/gen/sse-c8.c",
    "src/f32-igemm/gen/1x8-minmax-sse-load1.c",
    "src/f32-igemm/gen/4x2c4-minmax-sse.c",
    "src/f32-igemm/gen/4x8-minmax-sse-load1.c",
    "src/f32-maxpool/9p8x-minmax-sse-c4.c",
    "src/f32-pavgpool/9p8x-minmax-sse-c4.c",
    "src/f32-pavgpool/9x-minmax-sse-c4.c",
    "src/f32-rmax/sse.c",
    "src/f32-spmm/gen/32x1-minmax-sse.c",
    "src/f32-vbinary/gen/vadd-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vdiv-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vdivc-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vmax-sse-x8.c",
    "src/f32-vbinary/gen/vmaxc-sse-x8.c",
    "src/f32-vbinary/gen/vmin-sse-x8.c",
    "src/f32-vbinary/gen/vminc-sse-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vrsubc-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vsqrdiff-sse-x8.c",
    "src/f32-vbinary/gen/vsqrdiffc-sse-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-sse-x8.c",
    "src/f32-vclamp/gen/vclamp-sse-x8.c",
    "src/f32-vhswish/gen/vhswish-sse-x8.c",
    "src/f32-vlrelu/gen/vlrelu-sse-x8.c",
    "src/f32-vmulcaddc/gen/c4-minmax-sse-2x.c",
    "src/f32-vsqrt/gen/sse-sqrt-x4.c",
    "src/f32-vunary/gen/vabs-sse-x8.c",
    "src/f32-vunary/gen/vneg-sse-x8.c",
    "src/f32-vunary/gen/vsqr-sse-x8.c",
    "src/x32-packx/x4-sse.c",
    "src/x32-transposec/4x4-sse.c",
]

ALL_SSE_MICROKERNEL_SRCS = [
    "src/f32-avgpool/9p8x-minmax-sse-c4.c",
    "src/f32-avgpool/9x-minmax-sse-c4.c",
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-sse-1x1.c",
    "src/f32-conv-hwc2chw/3x3s2p1c3x4-sse-2x2.c",
    "src/f32-dwconv/gen/up4x3-minmax-sse-acc2.c",
    "src/f32-dwconv/gen/up4x3-minmax-sse.c",
    "src/f32-dwconv/gen/up4x4-minmax-sse-acc2.c",
    "src/f32-dwconv/gen/up4x4-minmax-sse.c",
    "src/f32-dwconv/gen/up4x9-minmax-sse-acc2.c",
    "src/f32-dwconv/gen/up4x9-minmax-sse.c",
    "src/f32-dwconv/gen/up4x25-minmax-sse-acc2.c",
    "src/f32-dwconv/gen/up4x25-minmax-sse.c",
    "src/f32-dwconv/gen/up8x3-minmax-sse-acc2.c",
    "src/f32-dwconv/gen/up8x3-minmax-sse.c",
    "src/f32-dwconv/gen/up8x4-minmax-sse-acc2.c",
    "src/f32-dwconv/gen/up8x4-minmax-sse.c",
    "src/f32-dwconv/gen/up8x9-minmax-sse-acc2.c",
    "src/f32-dwconv/gen/up8x9-minmax-sse.c",
    "src/f32-dwconv/gen/up8x25-minmax-sse-acc2.c",
    "src/f32-dwconv/gen/up8x25-minmax-sse.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-4x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-5x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-sse-6x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3s2p1-minmax-sse-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-3x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-4x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-4x4.c",
    "src/f32-dwconv2d-chw/gen/5x5p2-minmax-sse-5x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-1x4-acc5.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-1x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-2x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-2x4.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-3x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/5x5s2p2-minmax-sse-3x4.c",
    "src/f32-gavgpool-cw/sse-x4.c",
    "src/f32-gavgpool/7p7x-minmax-sse-c4.c",
    "src/f32-gavgpool/7x-minmax-sse-c4.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-sse-dup.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-sse-load1.c",
    "src/f32-gemm/gen-inc/1x8s4inc-minmax-sse.c",
    "src/f32-gemm/gen-inc/3x8inc-minmax-sse-dup.c",
    "src/f32-gemm/gen-inc/3x8inc-minmax-sse-load1.c",
    "src/f32-gemm/gen-inc/3x8s4inc-minmax-sse.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-sse-dup.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-sse-load1.c",
    "src/f32-gemm/gen-inc/4x8s4inc-minmax-sse.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-sse-dup.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-sse-load1.c",
    "src/f32-gemm/gen-inc/5x8s4inc-minmax-sse.c",
    "src/f32-gemm/gen/1x8-minmax-sse-dup.c",
    "src/f32-gemm/gen/1x8-minmax-sse-load1.c",
    "src/f32-gemm/gen/1x8s4-minmax-sse.c",
    "src/f32-gemm/gen/3x8-minmax-sse-dup.c",
    "src/f32-gemm/gen/3x8-minmax-sse-load1.c",
    "src/f32-gemm/gen/3x8s4-minmax-sse.c",
    "src/f32-gemm/gen/4x2c4-minmax-sse.c",
    "src/f32-gemm/gen/4x8-minmax-sse-dup.c",
    "src/f32-gemm/gen/4x8-minmax-sse-load1.c",
    "src/f32-gemm/gen/4x8s4-minmax-sse.c",
    "src/f32-gemm/gen/5x8-minmax-sse-dup.c",
    "src/f32-gemm/gen/5x8-minmax-sse-load1.c",
    "src/f32-gemm/gen/5x8s4-minmax-sse.c",
    "src/f32-ibilinear-chw/gen/sse-p4.c",
    "src/f32-ibilinear-chw/gen/sse-p8.c",
    "src/f32-ibilinear/gen/sse-c4.c",
    "src/f32-ibilinear/gen/sse-c8.c",
    "src/f32-igemm/gen/1x8-minmax-sse-dup.c",
    "src/f32-igemm/gen/1x8-minmax-sse-load1.c",
    "src/f32-igemm/gen/1x8s4-minmax-sse.c",
    "src/f32-igemm/gen/3x8-minmax-sse-dup.c",
    "src/f32-igemm/gen/3x8-minmax-sse-load1.c",
    "src/f32-igemm/gen/3x8s4-minmax-sse.c",
    "src/f32-igemm/gen/4x2c4-minmax-sse.c",
    "src/f32-igemm/gen/4x8-minmax-sse-dup.c",
    "src/f32-igemm/gen/4x8-minmax-sse-load1.c",
    "src/f32-igemm/gen/4x8s4-minmax-sse.c",
    "src/f32-igemm/gen/5x8-minmax-sse-dup.c",
    "src/f32-igemm/gen/5x8-minmax-sse-load1.c",
    "src/f32-igemm/gen/5x8s4-minmax-sse.c",
    "src/f32-maxpool/9p8x-minmax-sse-c4.c",
    "src/f32-pavgpool/9p8x-minmax-sse-c4.c",
    "src/f32-pavgpool/9x-minmax-sse-c4.c",
    "src/f32-ppmm/gen/4x8-minmax-sse.c",
    "src/f32-prelu/gen/sse-2x4.c",
    "src/f32-prelu/gen/sse-2x8.c",
    "src/f32-rmax/sse.c",
    "src/f32-spmm/gen/4x1-minmax-sse.c",
    "src/f32-spmm/gen/8x1-minmax-sse.c",
    "src/f32-spmm/gen/16x1-minmax-sse.c",
    "src/f32-spmm/gen/32x1-minmax-sse.c",
    "src/f32-vbinary/gen/vadd-minmax-sse-x4.c",
    "src/f32-vbinary/gen/vadd-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-sse-x4.c",
    "src/f32-vbinary/gen/vaddc-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vdiv-minmax-sse-x4.c",
    "src/f32-vbinary/gen/vdiv-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vdivc-minmax-sse-x4.c",
    "src/f32-vbinary/gen/vdivc-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vmax-sse-x4.c",
    "src/f32-vbinary/gen/vmax-sse-x8.c",
    "src/f32-vbinary/gen/vmaxc-sse-x4.c",
    "src/f32-vbinary/gen/vmaxc-sse-x8.c",
    "src/f32-vbinary/gen/vmin-sse-x4.c",
    "src/f32-vbinary/gen/vmin-sse-x8.c",
    "src/f32-vbinary/gen/vminc-sse-x4.c",
    "src/f32-vbinary/gen/vminc-sse-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-sse-x4.c",
    "src/f32-vbinary/gen/vmul-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-sse-x4.c",
    "src/f32-vbinary/gen/vmulc-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-sse-x4.c",
    "src/f32-vbinary/gen/vrdivc-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vrsubc-minmax-sse-x4.c",
    "src/f32-vbinary/gen/vrsubc-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vsqrdiff-sse-x4.c",
    "src/f32-vbinary/gen/vsqrdiff-sse-x8.c",
    "src/f32-vbinary/gen/vsqrdiffc-sse-x4.c",
    "src/f32-vbinary/gen/vsqrdiffc-sse-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-sse-x4.c",
    "src/f32-vbinary/gen/vsub-minmax-sse-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-sse-x4.c",
    "src/f32-vbinary/gen/vsubc-minmax-sse-x8.c",
    "src/f32-vclamp/gen/vclamp-sse-x4.c",
    "src/f32-vclamp/gen/vclamp-sse-x8.c",
    "src/f32-vhswish/gen/vhswish-sse-x4.c",
    "src/f32-vhswish/gen/vhswish-sse-x8.c",
    "src/f32-vlrelu/gen/vlrelu-sse-x4.c",
    "src/f32-vlrelu/gen/vlrelu-sse-x8.c",
    "src/f32-vmulcaddc/gen/c4-minmax-sse-2x.c",
    "src/f32-vmulcaddc/gen/c8-minmax-sse-2x.c",
    "src/f32-vrelu/gen/vrelu-sse-x4.c",
    "src/f32-vrelu/gen/vrelu-sse-x8.c",
    "src/f32-vsqrt/gen/sse-sqrt-x4.c",
    "src/f32-vsqrt/gen/sse-sqrt-x8.c",
    "src/f32-vunary/gen/vabs-sse-x4.c",
    "src/f32-vunary/gen/vabs-sse-x8.c",
    "src/f32-vunary/gen/vneg-sse-x4.c",
    "src/f32-vunary/gen/vneg-sse-x8.c",
    "src/f32-vunary/gen/vsqr-sse-x4.c",
    "src/f32-vunary/gen/vsqr-sse-x8.c",
    "src/math/roundd-sse-addsub.c",
    "src/math/roundne-sse-addsub.c",
    "src/math/roundu-sse-addsub.c",
    "src/math/roundz-sse-addsub.c",
    "src/math/sqrt-sse-hh1mac.c",
    "src/math/sqrt-sse-nr1mac.c",
    "src/math/sqrt-sse-nr2mac.c",
    "src/x32-packx/x4-sse.c",
    "src/x32-transposec/4x4-sse.c",
]

PROD_SSE2_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-sse2-int16-x32.c",
    "src/f16-vunary/gen/vabs-sse2-x16.c",
    "src/f16-vunary/gen/vneg-sse2-x16.c",
    "src/f32-argmaxpool/4x-sse2-c4.c",
    "src/f32-argmaxpool/9p8x-sse2-c4.c",
    "src/f32-argmaxpool/9x-sse2-c4.c",
    "src/f32-f16-vcvt/gen/vcvt-sse2-x16.c",
    "src/f32-prelu/gen/sse2-2x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-sse2-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-sse2-x32.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x20-acc2.c",
    "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x12.c",
    "src/f32-vlrelu/gen/vlrelu-sse2-x8.c",
    "src/f32-vrnd/gen/vrndd-sse2-x8.c",
    "src/f32-vrnd/gen/vrndne-sse2-x8.c",
    "src/f32-vrnd/gen/vrndu-sse2-x8.c",
    "src/f32-vrnd/gen/vrndz-sse2-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x8.c",
    "src/qc8-dwconv/gen/up8x3-minmax-fp32-sse2-mul16.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16-add16.c",
    "src/qs8-f32-vcvt/gen/vcvt-sse2-x32.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse2-c8.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-sse2-c8.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
    "src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x8.c",
    "src/qs8-vcvt/gen/vcvt-sse2-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-sse2-x32.c",
    "src/qs8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
    "src/qs8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
    "src/qu8-avgpool/9p8x-minmax-sse2-c8.c",
    "src/qu8-avgpool/9x-minmax-sse2-c8.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
    "src/qu8-f32-vcvt/gen/vcvt-sse2-x32.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse2-c8.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-sse2-c8.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qu8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
    "src/qu8-vaddc/gen/minmax-sse2-mul16-ld64-x8.c",
    "src/qu8-vcvt/gen/vcvt-sse2-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-sse2-x32.c",
    "src/qu8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
    "src/qu8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
    "src/s8-ibilinear/gen/sse2-c8.c",
    "src/s8-maxpool/9p8x-minmax-sse2-c16.c",
    "src/s8-vclamp/sse2-x64.c",
    "src/u8-ibilinear/gen/sse2-c8.c",
    "src/u8-maxpool/9p8x-minmax-sse2-c16.c",
    "src/u8-rmax/sse2.c",
    "src/u8-vclamp/sse2-x64.c",
    "src/xx-fill/sse2-x64.c",
    "src/xx-pad/sse2.c",
    "src/x8-transposec/gen/16x16-reuse-mov-sse2.c",
    "src/x8-zip/xm-sse2.c",
    "src/x8-zip/x2-sse2.c",
    "src/x8-zip/x3-sse2.c",
    "src/x8-zip/x4-sse2.c",
    "src/x16-transposec/gen/8x8-reuse-multi-sse2.c",
    "src/x32-unpool/sse2.c",
    "src/x32-zip/xm-sse2.c",
    "src/x32-zip/x2-sse2.c",
    "src/x32-zip/x3-sse2.c",
    "src/x32-zip/x4-sse2.c",
]

ALL_SSE2_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-sse2-int16-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-sse2-int16-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-sse2-int16-x24.c",
    "src/f16-f32-vcvt/gen/vcvt-sse2-int16-x32.c",
    "src/f16-f32-vcvt/gen/vcvt-sse2-int32-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-sse2-int32-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-sse2-int32-x24.c",
    "src/f16-f32-vcvt/gen/vcvt-sse2-int32-x32.c",
    "src/f16-vunary/gen/vabs-sse2-x8.c",
    "src/f16-vunary/gen/vabs-sse2-x16.c",
    "src/f16-vunary/gen/vneg-sse2-x8.c",
    "src/f16-vunary/gen/vneg-sse2-x16.c",
    "src/f32-argmaxpool/4x-sse2-c4.c",
    "src/f32-argmaxpool/9p8x-sse2-c4.c",
    "src/f32-argmaxpool/9x-sse2-c4.c",
    "src/f32-f16-vcvt/gen/vcvt-sse2-x8.c",
    "src/f32-f16-vcvt/gen/vcvt-sse2-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-sse2-x24.c",
    "src/f32-f16-vcvt/gen/vcvt-sse2-x32.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-sse2-dup.c",
    "src/f32-gemm/gen-inc/3x8inc-minmax-sse2-dup.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-sse2-dup.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-sse2-dup.c",
    "src/f32-gemm/gen/1x8-minmax-sse2-dup.c",
    "src/f32-gemm/gen/3x8-minmax-sse2-dup.c",
    "src/f32-gemm/gen/4x8-minmax-sse2-dup.c",
    "src/f32-gemm/gen/5x8-minmax-sse2-dup.c",
    "src/f32-igemm/gen/1x8-minmax-sse2-dup.c",
    "src/f32-igemm/gen/3x8-minmax-sse2-dup.c",
    "src/f32-igemm/gen/4x8-minmax-sse2-dup.c",
    "src/f32-igemm/gen/5x8-minmax-sse2-dup.c",
    "src/f32-prelu/gen/sse2-2x4.c",
    "src/f32-prelu/gen/sse2-2x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-sse2-x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-sse2-x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-sse2-x24.c",
    "src/f32-qs8-vcvt/gen/vcvt-sse2-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-sse2-x8.c",
    "src/f32-qu8-vcvt/gen/vcvt-sse2-x16.c",
    "src/f32-qu8-vcvt/gen/vcvt-sse2-x24.c",
    "src/f32-qu8-vcvt/gen/vcvt-sse2-x32.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x4.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x8-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x8.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x12-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x12-acc3.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x12.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x16-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x16-acc4.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x16.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x20-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x20-acc5.c",
    "src/f32-raddstoreexpminusmax/gen/sse2-rr2-p5-x20.c",
    "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x4.c",
    "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x8.c",
    "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x12.c",
    "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x16.c",
    "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x20.c",
    "src/f32-velu/gen/velu-sse2-rr2-lut16-p3-x24.c",
    "src/f32-velu/gen/velu-sse2-rr2-p6-x4.c",
    "src/f32-velu/gen/velu-sse2-rr2-p6-x8.c",
    "src/f32-velu/gen/velu-sse2-rr2-p6-x12.c",
    "src/f32-velu/gen/velu-sse2-rr2-p6-x16.c",
    "src/f32-velu/gen/velu-sse2-rr2-p6-x20.c",
    "src/f32-velu/gen/velu-sse2-rr2-p6-x24.c",
    "src/f32-vlrelu/gen/vlrelu-sse2-x4.c",
    "src/f32-vlrelu/gen/vlrelu-sse2-x8.c",
    "src/f32-vrnd/gen/vrndd-sse2-x4.c",
    "src/f32-vrnd/gen/vrndd-sse2-x8.c",
    "src/f32-vrnd/gen/vrndne-sse2-x4.c",
    "src/f32-vrnd/gen/vrndne-sse2-x8.c",
    "src/f32-vrnd/gen/vrndu-sse2-x4.c",
    "src/f32-vrnd/gen/vrndu-sse2-x8.c",
    "src/f32-vrnd/gen/vrndz-sse2-x4.c",
    "src/f32-vrnd/gen/vrndz-sse2-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-lut64-p2-div-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse2-rr2-p5-div-x24.c",
    "src/math/cvt-f16-f32-sse2-int16.c",
    "src/math/cvt-f16-f32-sse2-int32.c",
    "src/math/cvt-f32-f16-sse2.c",
    "src/math/exp-f32-sse2-rr2-lut64-p2.c",
    "src/math/exp-f32-sse2-rr2-p5.c",
    "src/math/expminus-f32-sse2-rr2-p5.c",
    "src/math/expm1minus-f32-sse2-rr2-lut16-p3.c",
    "src/math/expm1minus-f32-sse2-rr2-p6.c",
    "src/math/roundd-sse2-cvt.c",
    "src/math/roundne-sse2-cvt.c",
    "src/math/roundu-sse2-cvt.c",
    "src/math/roundz-sse2-cvt.c",
    "src/math/sigmoid-f32-sse2-rr2-lut64-p2-div.c",
    "src/math/sigmoid-f32-sse2-rr2-lut64-p2-nr1.c",
    "src/math/sigmoid-f32-sse2-rr2-lut64-p2-nr2.c",
    "src/math/sigmoid-f32-sse2-rr2-p5-div.c",
    "src/math/sigmoid-f32-sse2-rr2-p5-nr1.c",
    "src/math/sigmoid-f32-sse2-rr2-p5-nr2.c",
    "src/qc8-dwconv/gen/up8x3-minmax-fp32-sse2-mul16.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16-add16.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16-add16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16.c",
    "src/qc8-dwconv/gen/up24x9-minmax-fp32-sse2-mul16.c",
    "src/qc8-dwconv/gen/up24x25-minmax-fp32-sse2-mul16.c",
    "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
    "src/qc8-gemm/gen/1x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/1x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
    "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
    "src/qc8-gemm/gen/2x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/2x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
    "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
    "src/qc8-gemm/gen/3x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/3x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
    "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
    "src/qc8-gemm/gen/4x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qc8-gemm/gen/4x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
    "src/qc8-igemm/gen/1x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/1x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
    "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
    "src/qc8-igemm/gen/2x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/2x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
    "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
    "src/qc8-igemm/gen/3x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/3x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
    "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
    "src/qc8-igemm/gen/4x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qc8-igemm/gen/4x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16.c",
    "src/qs8-dwconv/gen/up24x9-minmax-fp32-sse2-mul16.c",
    "src/qs8-dwconv/gen/up24x25-minmax-fp32-sse2-mul16.c",
    "src/qs8-f32-vcvt/gen/vcvt-sse2-x8.c",
    "src/qs8-f32-vcvt/gen/vcvt-sse2-x16.c",
    "src/qs8-f32-vcvt/gen/vcvt-sse2-x24.c",
    "src/qs8-f32-vcvt/gen/vcvt-sse2-x32.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse2-c8.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse2-c16.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse2-c24.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-sse2-c8.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-sse2-c16.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-sse2-c24.c",
    "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
    "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-sse2.c",
    "src/qs8-gemm/gen/1x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/1x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qs8-gemm/gen/1x4c2s4-xw-minmax-fp32-sse2.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
    "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-sse2.c",
    "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
    "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-sse2.c",
    "src/qs8-gemm/gen/2x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/2x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qs8-gemm/gen/2x4c2s4-xw-minmax-fp32-sse2.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
    "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-sse2.c",
    "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
    "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-sse2.c",
    "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qs8-gemm/gen/3x4c2s4-xw-minmax-fp32-sse2.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
    "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-sse2.c",
    "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
    "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-sse2.c",
    "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qs8-gemm/gen/4x4c2s4-xw-minmax-fp32-sse2.c",
    "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
    "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
    "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
    "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
    "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
    "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
    "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
    "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qs8-requantization/fp32-sse2.c",
    "src/qs8-requantization/gemmlowp-sse2.c",
    "src/qs8-requantization/rndna-sse2.c",
    "src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
    "src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x16.c",
    "src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x24.c",
    "src/qs8-vadd/gen/minmax-sse2-mul16-ld64-x32.c",
    "src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x8.c",
    "src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x16.c",
    "src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x24.c",
    "src/qs8-vaddc/gen/minmax-sse2-mul16-ld64-x32.c",
    "src/qs8-vcvt/gen/vcvt-sse2-x16.c",
    "src/qs8-vcvt/gen/vcvt-sse2-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-sse2-x16.c",
    "src/qs8-vlrelu/gen/vlrelu-sse2-x32.c",
    "src/qs8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
    "src/qs8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
    "src/qs8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
    "src/qs8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
    "src/qu8-avgpool/9p8x-minmax-sse2-c8.c",
    "src/qu8-avgpool/9x-minmax-sse2-c8.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse2-mul16.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse2-mul16.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-sse2-mul16.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-sse2-mul16.c",
    "src/qu8-f32-vcvt/gen/vcvt-sse2-x8.c",
    "src/qu8-f32-vcvt/gen/vcvt-sse2-x16.c",
    "src/qu8-f32-vcvt/gen/vcvt-sse2-x24.c",
    "src/qu8-f32-vcvt/gen/vcvt-sse2-x32.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse2-c8.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse2-c16.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse2-c24.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-sse2-c8.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-sse2-c16.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-sse2-c24.c",
    "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
    "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
    "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
    "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
    "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
    "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
    "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
    "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse2-ld128.c",
    "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse2-ld128.c",
    "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse2-ld128.c",
    "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse2-ld128.c",
    "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse2-ld128.c",
    "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse2-ld128.c",
    "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse2-ld128.c",
    "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-sse2-ld64.c",
    "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-sse2-ld128.c",
    "src/qu8-requantization/fp32-sse2.c",
    "src/qu8-requantization/gemmlowp-sse2.c",
    "src/qu8-requantization/rndna-sse2.c",
    "src/qu8-vadd/gen/minmax-sse2-mul16-ld64-x8.c",
    "src/qu8-vadd/gen/minmax-sse2-mul16-ld64-x16.c",
    "src/qu8-vaddc/gen/minmax-sse2-mul16-ld64-x8.c",
    "src/qu8-vaddc/gen/minmax-sse2-mul16-ld64-x16.c",
    "src/qu8-vcvt/gen/vcvt-sse2-x16.c",
    "src/qu8-vcvt/gen/vcvt-sse2-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-sse2-x16.c",
    "src/qu8-vlrelu/gen/vlrelu-sse2-x32.c",
    "src/qu8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
    "src/qu8-vmul/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
    "src/qu8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x8.c",
    "src/qu8-vmulc/gen/minmax-fp32-sse2-mul16-ld64-x16.c",
    "src/s8-ibilinear/gen/sse2-c8.c",
    "src/s8-ibilinear/gen/sse2-c16.c",
    "src/s8-maxpool/9p8x-minmax-sse2-c16.c",
    "src/s8-vclamp/sse2-x64.c",
    "src/u8-ibilinear/gen/sse2-c8.c",
    "src/u8-ibilinear/gen/sse2-c16.c",
    "src/u8-maxpool/9p8x-minmax-sse2-c16.c",
    "src/u8-rmax/sse2.c",
    "src/u8-vclamp/sse2-x64.c",
    "src/xx-fill/sse2-x64.c",
    "src/xx-pad/sse2.c",
    "src/x8-transposec/gen/16x16-reuse-mov-sse2.c",
    "src/x8-transposec/gen/16x16-reuse-switch-sse2.c",
    "src/x8-zip/xm-sse2.c",
    "src/x8-zip/x2-sse2.c",
    "src/x8-zip/x3-sse2.c",
    "src/x8-zip/x4-sse2.c",
    "src/x16-transposec/gen/8x8-multi-mov-sse2.c",
    "src/x16-transposec/gen/8x8-multi-switch-sse2.c",
    "src/x16-transposec/gen/8x8-reuse-mov-sse2.c",
    "src/x16-transposec/gen/8x8-reuse-multi-sse2.c",
    "src/x16-transposec/gen/8x8-reuse-switch-sse2.c",
    "src/x16-transposec/4x8-sse2.c",
    "src/x32-transposec/gen/4x4-multi-mov-sse2.c",
    "src/x32-transposec/gen/4x4-multi-multi-sse2.c",
    "src/x32-transposec/gen/4x4-multi-switch-sse2.c",
    "src/x32-transposec/gen/4x4-reuse-mov-sse2.c",
    "src/x32-transposec/gen/4x4-reuse-multi-sse2.c",
    "src/x32-transposec/gen/4x4-reuse-switch-sse2.c",
    "src/x32-unpool/sse2.c",
    "src/x32-zip/xm-sse2.c",
    "src/x32-zip/x2-sse2.c",
    "src/x32-zip/x3-sse2.c",
    "src/x32-zip/x4-sse2.c",
    "src/x64-transposec/gen/2x2-multi-mov-sse2.c",
    "src/x64-transposec/gen/2x2-multi-multi-sse2.c",
    "src/x64-transposec/gen/2x2-multi-switch-sse2.c",
    "src/x64-transposec/gen/2x2-reuse-mov-sse2.c",
    "src/x64-transposec/gen/2x2-reuse-multi-sse2.c",
    "src/x64-transposec/gen/2x2-reuse-switch-sse2.c",
]

PROD_SSSE3_MICROKERNEL_SRCS = [
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-2x4-acc2.c",
    "src/qs8-vcvt/gen/vcvt-ssse3-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-ssse3-x32.c",
    "src/qu8-vcvt/gen/vcvt-ssse3-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-ssse3-x32.c",
]

ALL_SSSE3_MICROKERNEL_SRCS = [
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-1x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-1x4-acc3.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-1x4-acc4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-1x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-2x4-acc2.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-2x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-3x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-4x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-5x4.c",
    "src/f32-dwconv2d-chw/gen/3x3p1-minmax-ssse3-6x4.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-ssse3-ld64.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-ssse3-ld128.c",
    "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-ssse3.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-ssse3-ld64.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-ssse3-ld128.c",
    "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-ssse3.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-ssse3-ld64.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-ssse3-ld128.c",
    "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-ssse3.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-ssse3-ld64.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-ssse3-ld128.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-ssse3-ld64.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-ssse3-ld128.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-ssse3-ld64.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-ssse3-ld128.c",
    "src/qs8-requantization/gemmlowp-ssse3.c",
    "src/qs8-requantization/rndna-ssse3.c",
    "src/qs8-vcvt/gen/vcvt-ssse3-x16.c",
    "src/qs8-vcvt/gen/vcvt-ssse3-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-ssse3-x16.c",
    "src/qs8-vlrelu/gen/vlrelu-ssse3-x32.c",
    "src/qu8-requantization/gemmlowp-ssse3.c",
    "src/qu8-requantization/rndna-ssse3.c",
    "src/qu8-vcvt/gen/vcvt-ssse3-x16.c",
    "src/qu8-vcvt/gen/vcvt-ssse3-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-ssse3-x16.c",
    "src/qu8-vlrelu/gen/vlrelu-ssse3-x32.c",
    "src/x8-lut/gen/lut-ssse3-x16.c",
    "src/x8-lut/gen/lut-ssse3-x32.c",
    "src/x24-transposec/4x4-ssse3.c",
]

PROD_SSE41_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-sse41-int16-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-sse41-x8.c",
    "src/f32-prelu/gen/sse41-2x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-sse41-x32.c",
    "src/f32-vlrelu/gen/vlrelu-sse41-x8.c",
    "src/f32-vrnd/gen/vrndd-sse41-x8.c",
    "src/f32-vrnd/gen/vrndne-sse41-x8.c",
    "src/f32-vrnd/gen/vrndu-sse41-x8.c",
    "src/f32-vrnd/gen/vrndz-sse41-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x8.c",
    "src/qc8-dwconv/gen/up8x3-minmax-fp32-sse41-mul16.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16-add16.c",
    "src/qs8-f32-vcvt/gen/vcvt-sse41-x16.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse41-c8.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-sse41-c8.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
    "src/qs8-vaddc/gen/minmax-sse41-mul16-ld64-x8.c",
    "src/qs8-vcvt/gen/vcvt-sse41-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-sse41-x32.c",
    "src/qs8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
    "src/qs8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
    "src/qu8-f32-vcvt/gen/vcvt-sse41-x16.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse41-c8.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-sse41-c8.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qu8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
    "src/qu8-vaddc/gen/minmax-sse41-mul16-ld64-x8.c",
    "src/qu8-vcvt/gen/vcvt-sse41-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-sse41-x32.c",
    "src/qu8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
    "src/qu8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
    "src/s8-ibilinear/gen/sse41-c16.c",
    "src/s8-maxpool/9p8x-minmax-sse41-c16.c",
    "src/s8-vclamp/sse41-x64.c",
    "src/u8-ibilinear/gen/sse41-c16.c",
]

ALL_SSE41_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-sse41-int16-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-sse41-int16-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-sse41-int16-x24.c",
    "src/f16-f32-vcvt/gen/vcvt-sse41-int16-x32.c",
    "src/f16-f32-vcvt/gen/vcvt-sse41-int32-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-sse41-int32-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-sse41-int32-x24.c",
    "src/f16-f32-vcvt/gen/vcvt-sse41-int32-x32.c",
    "src/f32-f16-vcvt/gen/vcvt-sse41-x8.c",
    "src/f32-f16-vcvt/gen/vcvt-sse41-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-sse41-x24.c",
    "src/f32-f16-vcvt/gen/vcvt-sse41-x32.c",
    "src/f32-prelu/gen/sse41-2x4.c",
    "src/f32-prelu/gen/sse41-2x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-sse41-x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-sse41-x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-sse41-x24.c",
    "src/f32-qs8-vcvt/gen/vcvt-sse41-x32.c",
    "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x4.c",
    "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x8.c",
    "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x12.c",
    "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x16.c",
    "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x20.c",
    "src/f32-velu/gen/velu-sse41-rr2-lut16-p3-x24.c",
    "src/f32-velu/gen/velu-sse41-rr2-p6-x4.c",
    "src/f32-velu/gen/velu-sse41-rr2-p6-x8.c",
    "src/f32-velu/gen/velu-sse41-rr2-p6-x12.c",
    "src/f32-velu/gen/velu-sse41-rr2-p6-x16.c",
    "src/f32-velu/gen/velu-sse41-rr2-p6-x20.c",
    "src/f32-velu/gen/velu-sse41-rr2-p6-x24.c",
    "src/f32-vlrelu/gen/vlrelu-sse41-x4.c",
    "src/f32-vlrelu/gen/vlrelu-sse41-x8.c",
    "src/f32-vrnd/gen/vrndd-sse41-x4.c",
    "src/f32-vrnd/gen/vrndd-sse41-x8.c",
    "src/f32-vrnd/gen/vrndne-sse41-x4.c",
    "src/f32-vrnd/gen/vrndne-sse41-x8.c",
    "src/f32-vrnd/gen/vrndu-sse41-x4.c",
    "src/f32-vrnd/gen/vrndu-sse41-x8.c",
    "src/f32-vrnd/gen/vrndz-sse41-x4.c",
    "src/f32-vrnd/gen/vrndz-sse41-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-lut64-p2-div-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x4.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x12.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x20.c",
    "src/f32-vsigmoid/gen/vsigmoid-sse41-rr2-p5-div-x24.c",
    "src/math/cvt-f16-f32-sse41-int16.c",
    "src/math/cvt-f16-f32-sse41-int32.c",
    "src/math/cvt-f32-f16-sse41.c",
    "src/math/roundd-sse41.c",
    "src/math/roundne-sse41.c",
    "src/math/roundu-sse41.c",
    "src/math/roundz-sse41.c",
    "src/qc8-dwconv/gen/up8x3-minmax-fp32-sse41-mul16.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16-add16.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-sse41-mul32.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16-add16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-sse41-mul32.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-sse41-mul32.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-sse41-mul32.c",
    "src/qc8-dwconv/gen/up24x9-minmax-fp32-sse41-mul16.c",
    "src/qc8-dwconv/gen/up24x9-minmax-fp32-sse41-mul32.c",
    "src/qc8-dwconv/gen/up24x25-minmax-fp32-sse41-mul16.c",
    "src/qc8-dwconv/gen/up24x25-minmax-fp32-sse41-mul32.c",
    "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
    "src/qc8-gemm/gen/1x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/1x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
    "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
    "src/qc8-gemm/gen/2x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/2x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
    "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
    "src/qc8-gemm/gen/3x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/3x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
    "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
    "src/qc8-gemm/gen/4x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qc8-gemm/gen/4x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
    "src/qc8-igemm/gen/1x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/1x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
    "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
    "src/qc8-igemm/gen/2x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/2x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
    "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
    "src/qc8-igemm/gen/3x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/3x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
    "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
    "src/qc8-igemm/gen/4x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qc8-igemm/gen/4x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-sse41-mul32.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-sse41-mul32.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-sse41-mul32.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-sse41-mul32.c",
    "src/qs8-dwconv/gen/up24x9-minmax-fp32-sse41-mul16.c",
    "src/qs8-dwconv/gen/up24x9-minmax-fp32-sse41-mul32.c",
    "src/qs8-dwconv/gen/up24x25-minmax-fp32-sse41-mul16.c",
    "src/qs8-dwconv/gen/up24x25-minmax-fp32-sse41-mul32.c",
    "src/qs8-f32-vcvt/gen/vcvt-sse41-x8.c",
    "src/qs8-f32-vcvt/gen/vcvt-sse41-x16.c",
    "src/qs8-f32-vcvt/gen/vcvt-sse41-x24.c",
    "src/qs8-f32-vcvt/gen/vcvt-sse41-x32.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse41-c8.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse41-c16.c",
    "src/qs8-gavgpool/gen/7p7x-minmax-fp32-sse41-c24.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-sse41-c8.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-sse41-c16.c",
    "src/qs8-gavgpool/gen/7x-minmax-fp32-sse41-c24.c",
    "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
    "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-sse41.c",
    "src/qs8-gemm/gen/1x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/1x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qs8-gemm/gen/1x4c2s4-xw-minmax-fp32-sse41.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
    "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-sse41.c",
    "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
    "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-sse41.c",
    "src/qs8-gemm/gen/2x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/2x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qs8-gemm/gen/2x4c2s4-xw-minmax-fp32-sse41.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
    "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-sse41.c",
    "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
    "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-sse41.c",
    "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qs8-gemm/gen/3x4c2s4-xw-minmax-fp32-sse41.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
    "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-sse41.c",
    "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
    "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-sse41.c",
    "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qs8-gemm/gen/4x4c2s4-xw-minmax-fp32-sse41.c",
    "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
    "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
    "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
    "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
    "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
    "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
    "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
    "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qs8-requantization/fp32-sse4.c",
    "src/qs8-requantization/gemmlowp-sse4.c",
    "src/qs8-requantization/rndna-sse4.c",
    "src/qs8-requantization/rndnu-sse4-sra.c",
    "src/qs8-requantization/rndnu-sse4-srl.c",
    "src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
    "src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x16.c",
    "src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x24.c",
    "src/qs8-vadd/gen/minmax-sse41-mul16-ld64-x32.c",
    "src/qs8-vadd/gen/minmax-sse41-mul32-ld32-x8.c",
    "src/qs8-vadd/gen/minmax-sse41-mul32-ld32-x16.c",
    "src/qs8-vadd/gen/minmax-sse41-mul32-ld32-x24.c",
    "src/qs8-vadd/gen/minmax-sse41-mul32-ld32-x32.c",
    "src/qs8-vaddc/gen/minmax-sse41-mul16-ld64-x8.c",
    "src/qs8-vaddc/gen/minmax-sse41-mul16-ld64-x16.c",
    "src/qs8-vaddc/gen/minmax-sse41-mul16-ld64-x24.c",
    "src/qs8-vaddc/gen/minmax-sse41-mul16-ld64-x32.c",
    "src/qs8-vaddc/gen/minmax-sse41-mul32-ld32-x8.c",
    "src/qs8-vaddc/gen/minmax-sse41-mul32-ld32-x16.c",
    "src/qs8-vaddc/gen/minmax-sse41-mul32-ld32-x24.c",
    "src/qs8-vaddc/gen/minmax-sse41-mul32-ld32-x32.c",
    "src/qs8-vcvt/gen/vcvt-sse41-x8.c",
    "src/qs8-vcvt/gen/vcvt-sse41-x16.c",
    "src/qs8-vcvt/gen/vcvt-sse41-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-sse41-x8.c",
    "src/qs8-vlrelu/gen/vlrelu-sse41-x16.c",
    "src/qs8-vlrelu/gen/vlrelu-sse41-x32.c",
    "src/qs8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
    "src/qs8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
    "src/qs8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
    "src/qs8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse41-mul16.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-sse41-mul32.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse41-mul16.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-sse41-mul32.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-sse41-mul16.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-sse41-mul32.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-sse41-mul16.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-sse41-mul32.c",
    "src/qu8-f32-vcvt/gen/vcvt-sse41-x8.c",
    "src/qu8-f32-vcvt/gen/vcvt-sse41-x16.c",
    "src/qu8-f32-vcvt/gen/vcvt-sse41-x24.c",
    "src/qu8-f32-vcvt/gen/vcvt-sse41-x32.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse41-c8.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse41-c16.c",
    "src/qu8-gavgpool/gen/7p7x-minmax-fp32-sse41-c24.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-sse41-c8.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-sse41-c16.c",
    "src/qu8-gavgpool/gen/7x-minmax-fp32-sse41-c24.c",
    "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
    "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
    "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
    "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
    "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
    "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
    "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
    "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/1x4c2-minmax-fp32-sse41-ld128.c",
    "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-sse41-ld128.c",
    "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/2x4c2-minmax-fp32-sse41-ld128.c",
    "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-sse41-ld128.c",
    "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/3x4c2-minmax-fp32-sse41-ld128.c",
    "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-sse41-ld128.c",
    "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/4x4c2-minmax-fp32-sse41-ld128.c",
    "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-sse41-ld64.c",
    "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-sse41-ld128.c",
    "src/qu8-requantization/gemmlowp-sse4.c",
    "src/qu8-requantization/rndna-sse4.c",
    "src/qu8-vadd/gen/minmax-sse41-mul16-ld64-x8.c",
    "src/qu8-vadd/gen/minmax-sse41-mul16-ld64-x16.c",
    "src/qu8-vadd/gen/minmax-sse41-mul32-ld32-x8.c",
    "src/qu8-vadd/gen/minmax-sse41-mul32-ld32-x16.c",
    "src/qu8-vaddc/gen/minmax-sse41-mul16-ld64-x8.c",
    "src/qu8-vaddc/gen/minmax-sse41-mul16-ld64-x16.c",
    "src/qu8-vaddc/gen/minmax-sse41-mul32-ld32-x8.c",
    "src/qu8-vaddc/gen/minmax-sse41-mul32-ld32-x16.c",
    "src/qu8-vcvt/gen/vcvt-sse41-x8.c",
    "src/qu8-vcvt/gen/vcvt-sse41-x16.c",
    "src/qu8-vcvt/gen/vcvt-sse41-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-sse41-x8.c",
    "src/qu8-vlrelu/gen/vlrelu-sse41-x16.c",
    "src/qu8-vlrelu/gen/vlrelu-sse41-x32.c",
    "src/qu8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
    "src/qu8-vmul/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
    "src/qu8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x8.c",
    "src/qu8-vmulc/gen/minmax-fp32-sse41-mul16-ld64-x16.c",
    "src/s8-ibilinear/gen/sse41-c8.c",
    "src/s8-ibilinear/gen/sse41-c16.c",
    "src/s8-maxpool/9p8x-minmax-sse41-c16.c",
    "src/s8-vclamp/sse41-x64.c",
    "src/u8-ibilinear/gen/sse41-c8.c",
    "src/u8-ibilinear/gen/sse41-c16.c",
]

PROD_AVX_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-avx-int16-x16.c",
    "src/f32-dwconv/gen/up8x25-minmax-avx.c",
    "src/f32-dwconv/gen/up16x3-minmax-avx.c",
    "src/f32-dwconv/gen/up16x4-minmax-avx.c",
    "src/f32-dwconv/gen/up16x9-minmax-avx.c",
    "src/f32-f16-vcvt/gen/vcvt-avx-x24.c",
    "src/f32-gemm/gen/1x16-minmax-avx-broadcast.c",
    "src/f32-gemm/gen/5x16-minmax-avx-broadcast.c",
    "src/f32-igemm/gen/1x16-minmax-avx-broadcast.c",
    "src/f32-igemm/gen/5x16-minmax-avx-broadcast.c",
    "src/f32-prelu/gen/avx-2x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx-x32.c",
    "src/f32-vbinary/gen/vadd-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vaddc-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vdiv-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vdivc-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vmax-avx-x16.c",
    "src/f32-vbinary/gen/vmaxc-avx-x16.c",
    "src/f32-vbinary/gen/vmin-avx-x16.c",
    "src/f32-vbinary/gen/vminc-avx-x16.c",
    "src/f32-vbinary/gen/vmul-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vmulc-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vrdivc-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vrsubc-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vsqrdiff-avx-x16.c",
    "src/f32-vbinary/gen/vsqrdiffc-avx-x16.c",
    "src/f32-vbinary/gen/vsub-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vsubc-minmax-avx-x16.c",
    "src/f32-vclamp/gen/vclamp-avx-x16.c",
    "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x32.c",
    "src/f32-vhswish/gen/vhswish-avx-x16.c",
    "src/f32-vlrelu/gen/vlrelu-avx-x16.c",
    "src/f32-vrnd/gen/vrndd-avx-x16.c",
    "src/f32-vrnd/gen/vrndne-avx-x16.c",
    "src/f32-vrnd/gen/vrndu-avx-x16.c",
    "src/f32-vrnd/gen/vrndz-avx-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x40.c",
    "src/f32-vsqrt/gen/avx-sqrt-x8.c",
    "src/f32-vunary/gen/vabs-avx-x16.c",
    "src/f32-vunary/gen/vneg-avx-x16.c",
    "src/f32-vunary/gen/vsqr-avx-x16.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-avx-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx-x32.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
    "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
    "src/qs8-vcvt/gen/vcvt-avx-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-avx-x32.c",
    "src/qs8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
    "src/qs8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx-x32.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qu8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
    "src/qu8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
    "src/qu8-vcvt/gen/vcvt-avx-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-avx-x32.c",
    "src/qu8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
    "src/qu8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
    "src/x8-lut/gen/lut-avx-x64.c",
]

ALL_AVX_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-avx-int16-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-avx-int16-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-avx-int16-x24.c",
    "src/f16-f32-vcvt/gen/vcvt-avx-int16-x32.c",
    "src/f16-f32-vcvt/gen/vcvt-avx-int32-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-avx-int32-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-avx-int32-x24.c",
    "src/f16-f32-vcvt/gen/vcvt-avx-int32-x32.c",
    "src/f32-dwconv/gen/up8x3-minmax-avx-acc2.c",
    "src/f32-dwconv/gen/up8x3-minmax-avx.c",
    "src/f32-dwconv/gen/up8x4-minmax-avx-acc2.c",
    "src/f32-dwconv/gen/up8x4-minmax-avx.c",
    "src/f32-dwconv/gen/up8x9-minmax-avx-acc2.c",
    "src/f32-dwconv/gen/up8x9-minmax-avx.c",
    "src/f32-dwconv/gen/up8x25-minmax-avx-acc2.c",
    "src/f32-dwconv/gen/up8x25-minmax-avx.c",
    "src/f32-dwconv/gen/up16x3-minmax-avx-acc2.c",
    "src/f32-dwconv/gen/up16x3-minmax-avx.c",
    "src/f32-dwconv/gen/up16x4-minmax-avx-acc2.c",
    "src/f32-dwconv/gen/up16x4-minmax-avx.c",
    "src/f32-dwconv/gen/up16x9-minmax-avx-acc2.c",
    "src/f32-dwconv/gen/up16x9-minmax-avx.c",
    "src/f32-dwconv/gen/up16x25-minmax-avx-acc2.c",
    "src/f32-dwconv/gen/up16x25-minmax-avx.c",
    "src/f32-f16-vcvt/gen/vcvt-avx-x8.c",
    "src/f32-f16-vcvt/gen/vcvt-avx-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-avx-x24.c",
    "src/f32-f16-vcvt/gen/vcvt-avx-x32.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-avx-broadcast.c",
    "src/f32-gemm/gen-inc/1x16inc-minmax-avx-broadcast.c",
    "src/f32-gemm/gen-inc/3x16inc-minmax-avx-broadcast.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-avx-broadcast.c",
    "src/f32-gemm/gen-inc/4x16inc-minmax-avx-broadcast.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-avx-broadcast.c",
    "src/f32-gemm/gen-inc/5x16inc-minmax-avx-broadcast.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-avx-broadcast.c",
    "src/f32-gemm/gen-inc/7x8inc-minmax-avx-broadcast.c",
    "src/f32-gemm/gen/1x8-minmax-avx-broadcast.c",
    "src/f32-gemm/gen/1x16-minmax-avx-broadcast.c",
    "src/f32-gemm/gen/3x16-minmax-avx-broadcast.c",
    "src/f32-gemm/gen/4x8-minmax-avx-broadcast.c",
    "src/f32-gemm/gen/4x16-minmax-avx-broadcast.c",
    "src/f32-gemm/gen/5x8-minmax-avx-broadcast.c",
    "src/f32-gemm/gen/5x16-minmax-avx-broadcast.c",
    "src/f32-gemm/gen/6x8-minmax-avx-broadcast.c",
    "src/f32-gemm/gen/7x8-minmax-avx-broadcast.c",
    "src/f32-igemm/gen/1x8-minmax-avx-broadcast.c",
    "src/f32-igemm/gen/1x16-minmax-avx-broadcast.c",
    "src/f32-igemm/gen/3x16-minmax-avx-broadcast.c",
    "src/f32-igemm/gen/4x8-minmax-avx-broadcast.c",
    "src/f32-igemm/gen/4x16-minmax-avx-broadcast.c",
    "src/f32-igemm/gen/5x8-minmax-avx-broadcast.c",
    "src/f32-igemm/gen/5x16-minmax-avx-broadcast.c",
    "src/f32-igemm/gen/6x8-minmax-avx-broadcast.c",
    "src/f32-igemm/gen/7x8-minmax-avx-broadcast.c",
    "src/f32-prelu/gen/avx-2x8.c",
    "src/f32-prelu/gen/avx-2x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx-x8.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx-x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx-x24.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx-x8.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx-x16.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx-x24.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx-x32.c",
    "src/f32-rmax/avx.c",
    "src/f32-vbinary/gen/vadd-minmax-avx-x8.c",
    "src/f32-vbinary/gen/vadd-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vaddc-minmax-avx-x8.c",
    "src/f32-vbinary/gen/vaddc-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vdiv-minmax-avx-x8.c",
    "src/f32-vbinary/gen/vdiv-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vdivc-minmax-avx-x8.c",
    "src/f32-vbinary/gen/vdivc-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vmax-avx-x8.c",
    "src/f32-vbinary/gen/vmax-avx-x16.c",
    "src/f32-vbinary/gen/vmaxc-avx-x8.c",
    "src/f32-vbinary/gen/vmaxc-avx-x16.c",
    "src/f32-vbinary/gen/vmin-avx-x8.c",
    "src/f32-vbinary/gen/vmin-avx-x16.c",
    "src/f32-vbinary/gen/vminc-avx-x8.c",
    "src/f32-vbinary/gen/vminc-avx-x16.c",
    "src/f32-vbinary/gen/vmul-minmax-avx-x8.c",
    "src/f32-vbinary/gen/vmul-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vmulc-minmax-avx-x8.c",
    "src/f32-vbinary/gen/vmulc-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vrdivc-minmax-avx-x8.c",
    "src/f32-vbinary/gen/vrdivc-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vrsubc-minmax-avx-x8.c",
    "src/f32-vbinary/gen/vrsubc-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vsqrdiff-avx-x8.c",
    "src/f32-vbinary/gen/vsqrdiff-avx-x16.c",
    "src/f32-vbinary/gen/vsqrdiffc-avx-x8.c",
    "src/f32-vbinary/gen/vsqrdiffc-avx-x16.c",
    "src/f32-vbinary/gen/vsub-minmax-avx-x8.c",
    "src/f32-vbinary/gen/vsub-minmax-avx-x16.c",
    "src/f32-vbinary/gen/vsubc-minmax-avx-x8.c",
    "src/f32-vbinary/gen/vsubc-minmax-avx-x16.c",
    "src/f32-vclamp/gen/vclamp-avx-x8.c",
    "src/f32-vclamp/gen/vclamp-avx-x16.c",
    "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x8.c",
    "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x16.c",
    "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x24.c",
    "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x32.c",
    "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x40.c",
    "src/f32-velu/gen/velu-avx-rr2-lut4-p4-perm-x48.c",
    "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x8.c",
    "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x16.c",
    "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x24.c",
    "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x32.c",
    "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x40.c",
    "src/f32-velu/gen/velu-avx-rr2-lut16-p3-x48.c",
    "src/f32-velu/gen/velu-avx-rr2-p6-x8.c",
    "src/f32-velu/gen/velu-avx-rr2-p6-x16.c",
    "src/f32-velu/gen/velu-avx-rr2-p6-x24.c",
    "src/f32-velu/gen/velu-avx-rr2-p6-x32.c",
    "src/f32-velu/gen/velu-avx-rr2-p6-x40.c",
    "src/f32-velu/gen/velu-avx-rr2-p6-x48.c",
    "src/f32-vhswish/gen/vhswish-avx-x8.c",
    "src/f32-vhswish/gen/vhswish-avx-x16.c",
    "src/f32-vlrelu/gen/vlrelu-avx-x8.c",
    "src/f32-vlrelu/gen/vlrelu-avx-x16.c",
    "src/f32-vrelu/gen/vrelu-avx-x8.c",
    "src/f32-vrelu/gen/vrelu-avx-x16.c",
    "src/f32-vrnd/gen/vrndd-avx-x8.c",
    "src/f32-vrnd/gen/vrndd-avx-x16.c",
    "src/f32-vrnd/gen/vrndne-avx-x8.c",
    "src/f32-vrnd/gen/vrndne-avx-x16.c",
    "src/f32-vrnd/gen/vrndu-avx-x8.c",
    "src/f32-vrnd/gen/vrndu-avx-x16.c",
    "src/f32-vrnd/gen/vrndz-avx-x8.c",
    "src/f32-vrnd/gen/vrndz-avx-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x32.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x40.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x48.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x56.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x64.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x72.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-div-x80.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x32.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x40.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x48.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x56.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x64.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x72.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx-rr2-p5-nr2-x80.c",
    "src/f32-vsqrt/gen/avx-sqrt-x8.c",
    "src/f32-vsqrt/gen/avx-sqrt-x16.c",
    "src/f32-vunary/gen/vabs-avx-x8.c",
    "src/f32-vunary/gen/vabs-avx-x16.c",
    "src/f32-vunary/gen/vneg-avx-x8.c",
    "src/f32-vunary/gen/vneg-avx-x16.c",
    "src/f32-vunary/gen/vsqr-avx-x8.c",
    "src/f32-vunary/gen/vsqr-avx-x16.c",
    "src/math/exp-f32-avx-rr2-p5.c",
    "src/math/expm1minus-f32-avx-rr2-lut4-p4-perm.c",
    "src/math/expm1minus-f32-avx-rr2-lut16-p3.c",
    "src/math/expm1minus-f32-avx-rr2-p6.c",
    "src/math/sigmoid-f32-avx-rr2-lut64-p2-div.c",
    "src/math/sigmoid-f32-avx-rr2-p5-div.c",
    "src/math/sigmoid-f32-avx-rr2-p5-nr1.c",
    "src/math/sigmoid-f32-avx-rr2-p5-nr2.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx-mul16-add16.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx-mul16.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx-mul32.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx-mul16-add16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx-mul16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx-mul32.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-avx-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx-mul32.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx-mul32.c",
    "src/qc8-dwconv/gen/up24x9-minmax-fp32-avx-mul16.c",
    "src/qc8-dwconv/gen/up24x9-minmax-fp32-avx-mul32.c",
    "src/qc8-dwconv/gen/up24x25-minmax-fp32-avx-mul16.c",
    "src/qc8-dwconv/gen/up24x25-minmax-fp32-avx-mul32.c",
    "src/qc8-gemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
    "src/qc8-gemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
    "src/qc8-gemm/gen/1x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qc8-gemm/gen/1x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qc8-gemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
    "src/qc8-gemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
    "src/qc8-gemm/gen/2x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qc8-gemm/gen/2x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qc8-gemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
    "src/qc8-gemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
    "src/qc8-gemm/gen/3x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qc8-gemm/gen/3x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
    "src/qc8-gemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
    "src/qc8-gemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
    "src/qc8-gemm/gen/4x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qc8-gemm/gen/4x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
    "src/qc8-igemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/1x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qc8-igemm/gen/1x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
    "src/qc8-igemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/2x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qc8-igemm/gen/2x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
    "src/qc8-igemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/3x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qc8-igemm/gen/3x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
    "src/qc8-igemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
    "src/qc8-igemm/gen/4x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qc8-igemm/gen/4x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx-mul16.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx-mul32.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx-mul16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx-mul32.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx-mul32.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx-mul32.c",
    "src/qs8-dwconv/gen/up24x9-minmax-fp32-avx-mul16.c",
    "src/qs8-dwconv/gen/up24x9-minmax-fp32-avx-mul32.c",
    "src/qs8-dwconv/gen/up24x25-minmax-fp32-avx-mul16.c",
    "src/qs8-dwconv/gen/up24x25-minmax-fp32-avx-mul32.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx-x8.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx-x16.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx-x24.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx-x32.c",
    "src/qs8-gemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
    "src/qs8-gemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-avx.c",
    "src/qs8-gemm/gen/1x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qs8-gemm/gen/1x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/1x4c2s4-xw-minmax-fp32-avx.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-avx.c",
    "src/qs8-gemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
    "src/qs8-gemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-avx.c",
    "src/qs8-gemm/gen/2x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qs8-gemm/gen/2x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/2x4c2s4-xw-minmax-fp32-avx.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-avx.c",
    "src/qs8-gemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
    "src/qs8-gemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-avx.c",
    "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/3x4c2s4-xw-minmax-fp32-avx.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-avx.c",
    "src/qs8-gemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
    "src/qs8-gemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-avx.c",
    "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qs8-gemm/gen/4x4c2s4-xw-minmax-fp32-avx.c",
    "src/qs8-igemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
    "src/qs8-igemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
    "src/qs8-igemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
    "src/qs8-igemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
    "src/qs8-igemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
    "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x8.c",
    "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x16.c",
    "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x24.c",
    "src/qs8-vadd/gen/minmax-avx-mul16-ld64-x32.c",
    "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
    "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x16.c",
    "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x24.c",
    "src/qs8-vadd/gen/minmax-avx-mul32-ld32-x32.c",
    "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x8.c",
    "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x16.c",
    "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x24.c",
    "src/qs8-vaddc/gen/minmax-avx-mul16-ld64-x32.c",
    "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
    "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x16.c",
    "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x24.c",
    "src/qs8-vaddc/gen/minmax-avx-mul32-ld32-x32.c",
    "src/qs8-vcvt/gen/vcvt-avx-x8.c",
    "src/qs8-vcvt/gen/vcvt-avx-x16.c",
    "src/qs8-vcvt/gen/vcvt-avx-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-avx-x8.c",
    "src/qs8-vlrelu/gen/vlrelu-avx-x16.c",
    "src/qs8-vlrelu/gen/vlrelu-avx-x32.c",
    "src/qs8-vmul/gen/minmax-fp32-avx-mul16-ld64-x8.c",
    "src/qs8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
    "src/qs8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x8.c",
    "src/qs8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-avx-mul16.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-avx-mul32.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-avx-mul16.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-avx-mul32.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx-mul16.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx-mul32.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul16.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx-mul32.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx-x8.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx-x16.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx-x24.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx-x32.c",
    "src/qu8-gemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
    "src/qu8-gemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
    "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qu8-gemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
    "src/qu8-gemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
    "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qu8-gemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
    "src/qu8-gemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
    "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
    "src/qu8-gemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
    "src/qu8-gemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
    "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/1x4c2-minmax-fp32-avx-ld64.c",
    "src/qu8-igemm/gen/1x4c2-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-avx-ld64.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/2x4c2-minmax-fp32-avx-ld64.c",
    "src/qu8-igemm/gen/2x4c2-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-avx-ld64.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/3x4c2-minmax-fp32-avx-ld64.c",
    "src/qu8-igemm/gen/3x4c2-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-avx-ld64.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/4x4c2-minmax-fp32-avx-ld64.c",
    "src/qu8-igemm/gen/4x4c2-minmax-fp32-avx-ld128.c",
    "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-avx-ld64.c",
    "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-avx-ld128.c",
    "src/qu8-vadd/gen/minmax-avx-mul16-ld64-x8.c",
    "src/qu8-vadd/gen/minmax-avx-mul16-ld64-x16.c",
    "src/qu8-vadd/gen/minmax-avx-mul32-ld32-x8.c",
    "src/qu8-vadd/gen/minmax-avx-mul32-ld32-x16.c",
    "src/qu8-vaddc/gen/minmax-avx-mul16-ld64-x8.c",
    "src/qu8-vaddc/gen/minmax-avx-mul16-ld64-x16.c",
    "src/qu8-vaddc/gen/minmax-avx-mul32-ld32-x8.c",
    "src/qu8-vaddc/gen/minmax-avx-mul32-ld32-x16.c",
    "src/qu8-vcvt/gen/vcvt-avx-x8.c",
    "src/qu8-vcvt/gen/vcvt-avx-x16.c",
    "src/qu8-vcvt/gen/vcvt-avx-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-avx-x8.c",
    "src/qu8-vlrelu/gen/vlrelu-avx-x16.c",
    "src/qu8-vlrelu/gen/vlrelu-avx-x32.c",
    "src/qu8-vmul/gen/minmax-fp32-avx-mul16-ld64-x8.c",
    "src/qu8-vmul/gen/minmax-fp32-avx-mul16-ld64-x16.c",
    "src/qu8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x8.c",
    "src/qu8-vmulc/gen/minmax-fp32-avx-mul16-ld64-x16.c",
    "src/x8-lut/gen/lut-avx-x16.c",
    "src/x8-lut/gen/lut-avx-x32.c",
    "src/x8-lut/gen/lut-avx-x48.c",
    "src/x8-lut/gen/lut-avx-x64.c",
]

PROD_F16C_MICROKERNEL_SRCS = [
    "src/f16-avgpool/9p8x-minmax-f16c-c8.c",
    "src/f16-avgpool/9x-minmax-f16c-c8.c",
    "src/f16-f32-vcvt/gen/vcvt-f16c-x16.c",
    "src/f16-gavgpool/gen/7p7x-minmax-f16c-c8.c",
    "src/f16-gavgpool/gen/7x-minmax-f16c-c8.c",
    "src/f16-maxpool/9p8x-minmax-f16c-c8.c",
    "src/f16-prelu/gen/f16c-2x16.c",
    "src/f16-rmax/f16c.c",
    "src/f16-vbinary/gen/vadd-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vaddc-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vdiv-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vdivc-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vmax-f16c-x16.c",
    "src/f16-vbinary/gen/vmaxc-f16c-x16.c",
    "src/f16-vbinary/gen/vmin-f16c-x16.c",
    "src/f16-vbinary/gen/vminc-f16c-x16.c",
    "src/f16-vbinary/gen/vmul-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vmulc-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vrdivc-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vrsubc-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vsqrdiff-f16c-x16.c",
    "src/f16-vbinary/gen/vsqrdiffc-f16c-x16.c",
    "src/f16-vbinary/gen/vsub-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vsubc-minmax-f16c-x16.c",
    "src/f16-vclamp/gen/vclamp-f16c-x16.c",
    "src/f16-vhswish/gen/vhswish-f16c-x16.c",
    "src/f16-vlrelu/gen/vlrelu-f16c-x16.c",
    "src/f16-vrnd/gen/vrndd-f16c-x16.c",
    "src/f16-vrnd/gen/vrndne-f16c-x16.c",
    "src/f16-vrnd/gen/vrndu-f16c-x16.c",
    "src/f16-vrnd/gen/vrndz-f16c-x16.c",
    "src/f16-vsqrt/gen/f16c-sqrt-x8.c",
    "src/f16-vunary/gen/vsqr-f16c-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-f16c-x16.c",
]

ALL_F16C_MICROKERNEL_SRCS = [
    "src/f16-avgpool/9p8x-minmax-f16c-c8.c",
    "src/f16-avgpool/9x-minmax-f16c-c8.c",
    "src/f16-f32-vcvt/gen/vcvt-f16c-x8.c",
    "src/f16-f32-vcvt/gen/vcvt-f16c-x16.c",
    "src/f16-gavgpool/gen/7p7x-minmax-f16c-c8.c",
    "src/f16-gavgpool/gen/7p7x-minmax-f16c-c16.c",
    "src/f16-gavgpool/gen/7p7x-minmax-f16c-c24.c",
    "src/f16-gavgpool/gen/7p7x-minmax-f16c-c32.c",
    "src/f16-gavgpool/gen/7x-minmax-f16c-c8.c",
    "src/f16-gavgpool/gen/7x-minmax-f16c-c16.c",
    "src/f16-gavgpool/gen/7x-minmax-f16c-c24.c",
    "src/f16-gavgpool/gen/7x-minmax-f16c-c32.c",
    "src/f16-maxpool/9p8x-minmax-f16c-c8.c",
    "src/f16-prelu/gen/f16c-2x8.c",
    "src/f16-prelu/gen/f16c-2x16.c",
    "src/f16-rmax/f16c.c",
    "src/f16-vbinary/gen/vadd-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vadd-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vaddc-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vaddc-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vdiv-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vdiv-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vdivc-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vdivc-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vmax-f16c-x8.c",
    "src/f16-vbinary/gen/vmax-f16c-x16.c",
    "src/f16-vbinary/gen/vmaxc-f16c-x8.c",
    "src/f16-vbinary/gen/vmaxc-f16c-x16.c",
    "src/f16-vbinary/gen/vmin-f16c-x8.c",
    "src/f16-vbinary/gen/vmin-f16c-x16.c",
    "src/f16-vbinary/gen/vminc-f16c-x8.c",
    "src/f16-vbinary/gen/vminc-f16c-x16.c",
    "src/f16-vbinary/gen/vmul-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vmul-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vmulc-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vmulc-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vrdivc-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vrdivc-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vrsubc-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vrsubc-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vsqrdiff-f16c-x8.c",
    "src/f16-vbinary/gen/vsqrdiff-f16c-x16.c",
    "src/f16-vbinary/gen/vsqrdiffc-f16c-x8.c",
    "src/f16-vbinary/gen/vsqrdiffc-f16c-x16.c",
    "src/f16-vbinary/gen/vsub-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vsub-minmax-f16c-x16.c",
    "src/f16-vbinary/gen/vsubc-minmax-f16c-x8.c",
    "src/f16-vbinary/gen/vsubc-minmax-f16c-x16.c",
    "src/f16-vclamp/gen/vclamp-f16c-x8.c",
    "src/f16-vclamp/gen/vclamp-f16c-x16.c",
    "src/f16-vhswish/gen/vhswish-f16c-x8.c",
    "src/f16-vhswish/gen/vhswish-f16c-x16.c",
    "src/f16-vlrelu/gen/vlrelu-f16c-x8.c",
    "src/f16-vlrelu/gen/vlrelu-f16c-x16.c",
    "src/f16-vrnd/gen/vrndd-f16c-x8.c",
    "src/f16-vrnd/gen/vrndd-f16c-x16.c",
    "src/f16-vrnd/gen/vrndne-f16c-x8.c",
    "src/f16-vrnd/gen/vrndne-f16c-x16.c",
    "src/f16-vrnd/gen/vrndu-f16c-x8.c",
    "src/f16-vrnd/gen/vrndu-f16c-x16.c",
    "src/f16-vrnd/gen/vrndz-f16c-x8.c",
    "src/f16-vrnd/gen/vrndz-f16c-x16.c",
    "src/f16-vsqrt/gen/f16c-sqrt-x8.c",
    "src/f16-vsqrt/gen/f16c-sqrt-x16.c",
    "src/f16-vunary/gen/vsqr-f16c-x8.c",
    "src/f16-vunary/gen/vsqr-f16c-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-f16c-x8.c",
    "src/f32-f16-vcvt/gen/vcvt-f16c-x16.c",
    "src/math/cvt-f16-f32-f16c.c",
    "src/math/cvt-f32-f16-f16c.c",
]

PROD_XOP_MICROKERNEL_SRCS = [
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-xop-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qs8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
    "src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x8.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qu8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
    "src/qu8-vaddc/gen/minmax-xop-mul32-ld32-x8.c",
]

ALL_XOP_MICROKERNEL_SRCS = [
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-xop-mul16-add16.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-xop-mul32.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-xop-mul16-add16.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-xop-mul32.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-xop-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
    "src/qc8-dwconv/gen/up24x9-minmax-fp32-xop-mul32.c",
    "src/qc8-dwconv/gen/up24x25-minmax-fp32-xop-mul32.c",
    "src/qc8-gemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
    "src/qc8-gemm/gen/1x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/1x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
    "src/qc8-gemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
    "src/qc8-gemm/gen/2x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/2x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
    "src/qc8-gemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
    "src/qc8-gemm/gen/3x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/3x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
    "src/qc8-gemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
    "src/qc8-gemm/gen/4x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qc8-gemm/gen/4x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qc8-igemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
    "src/qc8-igemm/gen/1x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/1x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
    "src/qc8-igemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
    "src/qc8-igemm/gen/2x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/2x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
    "src/qc8-igemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
    "src/qc8-igemm/gen/3x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/3x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
    "src/qc8-igemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
    "src/qc8-igemm/gen/4x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qc8-igemm/gen/4x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-xop-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-xop-mul32.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-xop-mul16-add16.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-xop-mul32.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-xop-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-xop-mul16-add16.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
    "src/qs8-dwconv/gen/up24x9-minmax-fp32-xop-mul32.c",
    "src/qs8-dwconv/gen/up24x25-minmax-fp32-xop-mul32.c",
    "src/qs8-gemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
    "src/qs8-gemm/gen/1x4c2-xw-minmax-fp32-xop.c",
    "src/qs8-gemm/gen/1x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/1x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qs8-gemm/gen/1x4c2s4-xw-minmax-fp32-xop.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
    "src/qs8-gemm/gen/1x4c8-xw-minmax-fp32-xop.c",
    "src/qs8-gemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
    "src/qs8-gemm/gen/2x4c2-xw-minmax-fp32-xop.c",
    "src/qs8-gemm/gen/2x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/2x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qs8-gemm/gen/2x4c2s4-xw-minmax-fp32-xop.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
    "src/qs8-gemm/gen/2x4c8-xw-minmax-fp32-xop.c",
    "src/qs8-gemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
    "src/qs8-gemm/gen/3x4c2-xw-minmax-fp32-xop.c",
    "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/3x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qs8-gemm/gen/3x4c2s4-xw-minmax-fp32-xop.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
    "src/qs8-gemm/gen/3x4c8-xw-minmax-fp32-xop.c",
    "src/qs8-gemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
    "src/qs8-gemm/gen/4x4c2-xw-minmax-fp32-xop.c",
    "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qs8-gemm/gen/4x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qs8-gemm/gen/4x4c2s4-xw-minmax-fp32-xop.c",
    "src/qs8-igemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
    "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/1x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
    "src/qs8-igemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
    "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/2x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
    "src/qs8-igemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
    "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/3x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
    "src/qs8-igemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
    "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qs8-igemm/gen/4x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qs8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
    "src/qs8-vadd/gen/minmax-xop-mul32-ld32-x16.c",
    "src/qs8-vadd/gen/minmax-xop-mul32-ld32-x24.c",
    "src/qs8-vadd/gen/minmax-xop-mul32-ld32-x32.c",
    "src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x8.c",
    "src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x16.c",
    "src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x24.c",
    "src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x32.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-xop-mul32.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-xop-mul32.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-xop-mul32.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-xop-mul32.c",
    "src/qu8-gemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
    "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/1x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
    "src/qu8-gemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
    "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/2x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
    "src/qu8-gemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
    "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/3x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
    "src/qu8-gemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
    "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qu8-gemm/gen/4x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qu8-igemm/gen/1x4c2-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/1x4c2-minmax-fp32-xop-ld128.c",
    "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/1x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/1x4c8-minmax-fp32-xop-ld128.c",
    "src/qu8-igemm/gen/2x4c2-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/2x4c2-minmax-fp32-xop-ld128.c",
    "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/2x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/2x4c8-minmax-fp32-xop-ld128.c",
    "src/qu8-igemm/gen/3x4c2-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/3x4c2-minmax-fp32-xop-ld128.c",
    "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/3x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/3x4c8-minmax-fp32-xop-ld128.c",
    "src/qu8-igemm/gen/4x4c2-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/4x4c2-minmax-fp32-xop-ld128.c",
    "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-xop-ld64.c",
    "src/qu8-igemm/gen/4x4c2s4-minmax-fp32-xop-ld128.c",
    "src/qu8-vadd/gen/minmax-xop-mul32-ld32-x8.c",
    "src/qu8-vadd/gen/minmax-xop-mul32-ld32-x16.c",
    "src/qu8-vaddc/gen/minmax-xop-mul32-ld32-x8.c",
    "src/qu8-vaddc/gen/minmax-xop-mul32-ld32-x16.c",
]

PROD_FMA3_MICROKERNEL_SRCS = [
    "src/f16-dwconv/gen/up8x25-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up16x3-minmax-fma3.c",
    "src/f16-dwconv/gen/up16x4-minmax-fma3.c",
    "src/f16-dwconv/gen/up16x9-minmax-fma3.c",
    "src/f16-ibilinear/gen/fma3-c8.c",
    "src/f16-vmulcaddc/gen/c8-minmax-fma3-2x.c",
    "src/f32-dwconv/gen/up8x25-minmax-fma3.c",
    "src/f32-dwconv/gen/up16x3-minmax-fma3.c",
    "src/f32-dwconv/gen/up16x4-minmax-fma3.c",
    "src/f32-dwconv/gen/up16x9-minmax-fma3.c",
    "src/f32-gemm/gen/1x16-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/1x16s4-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/4x16s4-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/5x16-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/1x16-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/1x16s4-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/4x16s4-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/5x16-minmax-fma3-broadcast.c",
    "src/f32-vhswish/gen/vhswish-fma3-x16.c",
]

ALL_FMA3_MICROKERNEL_SRCS = [
    "src/f16-dwconv/gen/up8x3-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up8x3-minmax-fma3.c",
    "src/f16-dwconv/gen/up8x4-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up8x4-minmax-fma3.c",
    "src/f16-dwconv/gen/up8x9-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up8x9-minmax-fma3.c",
    "src/f16-dwconv/gen/up8x25-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up8x25-minmax-fma3.c",
    "src/f16-dwconv/gen/up16x3-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up16x3-minmax-fma3.c",
    "src/f16-dwconv/gen/up16x4-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up16x4-minmax-fma3.c",
    "src/f16-dwconv/gen/up16x9-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up16x9-minmax-fma3.c",
    "src/f16-dwconv/gen/up16x25-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up16x25-minmax-fma3.c",
    "src/f16-dwconv/gen/up32x3-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up32x3-minmax-fma3.c",
    "src/f16-dwconv/gen/up32x4-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up32x4-minmax-fma3.c",
    "src/f16-dwconv/gen/up32x9-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up32x9-minmax-fma3.c",
    "src/f16-dwconv/gen/up32x25-minmax-fma3-acc2.c",
    "src/f16-dwconv/gen/up32x25-minmax-fma3.c",
    "src/f16-ibilinear/gen/fma3-c8.c",
    "src/f16-ibilinear/gen/fma3-c16.c",
    "src/f16-vmulcaddc/gen/c8-minmax-fma3-2x.c",
    "src/f16-vmulcaddc/gen/c16-minmax-fma3-2x.c",
    "src/f32-dwconv/gen/up8x3-minmax-fma3-acc2.c",
    "src/f32-dwconv/gen/up8x3-minmax-fma3.c",
    "src/f32-dwconv/gen/up8x4-minmax-fma3-acc2.c",
    "src/f32-dwconv/gen/up8x4-minmax-fma3.c",
    "src/f32-dwconv/gen/up8x9-minmax-fma3-acc2.c",
    "src/f32-dwconv/gen/up8x9-minmax-fma3.c",
    "src/f32-dwconv/gen/up8x25-minmax-fma3-acc2.c",
    "src/f32-dwconv/gen/up8x25-minmax-fma3.c",
    "src/f32-dwconv/gen/up16x3-minmax-fma3-acc2.c",
    "src/f32-dwconv/gen/up16x3-minmax-fma3.c",
    "src/f32-dwconv/gen/up16x4-minmax-fma3-acc2.c",
    "src/f32-dwconv/gen/up16x4-minmax-fma3.c",
    "src/f32-dwconv/gen/up16x9-minmax-fma3-acc2.c",
    "src/f32-dwconv/gen/up16x9-minmax-fma3.c",
    "src/f32-dwconv/gen/up16x25-minmax-fma3-acc2.c",
    "src/f32-dwconv/gen/up16x25-minmax-fma3.c",
    "src/f32-gemm/gen-inc/1x8inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/1x16inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/1x16s4inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/3x16inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/3x16s4inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/4x8inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/4x16inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/4x16s4inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/5x8inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/5x16inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/5x16s4inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/6x8inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/7x8inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen-inc/8x8inc-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/1x8-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/1x16-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/1x16s4-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/3x16-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/3x16s4-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/4x8-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/4x16-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/4x16s4-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/5x8-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/5x16-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/5x16s4-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/6x8-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/7x8-minmax-fma3-broadcast.c",
    "src/f32-gemm/gen/8x8-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/1x8-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/1x16-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/1x16s4-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/3x16-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/3x16s4-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/4x8-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/4x16-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/4x16s4-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/5x8-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/5x16-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/5x16s4-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/6x8-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/7x8-minmax-fma3-broadcast.c",
    "src/f32-igemm/gen/8x8-minmax-fma3-broadcast.c",
    "src/f32-vhswish/gen/vhswish-fma3-x8.c",
    "src/f32-vhswish/gen/vhswish-fma3-x16.c",
    "src/f32-vsqrt/gen/fma3-nr1fma1adj-x8.c",
    "src/f32-vsqrt/gen/fma3-nr1fma1adj-x16.c",
    "src/f32-vsqrt/gen/fma3-nr1fma1adj-x24.c",
    "src/f32-vsqrt/gen/fma3-nr1fma1adj-x32.c",
    "src/f32-vsqrt/gen/fma3-nr1fma1adj-x40.c",
    "src/f32-vsqrt/gen/fma3-nr1fma1adj-x48.c",
    "src/f32-vsqrt/gen/fma3-nr1fma1adj-x56.c",
    "src/f32-vsqrt/gen/fma3-nr1fma1adj-x64.c",
    "src/math/sqrt-fma3-nr1fma.c",
    "src/math/sqrt-fma3-nr1fma1adj.c",
    "src/math/sqrt-fma3-nr2fma.c",
]

PROD_AVX2_MICROKERNEL_SRCS = [
    "src/f16-gemm/gen/1x16-minmax-avx2-broadcast.c",
    "src/f16-gemm/gen/4x16-minmax-avx2-broadcast.c",
    "src/f16-igemm/gen/1x16-minmax-avx2-broadcast.c",
    "src/f16-igemm/gen/4x16-minmax-avx2-broadcast.c",
    "src/f16-pavgpool/9p8x-minmax-avx2-c8.c",
    "src/f16-pavgpool/9x-minmax-avx2-c8.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x40.c",
    "src/f16-velu/gen/velu-avx2-rr1-p3-x16.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-rcp-x32.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx2-x64.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx2-x64.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x56.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x40.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-avx2-mul32.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
    "src/qc8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qc8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qc8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qc8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx2-x16.c",
    "src/qs8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qs8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qs8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qs8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
    "src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
    "src/qs8-vcvt/gen/vcvt-avx2-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-avx2-x32.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx2-x16.c",
    "src/qu8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qu8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qu8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qu8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qu8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
    "src/qu8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
    "src/qu8-vcvt/gen/vcvt-avx2-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-avx2-x32.c",
    "src/x8-lut/gen/lut-avx2-x128.c",
]

ALL_AVX2_MICROKERNEL_SRCS = [
    "src/f16-gemm/gen/1x8-minmax-avx2-broadcast.c",
    "src/f16-gemm/gen/1x16-minmax-avx2-broadcast.c",
    "src/f16-gemm/gen/3x16-minmax-avx2-broadcast.c",
    "src/f16-gemm/gen/4x8-minmax-avx2-broadcast.c",
    "src/f16-gemm/gen/4x16-minmax-avx2-broadcast.c",
    "src/f16-gemm/gen/5x8-minmax-avx2-broadcast.c",
    "src/f16-gemm/gen/5x16-minmax-avx2-broadcast.c",
    "src/f16-gemm/gen/6x8-minmax-avx2-broadcast.c",
    "src/f16-gemm/gen/7x8-minmax-avx2-broadcast.c",
    "src/f16-igemm/gen/1x8-minmax-avx2-broadcast.c",
    "src/f16-igemm/gen/1x16-minmax-avx2-broadcast.c",
    "src/f16-igemm/gen/3x16-minmax-avx2-broadcast.c",
    "src/f16-igemm/gen/4x8-minmax-avx2-broadcast.c",
    "src/f16-igemm/gen/4x16-minmax-avx2-broadcast.c",
    "src/f16-igemm/gen/5x8-minmax-avx2-broadcast.c",
    "src/f16-igemm/gen/5x16-minmax-avx2-broadcast.c",
    "src/f16-igemm/gen/6x8-minmax-avx2-broadcast.c",
    "src/f16-igemm/gen/7x8-minmax-avx2-broadcast.c",
    "src/f16-pavgpool/9p8x-minmax-avx2-c8.c",
    "src/f16-pavgpool/9x-minmax-avx2-c8.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x32-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x32-acc4.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x32.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x40-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x40-acc5.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x40.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x48-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x48-acc3.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x48.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x64-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x64-acc4.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x64.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x72-acc3.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x72.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x80-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x80-acc5.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x80.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x96-acc2.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x96-acc3.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x96-acc6.c",
    "src/f16-raddstoreexpminusmax/gen/avx2-rr1-p2-x96.c",
    "src/f16-velu/gen/velu-avx2-rr1-p3-x8.c",
    "src/f16-velu/gen/velu-avx2-rr1-p3-x16.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-div-x8.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-div-x16.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-div-x24.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-div-x32.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-div-x40.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-div-x48.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-div-x56.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-div-x64.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-rcp-x8.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-rcp-x16.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-rcp-x24.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-rcp-x32.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-rcp-x40.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-rcp-x48.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-rcp-x56.c",
    "src/f16-vsigmoid/gen/vsigmoid-avx2-rr1-p2-rcp-x64.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx2-x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx2-x32.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx2-x48.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx2-x64.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx2-x16.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx2-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx2-x48.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx2-x64.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x64-acc2.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x64-acc4.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x64.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x72-acc3.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x72.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x80-acc2.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x80-acc5.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x80.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x96-acc2.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x96-acc3.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x96-acc6.c",
    "src/f32-raddexpminusmax/gen/avx2-p5-x96.c",
    "src/f32-raddextexp/gen/avx2-p5-x64-acc2.c",
    "src/f32-raddextexp/gen/avx2-p5-x64-acc4.c",
    "src/f32-raddextexp/gen/avx2-p5-x64.c",
    "src/f32-raddextexp/gen/avx2-p5-x72-acc3.c",
    "src/f32-raddextexp/gen/avx2-p5-x72.c",
    "src/f32-raddextexp/gen/avx2-p5-x80-acc2.c",
    "src/f32-raddextexp/gen/avx2-p5-x80-acc5.c",
    "src/f32-raddextexp/gen/avx2-p5-x80.c",
    "src/f32-raddextexp/gen/avx2-p5-x96-acc2.c",
    "src/f32-raddextexp/gen/avx2-p5-x96-acc3.c",
    "src/f32-raddextexp/gen/avx2-p5-x96-acc6.c",
    "src/f32-raddextexp/gen/avx2-p5-x96.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x64-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x64-acc4.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x64.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x72-acc3.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x72.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x80-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x80-acc5.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x80.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x96-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x96-acc3.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x96-acc6.c",
    "src/f32-raddstoreexpminusmax/gen/avx2-rr1-p5-x96.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x8.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x16.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x24.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x32.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x40.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x48.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x56.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x64.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x72.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut4-p4-perm-x80.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x8.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x16.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x24.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x32.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x40.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x48.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x56.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x64.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x72.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut8-p4-perm-x80.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x8.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x16.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x24.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x32.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x40.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x48.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x56.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x64.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x72.c",
    "src/f32-velu/gen/velu-avx2-rr1-lut16-p3-gather-x80.c",
    "src/f32-velu/gen/velu-avx2-rr1-p6-x8.c",
    "src/f32-velu/gen/velu-avx2-rr1-p6-x16.c",
    "src/f32-velu/gen/velu-avx2-rr1-p6-x24.c",
    "src/f32-velu/gen/velu-avx2-rr1-p6-x32.c",
    "src/f32-velu/gen/velu-avx2-rr1-p6-x40.c",
    "src/f32-velu/gen/velu-avx2-rr1-p6-x48.c",
    "src/f32-velu/gen/velu-avx2-rr1-p6-x56.c",
    "src/f32-velu/gen/velu-avx2-rr1-p6-x64.c",
    "src/f32-velu/gen/velu-avx2-rr1-p6-x72.c",
    "src/f32-velu/gen/velu-avx2-rr1-p6-x80.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x8.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x16.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x24.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x32.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x40.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x48.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x56.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x64.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x72.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x80.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x88.c",
    "src/f32-vscaleexpminusmax/gen/avx2-p5-x96.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x8.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x16.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x24.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x32.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x40.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x48.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x56.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x64.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x72.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x80.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x88.c",
    "src/f32-vscaleextexp/gen/avx2-p5-x96.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x32.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x40.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x48.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x56.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x64.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x72.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-div-x80.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x32.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x40.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x48.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x56.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x64.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x72.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr1fma-x80.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x8.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x24.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x32.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x40.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x48.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x56.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x64.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x72.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx2-rr1-p5-nr2fma-x80.c",
    "src/math/exp-f32-avx2-rr2-lut8-p3-perm.c",
    "src/math/exp-f32-avx2-rr2-lut8-p4-perm.c",
    "src/math/exp-f32-avx2-rr2-p5.c",
    "src/math/expminus-f16-avx2-rr1-p2.c",
    "src/math/expminus-f16-avx2-rr1-p3.c",
    "src/math/expminus-f32-avx2-rr1-p5.c",
    "src/math/expminus-f32-avx2-rr2-p5.c",
    "src/math/expm1minus-f16-avx2-rr1-p3.c",
    "src/math/expm1minus-f32-avx2-rr1-lut4-p4-perm.c",
    "src/math/expm1minus-f32-avx2-rr1-lut8-p4-perm.c",
    "src/math/expm1minus-f32-avx2-rr1-lut16-p3-gather.c",
    "src/math/expm1minus-f32-avx2-rr1-p6.c",
    "src/math/extexp-avx2-p5.c",
    "src/math/sigmoid-f16-avx2-rr1-p2-div.c",
    "src/math/sigmoid-f16-avx2-rr1-p2-rcp.c",
    "src/math/sigmoid-f16-avx2-rr1-p3-div.c",
    "src/math/sigmoid-f16-avx2-rr1-p3-rcp.c",
    "src/math/sigmoid-f32-avx2-rr1-lut64-p2-gather-div.c",
    "src/math/sigmoid-f32-avx2-rr1-lut64-p2-gather-nr1fma.c",
    "src/math/sigmoid-f32-avx2-rr1-lut64-p2-gather-nr2fma.c",
    "src/math/sigmoid-f32-avx2-rr1-lut64-p2-gather-nr2fma1adj.c",
    "src/math/sigmoid-f32-avx2-rr1-p5-div.c",
    "src/math/sigmoid-f32-avx2-rr1-p5-nr1fma.c",
    "src/math/sigmoid-f32-avx2-rr1-p5-nr2fma.c",
    "src/math/sigmoid-f32-avx2-rr2-lut64-p2-gather-div.c",
    "src/math/sigmoid-f32-avx2-rr2-lut64-p2-gather-nr1fma.c",
    "src/math/sigmoid-f32-avx2-rr2-lut64-p2-gather-nr2fma.c",
    "src/math/sigmoid-f32-avx2-rr2-lut64-p2-gather-nr2fma1adj.c",
    "src/math/sigmoid-f32-avx2-rr2-p5-div.c",
    "src/math/sigmoid-f32-avx2-rr2-p5-nr1fma.c",
    "src/math/sigmoid-f32-avx2-rr2-p5-nr2fma.c",
    "src/qc8-dwconv/gen/up8x9-minmax-fp32-avx2-mul32.c",
    "src/qc8-dwconv/gen/up8x25-minmax-fp32-avx2-mul32.c",
    "src/qc8-dwconv/gen/up16x3-minmax-fp32-avx2-mul32.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpmovsx.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpunpck.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpmovsx.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpunpck.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
    "src/qc8-dwconv/gen/up24x9-minmax-fp32-avx2-mul32.c",
    "src/qc8-dwconv/gen/up24x25-minmax-fp32-avx2-mul32.c",
    "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
    "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpmovsx.c",
    "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpunpck.c",
    "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx2-mul32.c",
    "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
    "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpmovsx.c",
    "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpunpck.c",
    "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx2-mul32.c",
    "src/qc8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qc8-gemm/gen/1x8c8-xw-minmax-fp32-avx2.c",
    "src/qc8-gemm/gen/2x8c8-minmax-fp32-avx2.c",
    "src/qc8-gemm/gen/2x8c8-xw-minmax-fp32-avx2.c",
    "src/qc8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qc8-gemm/gen/3x8c8-xw-minmax-fp32-avx2.c",
    "src/qc8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qc8-igemm/gen/2x8c8-minmax-fp32-avx2.c",
    "src/qc8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qs8-dwconv/gen/up8x9-minmax-fp32-avx2-mul32.c",
    "src/qs8-dwconv/gen/up8x25-minmax-fp32-avx2-mul32.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpmovsx.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul16-vpunpck.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpmovsx.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul16-vpunpck.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
    "src/qs8-dwconv/gen/up24x9-minmax-fp32-avx2-mul32.c",
    "src/qs8-dwconv/gen/up24x25-minmax-fp32-avx2-mul32.c",
    "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-add16-vpunpck.c",
    "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpmovsx.c",
    "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul16-vpunpck.c",
    "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx2-mul32.c",
    "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-add16-vpunpck.c",
    "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpmovsx.c",
    "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul16-vpunpck.c",
    "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx2-mul32.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx2-x8.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx2-x16.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx2-x24.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx2-x32.c",
    "src/qs8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qs8-gemm/gen/1x8c8-xw-minmax-fp32-avx2.c",
    "src/qs8-gemm/gen/2x8c8-minmax-fp32-avx2.c",
    "src/qs8-gemm/gen/2x8c8-xw-minmax-fp32-avx2.c",
    "src/qs8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qs8-gemm/gen/3x8c8-xw-minmax-fp32-avx2.c",
    "src/qs8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qs8-igemm/gen/2x8c8-minmax-fp32-avx2.c",
    "src/qs8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x8.c",
    "src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
    "src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x24.c",
    "src/qs8-vadd/gen/minmax-avx2-mul32-ld64-x32.c",
    "src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x8.c",
    "src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
    "src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x24.c",
    "src/qs8-vaddc/gen/minmax-avx2-mul32-ld64-x32.c",
    "src/qs8-vcvt/gen/vcvt-avx2-x16.c",
    "src/qs8-vcvt/gen/vcvt-avx2-x32.c",
    "src/qs8-vcvt/gen/vcvt-avx2-x64.c",
    "src/qs8-vlrelu/gen/vlrelu-avx2-x16.c",
    "src/qs8-vlrelu/gen/vlrelu-avx2-x32.c",
    "src/qs8-vlrelu/gen/vlrelu-avx2-x64.c",
    "src/qu8-dwconv/gen/up8x9-minmax-fp32-avx2-mul32.c",
    "src/qu8-dwconv/gen/up8x25-minmax-fp32-avx2-mul32.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx2-mul32.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx2-mul32.c",
    "src/qu8-dwconv/gen/up32x9-minmax-fp32-avx2-mul32.c",
    "src/qu8-dwconv/gen/up32x25-minmax-fp32-avx2-mul32.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx2-x8.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx2-x16.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx2-x24.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx2-x32.c",
    "src/qu8-gemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qu8-gemm/gen/2x8c8-minmax-fp32-avx2.c",
    "src/qu8-gemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qu8-igemm/gen/1x8c8-minmax-fp32-avx2.c",
    "src/qu8-igemm/gen/2x8c8-minmax-fp32-avx2.c",
    "src/qu8-igemm/gen/3x8c8-minmax-fp32-avx2.c",
    "src/qu8-vadd/gen/minmax-avx2-mul32-ld64-x8.c",
    "src/qu8-vadd/gen/minmax-avx2-mul32-ld64-x16.c",
    "src/qu8-vaddc/gen/minmax-avx2-mul32-ld64-x8.c",
    "src/qu8-vaddc/gen/minmax-avx2-mul32-ld64-x16.c",
    "src/qu8-vcvt/gen/vcvt-avx2-x16.c",
    "src/qu8-vcvt/gen/vcvt-avx2-x32.c",
    "src/qu8-vcvt/gen/vcvt-avx2-x64.c",
    "src/qu8-vlrelu/gen/vlrelu-avx2-x16.c",
    "src/qu8-vlrelu/gen/vlrelu-avx2-x32.c",
    "src/qu8-vlrelu/gen/vlrelu-avx2-x64.c",
    "src/x8-lut/gen/lut-avx2-x32.c",
    "src/x8-lut/gen/lut-avx2-x64.c",
    "src/x8-lut/gen/lut-avx2-x96.c",
    "src/x8-lut/gen/lut-avx2-x128.c",
]

PROD_AVX512F_MICROKERNEL_SRCS = [
    "src/f32-dwconv/gen/up16x3-minmax-avx512f.c",
    "src/f32-dwconv/gen/up16x4-minmax-avx512f.c",
    "src/f32-dwconv/gen/up16x9-minmax-avx512f.c",
    "src/f32-dwconv/gen/up16x25-minmax-avx512f.c",
    "src/f32-gemm/gen/1x16-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen/7x16-minmax-avx512f-broadcast.c",
    "src/f32-igemm/gen/1x16-minmax-avx512f-broadcast.c",
    "src/f32-igemm/gen/7x16-minmax-avx512f-broadcast.c",
    "src/f32-prelu/gen/avx512f-2x16.c",
    "src/f32-vbinary/gen/vadd-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vaddc-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vdiv-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vdivc-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vmaxc-avx512f-x32.c",
    "src/f32-vbinary/gen/vmin-avx512f-x32.c",
    "src/f32-vbinary/gen/vminc-avx512f-x32.c",
    "src/f32-vbinary/gen/vmul-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vmulc-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vrdivc-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vrsubc-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vsqrdiff-avx512f-x32.c",
    "src/f32-vbinary/gen/vsqrdiffc-avx512f-x32.c",
    "src/f32-vbinary/gen/vsub-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vsubc-minmax-avx512f-x32.c",
    "src/f32-vclamp/gen/vclamp-avx512f-x16.c",
    "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x64.c",
    "src/f32-vhswish/gen/vhswish-avx512f-x16.c",
    "src/f32-vlrelu/gen/vlrelu-avx512f-x16.c",
    "src/f32-vrnd/gen/vrndd-avx512f-x16.c",
    "src/f32-vrnd/gen/vrndne-avx512f-x16.c",
    "src/f32-vrnd/gen/vrndu-avx512f-x16.c",
    "src/f32-vrnd/gen/vrndz-avx512f-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x64.c",
    "src/f32-vunary/gen/vabs-avx512f-x16.c",
    "src/f32-vunary/gen/vneg-avx512f-x16.c",
    "src/f32-vunary/gen/vsqr-avx512f-x16.c",
]

ALL_AVX512F_MICROKERNEL_SRCS = [
    "src/f32-dwconv/gen/up16x3-minmax-avx512f-acc2.c",
    "src/f32-dwconv/gen/up16x3-minmax-avx512f.c",
    "src/f32-dwconv/gen/up16x4-minmax-avx512f-acc2.c",
    "src/f32-dwconv/gen/up16x4-minmax-avx512f.c",
    "src/f32-dwconv/gen/up16x9-minmax-avx512f-acc2.c",
    "src/f32-dwconv/gen/up16x9-minmax-avx512f.c",
    "src/f32-dwconv/gen/up16x25-minmax-avx512f-acc2.c",
    "src/f32-dwconv/gen/up16x25-minmax-avx512f.c",
    "src/f32-dwconv/gen/up32x3-minmax-avx512f-acc2.c",
    "src/f32-dwconv/gen/up32x3-minmax-avx512f.c",
    "src/f32-dwconv/gen/up32x4-minmax-avx512f-acc2.c",
    "src/f32-dwconv/gen/up32x4-minmax-avx512f.c",
    "src/f32-dwconv/gen/up32x9-minmax-avx512f-acc2.c",
    "src/f32-dwconv/gen/up32x9-minmax-avx512f.c",
    "src/f32-dwconv/gen/up32x25-minmax-avx512f-acc2.c",
    "src/f32-dwconv/gen/up32x25-minmax-avx512f.c",
    "src/f32-gemm/gen-inc/1x16inc-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen-inc/4x16inc-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen-inc/5x16inc-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen-inc/6x16inc-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen-inc/7x16inc-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen-inc/8x16inc-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen/1x16-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen/4x16-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen/5x16-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen/6x16-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen/7x16-minmax-avx512f-broadcast.c",
    "src/f32-gemm/gen/8x16-minmax-avx512f-broadcast.c",
    "src/f32-igemm/gen/1x16-minmax-avx512f-broadcast.c",
    "src/f32-igemm/gen/4x16-minmax-avx512f-broadcast.c",
    "src/f32-igemm/gen/5x16-minmax-avx512f-broadcast.c",
    "src/f32-igemm/gen/6x16-minmax-avx512f-broadcast.c",
    "src/f32-igemm/gen/7x16-minmax-avx512f-broadcast.c",
    "src/f32-igemm/gen/8x16-minmax-avx512f-broadcast.c",
    "src/f32-prelu/gen/avx512f-2x16.c",
    "src/f32-prelu/gen/avx512f-2x32.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x128-acc2.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x128-acc4.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x128.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x144-acc3.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x144.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x160-acc2.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x160-acc5.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x160.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x192-acc2.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x192-acc3.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x192-acc6.c",
    "src/f32-raddexpminusmax/gen/avx512f-p5-scalef-x192.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x128-acc2.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x128-acc4.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x128.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x144-acc3.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x144.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x160-acc2.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x160-acc5.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x160.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x192-acc2.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x192-acc3.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x192-acc6.c",
    "src/f32-raddextexp/gen/avx512f-p5-scalef-x192.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x128-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x128-acc4.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x128.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x144-acc3.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x144.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x160-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x160-acc5.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x160.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x192-acc2.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x192-acc3.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x192-acc6.c",
    "src/f32-raddstoreexpminusmax/gen/avx512f-rr1-p5-scalef-x192.c",
    "src/f32-rmax/avx512f.c",
    "src/f32-vbinary/gen/vadd-minmax-avx512f-x16.c",
    "src/f32-vbinary/gen/vadd-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vaddc-minmax-avx512f-x16.c",
    "src/f32-vbinary/gen/vaddc-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vdiv-minmax-avx512f-x16.c",
    "src/f32-vbinary/gen/vdiv-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vdivc-minmax-avx512f-x16.c",
    "src/f32-vbinary/gen/vdivc-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vmax-avx512f-x16.c",
    "src/f32-vbinary/gen/vmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vmaxc-avx512f-x16.c",
    "src/f32-vbinary/gen/vmaxc-avx512f-x32.c",
    "src/f32-vbinary/gen/vmin-avx512f-x16.c",
    "src/f32-vbinary/gen/vmin-avx512f-x32.c",
    "src/f32-vbinary/gen/vminc-avx512f-x16.c",
    "src/f32-vbinary/gen/vminc-avx512f-x32.c",
    "src/f32-vbinary/gen/vmul-minmax-avx512f-x16.c",
    "src/f32-vbinary/gen/vmul-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vmulc-minmax-avx512f-x16.c",
    "src/f32-vbinary/gen/vmulc-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vrdivc-minmax-avx512f-x16.c",
    "src/f32-vbinary/gen/vrdivc-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vrsubc-minmax-avx512f-x16.c",
    "src/f32-vbinary/gen/vrsubc-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vsqrdiff-avx512f-x16.c",
    "src/f32-vbinary/gen/vsqrdiff-avx512f-x32.c",
    "src/f32-vbinary/gen/vsqrdiffc-avx512f-x16.c",
    "src/f32-vbinary/gen/vsqrdiffc-avx512f-x32.c",
    "src/f32-vbinary/gen/vsub-minmax-avx512f-x16.c",
    "src/f32-vbinary/gen/vsub-minmax-avx512f-x32.c",
    "src/f32-vbinary/gen/vsubc-minmax-avx512f-x16.c",
    "src/f32-vbinary/gen/vsubc-minmax-avx512f-x32.c",
    "src/f32-vclamp/gen/vclamp-avx512f-x16.c",
    "src/f32-vclamp/gen/vclamp-avx512f-x32.c",
    "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x16.c",
    "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x32.c",
    "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x48.c",
    "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x64.c",
    "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x80.c",
    "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x96.c",
    "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x112.c",
    "src/f32-velu/gen/velu-avx512f-rr1-lut16-p3-perm-x128.c",
    "src/f32-velu/gen/velu-avx512f-rr1-p6-x16.c",
    "src/f32-velu/gen/velu-avx512f-rr1-p6-x32.c",
    "src/f32-velu/gen/velu-avx512f-rr1-p6-x48.c",
    "src/f32-velu/gen/velu-avx512f-rr1-p6-x64.c",
    "src/f32-velu/gen/velu-avx512f-rr1-p6-x80.c",
    "src/f32-velu/gen/velu-avx512f-rr1-p6-x96.c",
    "src/f32-velu/gen/velu-avx512f-rr1-p6-x112.c",
    "src/f32-velu/gen/velu-avx512f-rr1-p6-x128.c",
    "src/f32-vhswish/gen/vhswish-avx512f-x16.c",
    "src/f32-vhswish/gen/vhswish-avx512f-x32.c",
    "src/f32-vlrelu/gen/vlrelu-avx512f-x16.c",
    "src/f32-vlrelu/gen/vlrelu-avx512f-x32.c",
    "src/f32-vrelu/gen/vrelu-avx512f-x16.c",
    "src/f32-vrelu/gen/vrelu-avx512f-x32.c",
    "src/f32-vrnd/gen/vrndd-avx512f-x16.c",
    "src/f32-vrnd/gen/vrndd-avx512f-x32.c",
    "src/f32-vrnd/gen/vrndne-avx512f-x16.c",
    "src/f32-vrnd/gen/vrndne-avx512f-x32.c",
    "src/f32-vrnd/gen/vrndu-avx512f-x16.c",
    "src/f32-vrnd/gen/vrndu-avx512f-x32.c",
    "src/f32-vrnd/gen/vrndz-avx512f-x16.c",
    "src/f32-vrnd/gen/vrndz-avx512f-x32.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x16.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x32.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x48.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x64.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x80.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x96.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x112.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x128.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x144.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x160.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x176.c",
    "src/f32-vscaleexpminusmax/gen/avx512f-p5-scalef-x192.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x16.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x32.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x48.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x64.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x80.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x96.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x112.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x128.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x144.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x160.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x176.c",
    "src/f32-vscaleextexp/gen/avx512f-p5-scalef-x192.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x32.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x48.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x64.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x80.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x96.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x112.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-div-x128.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x32.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x48.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x64.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x80.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x96.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x112.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-lut16-p3-perm-scalef-nr1fma-x128.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x32.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x48.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x64.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x80.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x96.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x112.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-div-x128.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x32.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x48.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x64.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x80.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x96.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x112.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr1-p5-scalef-nr1fma-x128.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x32.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x48.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x64.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x80.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x96.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x112.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-div-x128.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x16.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x32.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x48.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x64.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x80.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x96.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x112.c",
    "src/f32-vsigmoid/gen/vsigmoid-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma-x128.c",
    "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x16.c",
    "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x32.c",
    "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x48.c",
    "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x64.c",
    "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x80.c",
    "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x96.c",
    "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x112.c",
    "src/f32-vsqrt/gen/avx512f-nr1fma1adj-x128.c",
    "src/f32-vunary/gen/vabs-avx512f-x16.c",
    "src/f32-vunary/gen/vabs-avx512f-x32.c",
    "src/f32-vunary/gen/vneg-avx512f-x16.c",
    "src/f32-vunary/gen/vneg-avx512f-x32.c",
    "src/f32-vunary/gen/vsqr-avx512f-x16.c",
    "src/f32-vunary/gen/vsqr-avx512f-x32.c",
    "src/math/exp-f32-avx512f-rr2-lut16-p3-perm-scalef.c",
    "src/math/exp-f32-avx512f-rr2-lut16-p3-perm.c",
    "src/math/exp-f32-avx512f-rr2-lut32-p2-perm2-scalef.c",
    "src/math/exp-f32-avx512f-rr2-lut32-p2-perm2.c",
    "src/math/exp-f32-avx512f-rr2-p5-scalef.c",
    "src/math/exp-f32-avx512f-rr2-p5.c",
    "src/math/expm1minus-f32-avx512f-rr1-lut16-p3-perm.c",
    "src/math/expm1minus-f32-avx512f-rr1-p6.c",
    "src/math/extexp-avx512f-p5.c",
    "src/math/sigmoid-f32-avx512f-rr1-lut16-p3-perm-scalef-div.c",
    "src/math/sigmoid-f32-avx512f-rr1-lut16-p3-perm-scalef-nr1fma.c",
    "src/math/sigmoid-f32-avx512f-rr1-lut16-p3-perm-scalef-nr1fma1adj.c",
    "src/math/sigmoid-f32-avx512f-rr1-lut32-p2-perm2-scalef-div.c",
    "src/math/sigmoid-f32-avx512f-rr1-lut32-p2-perm2-scalef-nr1fma.c",
    "src/math/sigmoid-f32-avx512f-rr1-lut32-p2-perm2-scalef-nr1fma1adj.c",
    "src/math/sigmoid-f32-avx512f-rr1-lut64-p2-gather-scalef-div.c",
    "src/math/sigmoid-f32-avx512f-rr1-lut64-p2-gather-scalef-nr1fma.c",
    "src/math/sigmoid-f32-avx512f-rr1-lut64-p2-gather-scalef-nr1fma1adj.c",
    "src/math/sigmoid-f32-avx512f-rr1-p5-scalef-div.c",
    "src/math/sigmoid-f32-avx512f-rr1-p5-scalef-nr1fma.c",
    "src/math/sigmoid-f32-avx512f-rr1-p5-scalef-nr1fma1adj.c",
    "src/math/sigmoid-f32-avx512f-rr2-lut16-p3-perm-scalef-div.c",
    "src/math/sigmoid-f32-avx512f-rr2-lut16-p3-perm-scalef-nr1fma.c",
    "src/math/sigmoid-f32-avx512f-rr2-lut16-p3-perm-scalef-nr1fma1adj.c",
    "src/math/sigmoid-f32-avx512f-rr2-lut32-p2-perm2-scalef-div.c",
    "src/math/sigmoid-f32-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma.c",
    "src/math/sigmoid-f32-avx512f-rr2-lut32-p2-perm2-scalef-nr1fma1adj.c",
    "src/math/sigmoid-f32-avx512f-rr2-lut64-p2-gather-scalef-div.c",
    "src/math/sigmoid-f32-avx512f-rr2-lut64-p2-gather-scalef-nr1fma.c",
    "src/math/sigmoid-f32-avx512f-rr2-lut64-p2-gather-scalef-nr1fma1adj.c",
    "src/math/sigmoid-f32-avx512f-rr2-p5-scalef-div.c",
    "src/math/sigmoid-f32-avx512f-rr2-p5-scalef-nr1fma.c",
    "src/math/sigmoid-f32-avx512f-rr2-p5-scalef-nr1fma1adj.c",
    "src/math/sqrt-avx512f-nr1fma.c",
    "src/math/sqrt-avx512f-nr1fma1adj.c",
    "src/math/sqrt-avx512f-nr2fma.c",
]

PROD_AVX512SKX_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-avx512skx-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-avx512skx-x16.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx512skx-x128.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx512skx-x128.c",
    "src/qc8-dwconv/gen/up32x3-minmax-fp32-avx512skx-mul32.c",
    "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
    "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
    "src/qc8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qc8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qc8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qc8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
    "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx512skx-x32.c",
    "src/qs8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
    "src/qs8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
    "src/qu8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
    "src/qu8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx512skx-x32.c",
    "src/qu8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
    "src/qu8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
    "src/x8-lut/gen/lut-avx512skx-vpshufb-x64.c",
]

ALL_AVX512SKX_MICROKERNEL_SRCS = [
    "src/f16-f32-vcvt/gen/vcvt-avx512skx-x16.c",
    "src/f16-f32-vcvt/gen/vcvt-avx512skx-x32.c",
    "src/f32-f16-vcvt/gen/vcvt-avx512skx-x16.c",
    "src/f32-f16-vcvt/gen/vcvt-avx512skx-x32.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx512skx-x32.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx512skx-x64.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx512skx-x96.c",
    "src/f32-qs8-vcvt/gen/vcvt-avx512skx-x128.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx512skx-x32.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx512skx-x64.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx512skx-x96.c",
    "src/f32-qu8-vcvt/gen/vcvt-avx512skx-x128.c",
    "src/qc8-dwconv/gen/up16x9-minmax-fp32-avx512skx-mul32.c",
    "src/qc8-dwconv/gen/up16x25-minmax-fp32-avx512skx-mul32.c",
    "src/qc8-dwconv/gen/up32x3-minmax-fp32-avx512skx-mul32.c",
    "src/qc8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
    "src/qc8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
    "src/qc8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qc8-gemm/gen/2x16c8-minmax-fp32-avx512skx.c",
    "src/qc8-gemm/gen/3x16c8-minmax-fp32-avx512skx.c",
    "src/qc8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qc8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qc8-igemm/gen/2x16c8-minmax-fp32-avx512skx.c",
    "src/qc8-igemm/gen/3x16c8-minmax-fp32-avx512skx.c",
    "src/qc8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-dwconv/gen/up16x9-minmax-fp32-avx512skx-mul32.c",
    "src/qs8-dwconv/gen/up16x25-minmax-fp32-avx512skx-mul32.c",
    "src/qs8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
    "src/qs8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx512skx-x16.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx512skx-x32.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx512skx-x48.c",
    "src/qs8-f32-vcvt/gen/vcvt-avx512skx-x64.c",
    "src/qs8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-gemm/gen/2x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-gemm/gen/3x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-igemm/gen/2x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-igemm/gen/3x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qs8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
    "src/qs8-vadd/gen/minmax-avx512skx-mul32-ld128-x32.c",
    "src/qs8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
    "src/qs8-vaddc/gen/minmax-avx512skx-mul32-ld128-x32.c",
    "src/qu8-dwconv/gen/up16x9-minmax-fp32-avx512skx-mul32.c",
    "src/qu8-dwconv/gen/up16x25-minmax-fp32-avx512skx-mul32.c",
    "src/qu8-dwconv/gen/up32x9-minmax-fp32-avx512skx-mul32.c",
    "src/qu8-dwconv/gen/up32x25-minmax-fp32-avx512skx-mul32.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx512skx-x16.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx512skx-x32.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx512skx-x48.c",
    "src/qu8-f32-vcvt/gen/vcvt-avx512skx-x64.c",
    "src/qu8-gemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-gemm/gen/2x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-gemm/gen/3x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-gemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-igemm/gen/1x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-igemm/gen/2x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-igemm/gen/3x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-igemm/gen/4x16c8-minmax-fp32-avx512skx.c",
    "src/qu8-vadd/gen/minmax-avx512skx-mul32-ld128-x16.c",
    "src/qu8-vadd/gen/minmax-avx512skx-mul32-ld128-x32.c",
    "src/qu8-vaddc/gen/minmax-avx512skx-mul32-ld128-x16.c",
    "src/qu8-vaddc/gen/minmax-avx512skx-mul32-ld128-x32.c",
    "src/x8-lut/gen/lut-avx512skx-vpshufb-x64.c",
    "src/x8-lut/gen/lut-avx512skx-vpshufb-x128.c",
    "src/x8-lut/gen/lut-avx512skx-vpshufb-x192.c",
    "src/x8-lut/gen/lut-avx512skx-vpshufb-x256.c",
]

WASM32_ASM_MICROKERNEL_SRCS = [
    "src/f32-vrelu/wasm_shr_x1.S",
    "src/f32-vrelu/wasm_shr_x2.S",
    "src/f32-vrelu/wasm_shr_x4.S",
]

AARCH32_ASM_MICROKERNEL_SRCS = [
    "src/f32-gemm/gen/4x8-minmax-aarch32-neon-cortex-a7.S",
    "src/f32-gemm/gen/4x8-minmax-aarch32-neon-cortex-a53.S",
    "src/f32-gemm/gen/4x8-minmax-aarch32-neon-cortex-a75.S",
    "src/f32-gemm/gen/4x8-minmax-aarch32-neon-ld64.S",
    "src/f32-gemm/gen/4x8-minmax-aarch32-neon-prfm-cortex-a53.S",
    "src/f32-gemm/gen/4x8-minmax-aarch32-neon-prfm-cortex-a75.S",
    "src/f32-gemm/4x4-aarch32-vfp-ld64.S",
    "src/f32-gemm/4x4-minmax-aarch32-vfp-ld64.S",
    "src/f32-gemm/4x8-minmax-aarch32-neon-cortex-a55.S",
    "src/f32-igemm/gen/4x8-minmax-aarch32-neon-cortex-a7.S",
    "src/f32-igemm/gen/4x8-minmax-aarch32-neon-cortex-a53.S",
    "src/f32-igemm/gen/4x8-minmax-aarch32-neon-cortex-a75.S",
    "src/f32-igemm/gen/4x8-minmax-aarch32-neon-ld64.S",
    "src/f32-igemm/gen/4x8-minmax-aarch32-neon-prfm-cortex-a53.S",
    "src/f32-igemm/gen/4x8-minmax-aarch32-neon-prfm-cortex-a75.S",
    "src/f32-igemm/4x8-minmax-aarch32-neon-cortex-a55.S",
    "src/qc8-dwconv/up8x3-minmax-fp32-aarch32-neonv8-mla8-cortex-a35.S",
    "src/qc8-dwconv/up16x3-minmax-fp32-aarch32-neonv8-mla8-cortex-a35.S",
    "src/qc8-gemm/gen/1x8-minmax-fp32-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qc8-gemm/gen/1x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qc8-gemm/gen/1x8-minmax-fp32-aarch32-neonv8-mlal-lane-cortex-a35.S",
    "src/qc8-gemm/gen/1x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-cortex-a35.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-cortex-a53.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-ld64.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-ld64.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-cortex-a35.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-cortex-a53.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-ld64.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-cortex-a35.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-cortex-a53.S",
    "src/qc8-gemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-ld64.S",
    "src/qc8-gemm/gen/4x8c4-minmax-fp32-aarch32-neondot-cortex-a55.S",
    "src/qc8-gemm/gen/4x8c4-minmax-fp32-aarch32-neondot-ld64.S",
    "src/qc8-igemm/gen/1x8-minmax-fp32-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qc8-igemm/gen/1x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qc8-igemm/gen/1x8-minmax-fp32-aarch32-neonv8-mlal-lane-cortex-a35.S",
    "src/qc8-igemm/gen/1x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-cortex-a35.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-cortex-a53.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-ld64.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neon-mlal-lane-prfm-ld64.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-cortex-a35.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-cortex-a53.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-ld64.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-cortex-a35.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-cortex-a53.S",
    "src/qc8-igemm/gen/4x8-minmax-fp32-aarch32-neonv8-mlal-lane-prfm-ld64.S",
    "src/qc8-igemm/gen/4x8c4-minmax-fp32-aarch32-neondot-cortex-a55.S",
    "src/qc8-igemm/gen/4x8c4-minmax-fp32-aarch32-neondot-ld64.S",
    "src/qs8-gemm/gen/1x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qs8-gemm/gen/1x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a53.S",
    "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-ld64.S",
    "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-ld64.S",
    "src/qs8-gemm/gen/4x8c4-minmax-rndnu-aarch32-neondot-cortex-a55.S",
    "src/qs8-gemm/gen/4x8c4-minmax-rndnu-aarch32-neondot-ld64.S",
    "src/qs8-igemm/gen/1x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qs8-igemm/gen/1x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a53.S",
    "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-ld64.S",
    "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-ld64.S",
    "src/qs8-igemm/gen/4x8c4-minmax-rndnu-aarch32-neondot-cortex-a55.S",
    "src/qs8-igemm/gen/4x8c4-minmax-rndnu-aarch32-neondot-ld64.S",
    "src/qu8-gemm/gen/1x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qu8-gemm/gen/1x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a53.S",
    "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-ld64.S",
    "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qu8-gemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-ld64.S",
    "src/qu8-igemm/gen/1x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qu8-igemm/gen/1x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qu8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a7.S",
    "src/qu8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-cortex-a53.S",
    "src/qu8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-ld64.S",
    "src/qu8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a7.S",
    "src/qu8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qu8-igemm/gen/4x8-minmax-rndnu-aarch32-neon-mlal-lane-prfm-ld64.S",
    "src/u32-filterbank-accumulate/aarch32-arm-x1.S",
    "src/u32-filterbank-accumulate/aarch32-neon-x1.S",
    "src/u32-filterbank-accumulate/aarch32-neon-x2.S",
]

AARCH64_ASM_MICROKERNEL_SRCS = [
    "src/f16-gemm/gen-inc/1x8inc-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-gemm/gen-inc/1x16inc-minmax-aarch64-neonfp16arith-ld32.S",
    "src/f16-gemm/gen-inc/4x8inc-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-gemm/gen-inc/4x16inc-minmax-aarch64-neonfp16arith-ld32.S",
    "src/f16-gemm/gen-inc/6x8inc-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-gemm/gen-inc/6x16inc-minmax-aarch64-neonfp16arith-cortex-a55.S",
    "src/f16-gemm/gen-inc/6x16inc-minmax-aarch64-neonfp16arith-cortex-a75.S",
    "src/f16-gemm/gen-inc/6x16inc-minmax-aarch64-neonfp16arith-ld32.S",
    "src/f16-gemm/gen-inc/8x8inc-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-gemm/gen/1x8-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-gemm/gen/1x16-minmax-aarch64-neonfp16arith-ld32.S",
    "src/f16-gemm/gen/1x16-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-gemm/gen/4x8-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-gemm/gen/4x16-minmax-aarch64-neonfp16arith-ld32.S",
    "src/f16-gemm/gen/4x16-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-gemm/gen/6x8-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-gemm/gen/6x16-minmax-aarch64-neonfp16arith-cortex-a55.S",
    "src/f16-gemm/gen/6x16-minmax-aarch64-neonfp16arith-cortex-a55r0.S",
    "src/f16-gemm/gen/6x16-minmax-aarch64-neonfp16arith-cortex-a75.S",
    "src/f16-gemm/gen/6x16-minmax-aarch64-neonfp16arith-ld32.S",
    "src/f16-gemm/gen/6x16-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-gemm/gen/8x8-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-igemm/1x16-minmax-aarch64-neonfp16arith-ld32.S",
    "src/f16-igemm/1x16-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-igemm/4x16-minmax-aarch64-neonfp16arith-ld32.S",
    "src/f16-igemm/4x16-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f16-igemm/6x16-minmax-aarch64-neonfp16arith-cortex-a55.S",
    "src/f16-igemm/6x16-minmax-aarch64-neonfp16arith-cortex-a55r0.S",
    "src/f16-igemm/6x16-minmax-aarch64-neonfp16arith-cortex-a75.S",
    "src/f16-igemm/6x16-minmax-aarch64-neonfp16arith-ld32.S",
    "src/f16-igemm/6x16-minmax-aarch64-neonfp16arith-ld64.S",
    "src/f32-dwconv/up4x9-minmax-aarch64-neonfma-cortex-a55.S",
    "src/f32-dwconv/up4x9-minmax-aarch64-neonfma.S",
    "src/f32-gemm/gen-inc/1x8inc-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-gemm/gen-inc/1x8inc-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-gemm/gen-inc/1x8inc-minmax-aarch64-neonfma-ld64.S",
    "src/f32-gemm/gen-inc/1x8inc-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-gemm/gen-inc/1x12inc-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-cortex-a55.S",
    "src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-ld64.S",
    "src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-ld128.S",
    "src/f32-gemm/gen-inc/4x8inc-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-gemm/gen-inc/4x12inc-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-gemm/gen-inc/5x8inc-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-gemm/gen-inc/5x8inc-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-cortex-a55.S",
    "src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-cortex-a73.S",
    "src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-ld64.S",
    "src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-ld128.S",
    "src/f32-gemm/gen-inc/6x8inc-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-gemm/gen/1x8-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-gemm/gen/1x8-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-gemm/gen/1x8-minmax-aarch64-neonfma-ld64.S",
    "src/f32-gemm/gen/1x8-minmax-aarch64-neonfma-prfm-cortex-a53.S",
    "src/f32-gemm/gen/1x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-gemm/gen/1x12-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-gemm/gen/4x2-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-gemm/gen/4x2-minmax-aarch64-neonfma-ld64.S",
    "src/f32-gemm/gen/4x2-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-cortex-a55.S",
    "src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-ld64.S",
    "src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-ld128.S",
    "src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-prfm-cortex-a53.S",
    "src/f32-gemm/gen/4x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-gemm/gen/4x12-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-gemm/gen/5x8-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-gemm/gen/5x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-cortex-a55.S",
    "src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-cortex-a73.S",
    "src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-ld64.S",
    "src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-ld128.S",
    "src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-prfm-cortex-a53.S",
    "src/f32-gemm/gen/6x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-igemm/gen/1x8-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-igemm/gen/1x8-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-igemm/gen/1x8-minmax-aarch64-neonfma-prfm-cortex-a53.S",
    "src/f32-igemm/gen/1x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-igemm/gen/4x2-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-igemm/gen/4x2-minmax-aarch64-neonfma-ld64.S",
    "src/f32-igemm/gen/4x2-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-igemm/gen/4x8-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-igemm/gen/4x8-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-igemm/gen/4x8-minmax-aarch64-neonfma-ld64.S",
    "src/f32-igemm/gen/4x8-minmax-aarch64-neonfma-ld128.S",
    "src/f32-igemm/gen/4x8-minmax-aarch64-neonfma-prfm-cortex-a53.S",
    "src/f32-igemm/gen/4x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-igemm/gen/5x8-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-igemm/gen/5x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-igemm/gen/6x8-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-igemm/gen/6x8-minmax-aarch64-neonfma-cortex-a75.S",
    "src/f32-igemm/gen/6x8-minmax-aarch64-neonfma-ld64.S",
    "src/f32-igemm/gen/6x8-minmax-aarch64-neonfma-ld128.S",
    "src/f32-igemm/gen/6x8-minmax-aarch64-neonfma-prfm-cortex-a53.S",
    "src/f32-igemm/gen/6x8-minmax-aarch64-neonfma-prfm-cortex-a75.S",
    "src/f32-igemm/1x12-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-igemm/4x8-minmax-aarch64-neonfma-cortex-a55.S",
    "src/f32-igemm/4x12-minmax-aarch64-neonfma-cortex-a53.S",
    "src/f32-igemm/6x8-minmax-aarch64-neonfma-cortex-a55.S",
    "src/f32-igemm/6x8-minmax-aarch64-neonfma-cortex-a73.S",
    "src/qc8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
    "src/qc8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qc8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
    "src/qc8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal.S",
    "src/qc8-gemm/gen/1x16c4-minmax-fp32-aarch64-neondot-ld32.S",
    "src/qc8-gemm/gen/1x16c4-minmax-fp32-aarch64-neondot-ld64.S",
    "src/qc8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
    "src/qc8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qc8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
    "src/qc8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal.S",
    "src/qc8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mull.S",
    "src/qc8-gemm/gen/2x8c16-minmax-fp32-aarch64-neon-mlal.S",
    "src/qc8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-cortex-a53.S",
    "src/qc8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-ld64.S",
    "src/qc8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qc8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-ld64.S",
    "src/qc8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
    "src/qc8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld32.S",
    "src/qc8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld64.S",
    "src/qc8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
    "src/qc8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
    "src/qc8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qc8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
    "src/qc8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal.S",
    "src/qc8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
    "src/qc8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qc8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
    "src/qc8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal.S",
    "src/qc8-igemm/gen/2x8c16-minmax-fp32-aarch64-neon-mlal.S",
    "src/qc8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-cortex-a53.S",
    "src/qc8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-ld64.S",
    "src/qc8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qc8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-ld64.S",
    "src/qc8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
    "src/qc8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld64.S",
    "src/qc8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
    "src/qs8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
    "src/qs8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qs8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
    "src/qs8-gemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal.S",
    "src/qs8-gemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-cortex-a53.S",
    "src/qs8-gemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qs8-gemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-prfm.S",
    "src/qs8-gemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal.S",
    "src/qs8-gemm/gen/1x16c4-minmax-fp32-aarch64-neondot-ld32.S",
    "src/qs8-gemm/gen/1x16c4-minmax-fp32-aarch64-neondot-ld64.S",
    "src/qs8-gemm/gen/1x16c4-minmax-rndnu-aarch64-neondot-ld32.S",
    "src/qs8-gemm/gen/1x16c4-minmax-rndnu-aarch64-neondot-ld64.S",
    "src/qs8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
    "src/qs8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qs8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
    "src/qs8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal.S",
    "src/qs8-gemm/gen/2x8c8-minmax-fp32-aarch64-neon-mull.S",
    "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-cortex-a53.S",
    "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-prfm.S",
    "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal.S",
    "src/qs8-gemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mull.S",
    "src/qs8-gemm/gen/2x8c16-minmax-fp32-aarch64-neon-mlal.S",
    "src/qs8-gemm/gen/2x8c16-minmax-rndnu-aarch64-neon-mlal.S",
    "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
    "src/qs8-gemm/gen/4x8-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
    "src/qs8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-cortex-a53.S",
    "src/qs8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-ld64.S",
    "src/qs8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qs8-gemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-ld64.S",
    "src/qs8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
    "src/qs8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
    "src/qs8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qs8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
    "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
    "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld32.S",
    "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld64.S",
    "src/qs8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld32.S",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld64.S",
    "src/qs8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
    "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
    "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
    "src/qs8-igemm/gen/1x8c8-minmax-fp32-aarch64-neon-mlal.S",
    "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-cortex-a53.S",
    "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal-prfm.S",
    "src/qs8-igemm/gen/1x8c8-minmax-rndnu-aarch64-neon-mlal.S",
    "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-cortex-a53.S",
    "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal-prfm.S",
    "src/qs8-igemm/gen/2x8c8-minmax-fp32-aarch64-neon-mlal.S",
    "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-cortex-a53.S",
    "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-prfm-cortex-a53.S",
    "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal-prfm.S",
    "src/qs8-igemm/gen/2x8c8-minmax-rndnu-aarch64-neon-mlal.S",
    "src/qs8-igemm/gen/2x8c16-minmax-fp32-aarch64-neon-mlal.S",
    "src/qs8-igemm/gen/2x8c16-minmax-rndnu-aarch64-neon-mlal.S",
    "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
    "src/qs8-igemm/gen/4x8-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
    "src/qs8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-cortex-a53.S",
    "src/qs8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-ld64.S",
    "src/qs8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qs8-igemm/gen/4x16-minmax-fp32-aarch64-neon-mlal-lane-prfm-ld64.S",
    "src/qs8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
    "src/qs8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
    "src/qs8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qs8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
    "src/qs8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
    "src/qs8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld64.S",
    "src/qs8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
    "src/qs8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
    "src/qs8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld64.S",
    "src/qs8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
    "src/qu8-gemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
    "src/qu8-gemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-ld128.S",
    "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
    "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a75.S",
    "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
    "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a75.S",
    "src/qu8-gemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
    "src/qu8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
    "src/qu8-gemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
    "src/qu8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
    "src/qu8-gemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
    "src/qu8-igemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
    "src/qu8-igemm/gen/4x8c4-minmax-rndnu-aarch64-neondot-ld128.S",
    "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a53.S",
    "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-cortex-a75.S",
    "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-ld64.S",
    "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a53.S",
    "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-cortex-a75.S",
    "src/qu8-igemm/gen/4x16-minmax-rndnu-aarch64-neon-mlal-lane-prfm-ld64.S",
    "src/qu8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-cortex-a55.S",
    "src/qu8-igemm/gen/4x16c4-minmax-fp32-aarch64-neondot-ld128.S",
    "src/qu8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-cortex-a55.S",
    "src/qu8-igemm/gen/4x16c4-minmax-rndnu-aarch64-neondot-ld128.S",
]

JIT_AARCH32_SRCS = [
    "src/f32-gemm/4x8-aarch32-neon-cortex-a7.cc",
    "src/f32-gemm/4x8-aarch32-neon-cortex-a53.cc",
    "src/f32-gemm/4x8-aarch32-neon-cortex-a55.cc",
    "src/f32-gemm/4x8-aarch32-neon-cortex-a75.cc",
    "src/f32-gemm/4x8-aarch32-neon-ld64.cc",
    "src/f32-igemm/4x8-aarch32-neon-cortex-a7.cc",
    "src/f32-igemm/4x8-aarch32-neon-cortex-a53.cc",
    "src/f32-igemm/4x8-aarch32-neon-cortex-a55.cc",
    "src/f32-igemm/4x8-aarch32-neon-cortex-a75.cc",
    "src/f32-igemm/4x8-aarch32-neon-ld64.cc",
    "src/qc8-gemm/4x8-fp32-aarch32-neonv8-mlal-lane-ld64.cc",
    "src/qc8-gemm/4x8c4-fp32-aarch32-neondot-ld64.cc",
    "src/qc8-igemm/4x8-fp32-aarch32-neonv8-mlal-lane-ld64.cc",
    "src/qc8-igemm/4x8c4-fp32-aarch32-neondot-ld64.cc",
    "src/qs8-gemm/4x8-rndnu-aarch32-neon-mlal-lane-ld64.cc",
    "src/qs8-gemm/4x8c4-rndnu-aarch32-neondot-ld64.cc",
    "src/qs8-igemm/4x8-rndnu-aarch32-neon-mlal-lane-ld64.cc",
    "src/qs8-igemm/4x8c4-rndnu-aarch32-neondot-ld64.cc",
]

JIT_AARCH64_SRCS = [
    "src/f32-gemm/upto6x8-aarch64-neonfma-cortex-a75.cc",
    "src/f32-gemm/1x8-aarch64-neonfma-cortex-a75.cc",
    "src/f32-gemm/4x8-aarch64-neonfma-cortex-a75.cc",
    "src/f32-gemm/6x8-aarch64-neonfma-ld128.cc",
    "src/f32-igemm/upto6x8-aarch64-neonfma-cortex-a75.cc",
    "src/f32-igemm/1x8-aarch64-neonfma-cortex-a75.cc",
    "src/f32-igemm/4x8-aarch64-neonfma-cortex-a75.cc",
    "src/f32-igemm/6x8-aarch64-neonfma-ld128.cc",
]

cc_defaults {
    name: "xnnpack_internal_default",
    vendor_available: true,
    sdk_version: "current",
    local_include_dirs: [
        "include",
        "src",
    ],
    cflags: [
        "-std=c99",
        "-DXNN_LOG_LEVEL=2",
        "-DXNN_ENABLE_GEMM_M_SPECIALIZATION=1",
        "-DXNN_ENABLE_JIT=0",
        "-DXNN_ENABLE_SPARSE=1",
        "-DXNN_ENABLE_ASSEMBLY=1",
        "-DXNN_ENABLE_ARM_DOTPROD=0",
        "-Wno-unused-parameter",
        "-Wno-missing-field-initializers",
        "-Wno-pointer-arith",
        "-Wno-implicit-function-declaration",
        "-Wno-ignored-qualifiers",
    ],
    stl: "libc++_static",
}

cc_library_static {
    name: "xnnpack_tables",
    defaults: ["xnnpack_internal_default"],
    srcs: TABLE_SRCS,
}

cc_library_static {
    name: "xnnpack_logging",
    defaults: ["xnnpack_internal_default"],
    srcs: LOGGING_SRCS,
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libclog",
        "libpthreadpool",
    ],
    shared_libs: [
        "liblog",
    ],
}

cc_library_static {
    name: "xnnpack_params",
    defaults: ["xnnpack_internal_default"],
    srcs: [
        "src/params.c",
    ],
    static_libs: [
        "libpthreadpool",
    ],
}

cc_library_static {
    name: "xnnpack_microparams_init",
    defaults: ["xnnpack_internal_default"],
    srcs: [
        "src/microparams-init.c",
    ],
    header_libs: [
        "fp16_headers",
        "fxdiv_headers",
    ],
    static_libs: [
        "libpthreadpool",
    ],
}

cc_library_static {
    name: "xnnpack_allocator",
    defaults: ["xnnpack_internal_default"],
    srcs: [
        "src/allocator.c",
        "src/memory.c",
    ],
    header_libs: [
        "fp16_headers",
        "fxdiv_headers",
    ],
    static_libs: [
        "libclog",
        "libpthreadpool",
    ],
}

cc_library_static {
    name: "xnnpack_im2col",
    defaults: ["xnnpack_internal_default"],
    srcs: [
        "src/im2col.c",
    ],
}

cc_library_static {
    name: "xnnpack_indirection",
    defaults: ["xnnpack_internal_default"],
    srcs: [
        "src/indirection.c",
    ],
    header_libs: [
        "fp16_headers",
        "fxdiv_headers",
    ],
    static_libs: [
        "libpthreadpool",
    ],
}

cc_library_static {
    name: "xnnpack_packing",
    defaults: ["xnnpack_internal_default"],
    srcs: [
        "src/packing.c",
    ],
    header_libs: [
        "fp16_headers",
        "fxdiv_headers",
    ],
    static_libs: [
        "libpthreadpool",
    ],
}

cc_library_static {
    name: "xnnpack_mutex",
    defaults: ["xnnpack_internal_default"],
    srcs: [
        "src/mutex.c",
    ],
    static_libs: [
        "libclog",
        "libpthreadpool",
        "xnnpack_logging",
    ],
}

cc_library_static {
    name: "xnnpack_normalization",
    defaults: ["xnnpack_internal_default"],
    srcs: [
        "src/normalization.c",
    ],
    static_libs: [
        "libclog",
        "libpthreadpool",
        "xnnpack_logging",
    ],
}

cc_library_static {
    name: "xnnpack_cache",
    defaults: ["xnnpack_internal_default"],
    srcs: [
        "src/cache.c",
    ],
    static_libs: [
        "libclog",
        "libpthreadpool",
        "xnnpack_allocator",
        "xnnpack_logging",
        "xnnpack_mutex",
    ],
}

cc_library_static {
    name: "xnnpack_post_operation",
    defaults: ["xnnpack_internal_default"],
    srcs: [
        "src/operators/post-operation.c",
    ],
    static_libs: [
        "libclog",
        "libpthreadpool",
        "xnnpack_allocator",
        "xnnpack_params",
    ],
}

cc_library_static {
    name: "xnnpack_jit",
    defaults: ["xnnpack_internal_default"],
    srcs: [
        "src/jit/aarch32-assembler.cc",
        "src/jit/aarch64-assembler.cc",
        "src/jit/assembler.cc",
    ],
    arch: {
        arm: {
            srcs: JIT_AARCH32_SRCS,
        },
        arm64: {
            srcs: JIT_AARCH64_SRCS,
        },
    },
    static_libs: [
        "libclog",
        "libpthreadpool",
        "xnnpack_allocator",
        "xnnpack_logging",
        "xnnpack_params",
    ],
}

cc_library_static {
    name: "xnnpack_operators",
    defaults: ["xnnpack_internal_default"],
    srcs: OPERATOR_SRCS,
    header_libs: [
        "fp16_headers",
        "fxdiv_headers",
    ],
    static_libs: [
        "libclog",
        "libpthreadpool",
        "xnnpack_allocator",
        "xnnpack_cache",
        "xnnpack_logging",
        "xnnpack_microparams_init",
        "xnnpack_normalization",
        "xnnpack_packing",
        "xnnpack_post_operation",
    ],
    whole_static_libs: [
        "xnnpack_indirection",
    ],
}

cc_library_static {
    name: "xnnpack_subgraph",
    defaults: ["xnnpack_internal_default"],
    srcs: SUBGRAPH_SRCS,
    header_libs: [
        "fp16_headers",
        "fxdiv_headers",
    ],
    static_libs: [
        "libclog",
        "libpthreadpool",
        "xnnpack_allocator",
        "xnnpack_cache",
        "xnnpack_logging",
        "xnnpack_microparams_init",
        "xnnpack_normalization",
        "xnnpack_packing",
        "xnnpack_post_operation",
    ],
}

cc_library_static {
    name: "xnnpack_scalar_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    srcs: ALL_SCALAR_MICROKERNEL_SRCS,
    header_libs: [
        "fp16_headers",
        "fxdiv_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_scalar_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    srcs: PROD_SCALAR_PORTABLE_MICROKERNEL_SRCS,
    arch: {
        arm: {
            srcs: PROD_SCALAR_AARCH32_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
            ],
        },
        arm64: {
            srcs: PROD_SCALAR_AARCH32_MICROKERNEL_SRCS,
        },
        riscv64: {
            srcs: PROD_SCALAR_RISCV_MICROKERNEL_SRCS,
        },
    },
    header_libs: [
        "fp16_headers",
        "fxdiv_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_armsimd32_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    srcs: ALL_ARMSIMD32_MICROKERNEL_SRCS,
    arch: {
        arm: {
            cflags: [
                "-marm",
                "-march=armv6",
                "-mfpu=vfp",
                "-munaligned-access",
            ],
        },
        arm64: {
            enabled: false,
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_armsimd32_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    srcs: PROD_ARMSIMD32_MICROKERNEL_SRCS,
    arch: {
        arm: {
            cflags: [
                "-marm",
                "-march=armv6",
                "-mfpu=vfp",
                "-munaligned-access",
            ],
        },
        arm64: {
            enabled: false,
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neon_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    srcs: ALL_NEON_MICROKERNEL_SRCS,
    arch: {
        arm: {
            cflags: [
                "-marm",
                "-march=armv7-a",
                "-mfpu=neon",
            ],
        },
        arm64: {
            srcs: ALL_AARCH64_NEON_MICROKERNEL_SRCS,
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neon_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    srcs: PROD_NEON_MICROKERNEL_SRCS,
    arch: {
        arm: {
            cflags: [
                "-marm",
                "-march=armv7-a",
                "-mfpu=neon",
            ],
        },
        arm64: {
            srcs: PROD_AARCH64_NEON_MICROKERNEL_SRCS,
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neonfp16_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: ALL_NEONFP16_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
                "-march=armv7-a",
                "-mfpu=neon-fp16",
            ],
        },
        arm64: {
            srcs: ALL_NEONFP16_MICROKERNEL_SRCS,
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neonfp16_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: PROD_NEONFP16_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
                "-march=armv7-a",
                "-mfpu=neon-fp16",
            ],
        },
        arm64: {
            srcs: PROD_NEONFP16_MICROKERNEL_SRCS,
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neonfma_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: ALL_NEONFMA_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
                "-march=armv7-a",
                "-mfpu=neon-vfpv4",
            ],
        },
        arm64: {
            srcs: ALL_NEONFMA_MICROKERNEL_SRCS,
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neonfma_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: PROD_NEONFMA_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
                "-march=armv7-a",
                "-mfpu=neon-vfpv4",
            ],
        },
        arm64: {
            srcs: PROD_NEONFMA_MICROKERNEL_SRCS,
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neonv8_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: ALL_NEONV8_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
                "-march=armv8-a",
                "-mfpu=neon-fp-armv8",
            ],
        },
        arm64: {
            srcs: ALL_NEONV8_MICROKERNEL_SRCS,
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neonv8_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: PROD_NEONV8_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
                "-march=armv8-a",
                "-mfpu=neon-fp-armv8",
            ],
        },
        arm64: {
            srcs: PROD_NEONV8_MICROKERNEL_SRCS,
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neonfp16arith_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: ALL_NEONFP16ARITH_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
                "-march=armv8.2-a+fp16",
                "-mfpu=neon-fp-armv8",
            ],
        },
        arm64: {
            srcs: ALL_NEONFP16ARITH_MICROKERNEL_SRCS + ALL_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS,
            cflags: [
                "-march=armv8.2-a+fp16",
            ],
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neonfp16arith_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: PROD_NEONFP16ARITH_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
                "-march=armv8.2-a+fp16",
                "-mfpu=neon-fp-armv8",
            ],
        },
        arm64: {
            srcs: PROD_NEONFP16ARITH_MICROKERNEL_SRCS + PROD_AARCH64_NEONFP16ARITH_MICROKERNEL_SRCS,
            cflags: [
                "-march=armv8.2-a+fp16",
            ],
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neonbf16_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: PROD_NEONBF16_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
                "-march=armv8.2-a+bf16",
                "-mfpu=neon-fp-armv8",
            ],
        },
        arm64: {
            srcs: PROD_NEONBF16_MICROKERNEL_SRCS + PROD_AARCH64_NEONBF16_MICROKERNEL_SRCS,
            cflags: [
                "-march=armv8.2-a+bf16",
            ],
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neondot_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: ALL_NEONDOT_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
                "-march=armv8.2-a+dotprod",
                "-mfpu=neon-fp-armv8",
            ],
        },
        arm64: {
            srcs: ALL_NEONDOT_MICROKERNEL_SRCS,
            cflags: [
                "-march=armv8.2-a+dotprod",
            ],
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_neondot_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: PROD_NEONDOT_MICROKERNEL_SRCS,
            cflags: [
                "-marm",
                "-march=armv8.2-a+dotprod",
                "-mfpu=neon-fp-armv8",
            ],
        },
        arm64: {
            srcs: PROD_NEONDOT_MICROKERNEL_SRCS,
            cflags: [
                "-march=armv8.2-a+dotprod",
            ],
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_asm_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            srcs: AARCH32_ASM_MICROKERNEL_SRCS,
            asflags: [
                "-marm",
                "-march=armv8.2-a+dotprod",
                "-mfpu=neon-fp-armv8",
            ],
        },
        arm64: {
            srcs: AARCH64_ASM_MICROKERNEL_SRCS,
            asflags: [
                "-march=armv8.2-a+fp16+dotprod",
            ],
        },
        x86: {
            enabled: false,
        },
        x86_64: {
            enabled: false,
        },
    },
}

cc_library_static {
    name: "xnnpack_sse2_amalgam_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: [
                "src/amalgam/sse.c",
                "src/amalgam/sse2.c",
            ],
            cflags: [
                "-msse2",
            ],
        },
        x86_64: {
            srcs: [
                "src/amalgam/sse.c",
                "src/amalgam/sse2.c",
            ],
            cflags: [
                "-msse2",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_sse2_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: ALL_SSE_MICROKERNEL_SRCS + ALL_SSE2_MICROKERNEL_SRCS,
            cflags: [
                "-msse2",
            ],
        },
        x86_64: {
            srcs: ALL_SSE_MICROKERNEL_SRCS + ALL_SSE2_MICROKERNEL_SRCS,
            cflags: [
                "-msse2",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_sse2_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: ALL_SSE_MICROKERNEL_SRCS + ALL_SSE2_MICROKERNEL_SRCS,
            cflags: [
                "-msse2",
            ],
        },
        x86_64: {
            srcs: ALL_SSE_MICROKERNEL_SRCS + ALL_SSE2_MICROKERNEL_SRCS,
            cflags: [
                "-msse2",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_ssse3_amalgam_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: [
                "src/amalgam/ssse3.c",
            ],
            cflags: [
                "-mssse3",
            ],
        },
        x86_64: {
            srcs: [
                "src/amalgam/ssse3.c",
            ],
            cflags: [
                "-mssse3",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_ssse3_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: ALL_SSSE3_MICROKERNEL_SRCS,
            cflags: [
                "-mssse3",
            ],
        },
        x86_64: {
            srcs: ALL_SSSE3_MICROKERNEL_SRCS,
            cflags: [
                "-mssse3",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_ssse3_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: PROD_SSSE3_MICROKERNEL_SRCS,
            cflags: [
                "-mssse3",
            ],
        },
        x86_64: {
            srcs: PROD_SSSE3_MICROKERNEL_SRCS,
            cflags: [
                "-mssse3",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_sse41_amalgam_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: [
                "src/amalgam/sse41.c",
            ],
            cflags: [
                "-msse4.1",
            ],
        },
        x86_64: {
            srcs: [
                "src/amalgam/sse41.c",
            ],
            cflags: [
                "-msse4.1",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_sse41_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: ALL_SSE41_MICROKERNEL_SRCS,
            cflags: [
                "-msse4.1",
            ],
        },
        x86_64: {
            srcs: ALL_SSE41_MICROKERNEL_SRCS,
            cflags: [
                "-msse4.1",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_sse41_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: PROD_SSE41_MICROKERNEL_SRCS,
            cflags: [
                "-msse4.1",
            ],
        },
        x86_64: {
            srcs: PROD_SSE41_MICROKERNEL_SRCS,
            cflags: [
                "-msse4.1",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx_amalgam_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: [
                "src/amalgam/avx.c",
            ],
            cflags: [
                "-mavx",
            ],
        },
        x86_64: {
            srcs: [
                "src/amalgam/avx.c",
            ],
            cflags: [
                "-mavx",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: ALL_AVX_MICROKERNEL_SRCS,
            cflags: [
                "-mavx",
            ],
        },
        x86_64: {
            srcs: ALL_AVX_MICROKERNEL_SRCS,
            cflags: [
                "-mavx",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: PROD_AVX_MICROKERNEL_SRCS,
            cflags: [
                "-mavx",
            ],
        },
        x86_64: {
            srcs: PROD_AVX_MICROKERNEL_SRCS,
            cflags: [
                "-mavx",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_f16c_amalgam_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: [
                "src/amalgam/f16c.c",
            ],
            cflags: [
                "-mf16c",
            ],
        },
        x86_64: {
            srcs: [
                "src/amalgam/f16c.c",
            ],
            cflags: [
                "-mf16c",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_f16c_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: ALL_F16C_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
            ],
        },
        x86_64: {
            srcs: ALL_F16C_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_f16c_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: PROD_F16C_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
            ],
        },
        x86_64: {
            srcs: PROD_F16C_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_xop_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: ALL_XOP_MICROKERNEL_SRCS,
            cflags: [
                "-mxop",
            ],
        },
        x86_64: {
            srcs: ALL_XOP_MICROKERNEL_SRCS,
            cflags: [
                "-mxop",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_xop_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: PROD_XOP_MICROKERNEL_SRCS,
            cflags: [
                "-mxop",
            ],
        },
        x86_64: {
            srcs: PROD_XOP_MICROKERNEL_SRCS,
            cflags: [
                "-mxop",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_fma3_amalgam_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: [
                "src/amalgam/fma3.c",
            ],
            cflags: [
                "-mf16c",
                "-mfma",
            ],
        },
        x86_64: {
            srcs: [
                "src/amalgam/fma3.c",
            ],
            cflags: [
                "-mf16c",
                "-mfma",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_fma3_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: ALL_FMA3_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
                "-mfma",
            ],
        },
        x86_64: {
            srcs: ALL_FMA3_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
                "-mfma",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_fma3_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: PROD_FMA3_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
                "-mfma",
            ],
        },
        x86_64: {
            srcs: PROD_FMA3_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
                "-mfma",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx2_amalgam_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: [
                "src/amalgam/avx2.c",
            ],
            cflags: [
                "-mf16c",
                "-mfma",
                "-mavx2",
            ],
        },
        x86_64: {
            srcs: [
                "src/amalgam/avx2.c",
            ],
            cflags: [
                "-mf16c",
                "-mfma",
                "-mavx2",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx2_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: ALL_AVX2_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
                "-mfma",
                "-mavx2",
            ],
        },
        x86_64: {
            srcs: ALL_AVX2_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
                "-mfma",
                "-mavx2",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx2_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: PROD_AVX2_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
                "-mfma",
                "-mavx2",
            ],
        },
        x86_64: {
            srcs: PROD_AVX2_MICROKERNEL_SRCS,
            cflags: [
                "-mf16c",
                "-mfma",
                "-mavx2",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx512skx_amalgam_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: [
                "src/amalgam/avx512skx.c",
            ],
            cflags: [
                "-mavx512f",
                "-mavx512cd",
                "-mavx512bw",
                "-mavx512dq",
                "-mavx512vl",
            ],
        },
        x86_64: {
            srcs: [
                "src/amalgam/avx512skx.c",
            ],
            cflags: [
                "-mavx512f",
                "-mavx512cd",
                "-mavx512bw",
                "-mavx512dq",
                "-mavx512vl",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx512skx_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: ALL_AVX512SKX_MICROKERNEL_SRCS,
            cflags: [
                "-mavx512f",
                "-mavx512cd",
                "-mavx512bw",
                "-mavx512dq",
                "-mavx512vl",
            ],
        },
        x86_64: {
            srcs: ALL_AVX512SKX_MICROKERNEL_SRCS,
            cflags: [
                "-mavx512f",
                "-mavx512cd",
                "-mavx512bw",
                "-mavx512dq",
                "-mavx512vl",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx512skx_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: PROD_AVX512SKX_MICROKERNEL_SRCS,
            cflags: [
                "-mavx512f",
                "-mavx512cd",
                "-mavx512bw",
                "-mavx512dq",
                "-mavx512vl",
            ],
        },
        x86_64: {
            srcs: PROD_AVX512SKX_MICROKERNEL_SRCS,
            cflags: [
                "-mavx512f",
                "-mavx512cd",
                "-mavx512bw",
                "-mavx512dq",
                "-mavx512vl",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx512f_amalgam_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: [
                "src/amalgam/avx512f.c",
            ],
            cflags: [
                "-mavx512f",
            ],
        },
        x86_64: {
            srcs: [
                "src/amalgam/avx512f.c",
            ],
            cflags: [
                "-mavx512f",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx512f_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: ALL_AVX512F_MICROKERNEL_SRCS,
            cflags: [
                "-mavx512f",
            ],
        },
        x86_64: {
            srcs: ALL_AVX512F_MICROKERNEL_SRCS,
            cflags: [
                "-mavx512f",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_avx512f_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            enabled: false,
        },
        arm64: {
            enabled: false,
        },
        x86: {
            srcs: PROD_AVX512F_MICROKERNEL_SRCS,
            cflags: [
                "-mavx512f",
            ],
        },
        x86_64: {
            srcs: PROD_AVX512F_MICROKERNEL_SRCS,
            cflags: [
                "-mavx512f",
            ],
        },
    },
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libpthreadpool",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_amalgam_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            whole_static_libs: [
                "xnnpack_armsimd32_prod_microkernels",
                "xnnpack_neon_prod_microkernels",
                "xnnpack_neonfp16_prod_microkernels",
                "xnnpack_neonfma_prod_microkernels",
                "xnnpack_neonv8_prod_microkernels",
                "xnnpack_asm_microkernels",
            ],
        },
        arm64: {
            whole_static_libs: [
                "xnnpack_neon_prod_microkernels",
                "xnnpack_neonfp16_prod_microkernels",
                "xnnpack_neonfma_prod_microkernels",
                "xnnpack_neonv8_prod_microkernels",
                "xnnpack_asm_microkernels",
            ],
        },
        x86: {
            whole_static_libs: [
                "xnnpack_sse2_amalgam_microkernels",
                "xnnpack_ssse3_amalgam_microkernels",
                "xnnpack_sse41_amalgam_microkernels",
                "xnnpack_avx_amalgam_microkernels",
                "xnnpack_f16c_amalgam_microkernels",
                "xnnpack_fma3_amalgam_microkernels",
                "xnnpack_avx2_amalgam_microkernels",
                "xnnpack_avx512f_amalgam_microkernels",
                "xnnpack_avx512skx_amalgam_microkernels",
            ],
        },
        x86_64: {
            whole_static_libs: [
                "xnnpack_sse2_amalgam_microkernels",
                "xnnpack_ssse3_amalgam_microkernels",
                "xnnpack_sse41_amalgam_microkernels",
                "xnnpack_avx_amalgam_microkernels",
                "xnnpack_f16c_amalgam_microkernels",
                "xnnpack_fma3_amalgam_microkernels",
                "xnnpack_avx2_amalgam_microkernels",
                "xnnpack_avx512f_amalgam_microkernels",
                "xnnpack_avx512skx_amalgam_microkernels",
            ],
        },
    },
    whole_static_libs: [
        "xnnpack_scalar_prod_microkernels",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_bench_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            whole_static_libs: [
                "xnnpack_armsimd32_bench_microkernels",
                "xnnpack_neon_bench_microkernels",
                "xnnpack_neonfp16_bench_microkernels",
                "xnnpack_neonfma_bench_microkernels",
                "xnnpack_neonv8_bench_microkernels",
                "xnnpack_asm_microkernels",
            ],
        },
        arm64: {
            whole_static_libs: [
                "xnnpack_neon_bench_microkernels",
                "xnnpack_neonfp16_bench_microkernels",
                "xnnpack_neonfma_bench_microkernels",
                "xnnpack_neonv8_bench_microkernels",
                "xnnpack_asm_microkernels",
            ],
        },
        x86: {
            whole_static_libs: [
                "xnnpack_sse2_bench_microkernels",
                "xnnpack_ssse3_bench_microkernels",
                "xnnpack_sse41_bench_microkernels",
                "xnnpack_avx_bench_microkernels",
                "xnnpack_f16c_bench_microkernels",
                "xnnpack_xop_bench_microkernels",
                "xnnpack_fma3_bench_microkernels",
                "xnnpack_avx2_bench_microkernels",
                "xnnpack_avx512f_bench_microkernels",
                "xnnpack_avx512skx_bench_microkernels",
            ],
        },
        x86_64: {
            whole_static_libs: [
                "xnnpack_sse2_bench_microkernels",
                "xnnpack_ssse3_bench_microkernels",
                "xnnpack_sse41_bench_microkernels",
                "xnnpack_avx_bench_microkernels",
                "xnnpack_f16c_bench_microkernels",
                "xnnpack_xop_bench_microkernels",
                "xnnpack_fma3_bench_microkernels",
                "xnnpack_avx2_bench_microkernels",
                "xnnpack_avx512f_bench_microkernels",
                "xnnpack_avx512skx_bench_microkernels",
            ],
        },
    },
    whole_static_libs: [
        "xnnpack_scalar_bench_microkernels",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "xnnpack_prod_microkernels",
    defaults: ["xnnpack_internal_default"],
    arch: {
        arm: {
            whole_static_libs: [
                "xnnpack_armsimd32_prod_microkernels",
                "xnnpack_neon_prod_microkernels",
                "xnnpack_neonfp16_prod_microkernels",
                "xnnpack_neonfma_prod_microkernels",
                "xnnpack_neonv8_prod_microkernels",
                "xnnpack_asm_microkernels",
            ],
        },
        arm64: {
            whole_static_libs: [
                "xnnpack_neon_prod_microkernels",
                "xnnpack_neonfp16_prod_microkernels",
                "xnnpack_neonfma_prod_microkernels",
                "xnnpack_neonv8_prod_microkernels",
                "xnnpack_asm_microkernels",
            ],
        },
        x86: {
            whole_static_libs: [
                "xnnpack_sse2_prod_microkernels",
                "xnnpack_ssse3_prod_microkernels",
                "xnnpack_sse41_prod_microkernels",
                "xnnpack_avx_prod_microkernels",
                "xnnpack_f16c_prod_microkernels",
                "xnnpack_xop_prod_microkernels",
                "xnnpack_fma3_prod_microkernels",
                "xnnpack_avx2_prod_microkernels",
                "xnnpack_avx512f_prod_microkernels",
                "xnnpack_avx512skx_prod_microkernels",
            ],
        },
        x86_64: {
            whole_static_libs: [
                "xnnpack_sse2_prod_microkernels",
                "xnnpack_ssse3_prod_microkernels",
                "xnnpack_sse41_prod_microkernels",
                "xnnpack_avx_prod_microkernels",
                "xnnpack_f16c_prod_microkernels",
                "xnnpack_xop_prod_microkernels",
                "xnnpack_fma3_prod_microkernels",
                "xnnpack_avx2_prod_microkernels",
                "xnnpack_avx512f_prod_microkernels",
                "xnnpack_avx512skx_prod_microkernels",
            ],
        },
    },
    whole_static_libs: [
        "xnnpack_scalar_prod_microkernels",
        "xnnpack_tables",
    ],
}

cc_library_static {
    name: "libXNNPACK",
    defaults: ["xnnpack_internal_default"],
    export_include_dirs: ["include"],
    srcs: [
        "src/init.c",
    ],
    header_libs: [
        "fp16_headers",
    ],
    whole_static_libs: [
        "libclog",
        "libcpuinfo",
        "libpthreadpool",
        "xnnpack_allocator",
        "xnnpack_cache",
        "xnnpack_jit",
        "xnnpack_prod_microkernels",
        "xnnpack_operators",
        "xnnpack_logging",
        "xnnpack_microparams_init",
        "xnnpack_mutex",
        "xnnpack_normalization",
        "xnnpack_packing",
        "xnnpack_params",
        "xnnpack_subgraph",
    ],
}

// Tests and benchmarks
cc_defaults {
    name: "xnnpack_tests_default",
    vendor_available: true,
    stl: "libc++_static",
    local_include_dirs: [
        "bench",
        "models",
        "test",
        "src",
    ],
    cflags: [
        "-Wno-missing-field-initializers",
        "-Wno-unused-function",
        "-Wno-unused-parameter",
        "-Wno-unused-private-field",
    ],
    header_libs: [
        "fp16_headers",
    ],
    static_libs: [
        "libXNNPACK",
        "libpthreadpool",
        "libgmock",
        "xnnpack_allocator",
        "xnnpack_cache",
        "xnnpack_microparams_init",
        "xnnpack_mutex",
        "xnnpack_normalization",
        "xnnpack_params",
    ],
    shared_libs: [
        "liblog",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v1_fp32",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp32-mobilenet-v1.cc",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v1_fp32_sparse",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp32-sparse-mobilenet-v1.cc",
    ],
}

cc_library_static {
    name: "xnnpack_qc8_mobilenet_v1",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/qc8-mobilenet-v1.cc",
    ],
}

cc_library_static {
    name: "xnnpack_qc8_mobilenet_v2",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/qc8-mobilenet-v2.cc",
    ],
}

cc_library_static {
    name: "xnnpack_qs8_mobilenet_v1",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/qs8-mobilenet-v1.cc",
    ],
}

cc_library_static {
    name: "xnnpack_qu8_mobilenet_v1",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/qu8-mobilenet-v1.cc",
    ],
}

cc_library_static {
    name: "xnnpack_qu8_mobilenet_v2",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/qu8-mobilenet-v2.cc",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v1_fp16",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp16-mobilenet-v1.cc",
    ],
}

cc_library_static {
    name: "xnnpack_qs8_mobilenet_v2",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/qs8-mobilenet-v2.cc",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v2_fp32",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp32-mobilenet-v2.cc",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v2_fp32_sparse",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp32-sparse-mobilenet-v2.cc",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v2_fp16",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp16-mobilenet-v2.cc",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v3_large_fp32",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp32-mobilenet-v3-large.cc",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v3_large_fp32_sparse",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp32-sparse-mobilenet-v3-large.cc",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v3_large_fp16",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp16-mobilenet-v3-large.cc",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v3_small_fp32",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp32-mobilenet-v3-small.cc",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v3_small_fp32_sparse",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp32-sparse-mobilenet-v3-small.cc",
    ],
}

cc_library_static {
    name: "xnnpack_mobilenet_v3_small_fp16",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "models/fp16-mobilenet-v3-small.cc",
    ],
}

cc_benchmark {
    name: "xnnpack_end2end_bench",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "bench/end2end.cc",
        "bench/utils.cc",
    ],
    cflags: [
        "-Wno-unused-result",
    ],
    static_libs: [
        "libcpuinfo",
        "libgoogle-benchmark",
        "xnnpack_qc8_mobilenet_v1",
        "xnnpack_qc8_mobilenet_v2",
        "xnnpack_qs8_mobilenet_v1",
        "xnnpack_mobilenet_v1_fp32",
        "xnnpack_mobilenet_v1_fp32_sparse",
        "xnnpack_mobilenet_v1_fp16",
        "xnnpack_qs8_mobilenet_v2",
        "xnnpack_mobilenet_v2_fp32",
        "xnnpack_mobilenet_v2_fp32_sparse",
        "xnnpack_mobilenet_v2_fp16",
        "xnnpack_mobilenet_v3_large_fp32",
        "xnnpack_mobilenet_v3_large_fp32_sparse",
        "xnnpack_mobilenet_v3_large_fp16",
        "xnnpack_mobilenet_v3_small_fp32",
        "xnnpack_mobilenet_v3_small_fp32_sparse",
        "xnnpack_mobilenet_v3_small_fp16",
        "xnnpack_qu8_mobilenet_v1",
        "xnnpack_qu8_mobilenet_v2",
    ],
}

cc_test {
    name: "xnnpack_abs_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/abs-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_add_nd_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/add-nd.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_argmax_pooling_nhwc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/argmax-pooling-nhwc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_average_pooling_nhwc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/average-pooling-nhwc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_bankers_rounding_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/bankers-rounding-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_ceiling_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/ceiling-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_channel_shuffle_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/channel-shuffle-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_clamp_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/clamp-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_constant_pad_nd_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/constant-pad-nd.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_convolution_nhwc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/convolution-nhwc.cc",
        "test/convolution-test-helpers.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_convolution_nchw_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/convolution-nchw.cc",
        "test/convolution-test-helpers.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_copy_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/copy-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_deconvolution_nhwc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/deconvolution-nhwc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_divide_nd_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/divide-nd.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_fully_connected_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/fully-connected-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_floor_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/floor-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_global_average_pooling_nwc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/global-average-pooling-nwc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_global_average_pooling_ncw_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/global-average-pooling-ncw.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_hardswish_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/hardswish-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_leaky_relu_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/leaky-relu-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_max_pooling_nhwc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/max-pooling-nhwc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_maximum_nd_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/maximum-nd.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_minimum_nd_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/minimum-nd.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_multiply_nd_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/multiply-nd.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_negate_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/negate-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_prelu_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/prelu-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_resize_bilinear_nhwc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/resize-bilinear-nhwc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_sigmoid_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/sigmoid-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_softmax_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/softmax-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_square_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/square-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_square_root_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/square-root-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_square_difference_nd_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/squared-difference-nd.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_subtract_nd_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/subtract-nd.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_truncation_nc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/truncation-nc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}

cc_test {
    name: "xnnpack_unpooling_nhwc_test",
    defaults: ["xnnpack_tests_default"],
    srcs: [
        "test/unpooling-nhwc.cc",
    ],
    test_suites: [
        "general-tests",
    ],
}