1 /*
2 * Single-precision vector atanh(x) function.
3 *
4 * Copyright (c) 2022-2023, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6 */
7
8 #include "v_math.h"
9 #include "mathlib.h"
10 #include "pl_sig.h"
11 #include "pl_test.h"
12
13 #if V_SUPPORTED
14
15 #include "v_log1pf_inline.h"
16
17 #define AbsMask 0x7fffffff
18 #define Half 0x3f000000
19 #define One 0x3f800000
20 #define TinyBound 0x39800000 /* 0x1p-12, below which atanhf(x) rounds to x. */
21
22 /* Approximation for vector single-precision atanh(x) using modified log1p.
23 The maximum error is 3.08 ULP:
24 __v_atanhf(0x1.ff215p-5) got 0x1.ffcb7cp-5
25 want 0x1.ffcb82p-5. */
V_NAME(atanhf)26 VPCS_ATTR v_f32_t V_NAME (atanhf) (v_f32_t x)
27 {
28 v_u32_t ix = v_as_u32_f32 (x);
29 v_f32_t halfsign
30 = v_as_f32_u32 (v_bsl_u32 (v_u32 (AbsMask), v_u32 (Half), ix));
31 v_u32_t iax = ix & AbsMask;
32
33 v_f32_t ax = v_as_f32_u32 (iax);
34
35 #if WANT_SIMD_EXCEPT
36 v_u32_t special = v_cond_u32 ((iax >= One) | (iax <= TinyBound));
37 /* Side-step special cases by setting those lanes to 0, which will trigger no
38 exceptions. These will be fixed up later. */
39 if (unlikely (v_any_u32 (special)))
40 ax = v_sel_f32 (special, v_f32 (0), ax);
41 #else
42 v_u32_t special = v_cond_u32 (iax >= One);
43 #endif
44
45 v_f32_t y = halfsign * log1pf_inline ((2 * ax) / (1 - ax));
46
47 if (unlikely (v_any_u32 (special)))
48 return v_call_f32 (atanhf, x, y, special);
49 return y;
50 }
51 VPCS_ALIAS
52
53 PL_SIG (V, F, 1, atanh, -1.0, 1.0)
54 PL_TEST_ULP (V_NAME (atanhf), 2.59)
55 PL_TEST_EXPECT_FENV (V_NAME (atanhf), WANT_SIMD_EXCEPT)
56 PL_TEST_INTERVAL_C (V_NAME (atanhf), 0, 0x1p-12, 500, 0)
57 PL_TEST_INTERVAL_C (V_NAME (atanhf), 0x1p-12, 1, 200000, 0)
58 PL_TEST_INTERVAL_C (V_NAME (atanhf), 1, inf, 1000, 0)
59 PL_TEST_INTERVAL_C (V_NAME (atanhf), -0, -0x1p-12, 500, 0)
60 PL_TEST_INTERVAL_C (V_NAME (atanhf), -0x1p-12, -1, 200000, 0)
61 PL_TEST_INTERVAL_C (V_NAME (atanhf), -1, -inf, 1000, 0)
62 #endif
63