1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <inttypes.h>
25 #include <stdio.h>
26
27 #include "CUnit/Basic.h"
28
29 #include "util_math.h"
30
31 #include "amdgpu_drm.h"
32 #include "amdgpu_internal.h"
33 #include "amdgpu_test.h"
34 #include "decode_messages.h"
35
36 /* jpeg registers */
37 #define mmUVD_JPEG_CNTL 0x0200
38 #define mmUVD_JPEG_RB_BASE 0x0201
39 #define mmUVD_JPEG_RB_WPTR 0x0202
40 #define mmUVD_JPEG_RB_RPTR 0x0203
41 #define mmUVD_JPEG_RB_SIZE 0x0204
42 #define mmUVD_JPEG_TIER_CNTL2 0x021a
43 #define mmUVD_JPEG_UV_TILING_CTRL 0x021c
44 #define mmUVD_JPEG_TILING_CTRL 0x021e
45 #define mmUVD_JPEG_OUTBUF_RPTR 0x0220
46 #define mmUVD_JPEG_OUTBUF_WPTR 0x0221
47 #define mmUVD_JPEG_PITCH 0x0222
48 #define mmUVD_JPEG_INT_EN 0x0229
49 #define mmUVD_JPEG_UV_PITCH 0x022b
50 #define mmUVD_JPEG_INDEX 0x023e
51 #define mmUVD_JPEG_DATA 0x023f
52 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0438
53 #define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0439
54 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x045a
55 #define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x045b
56 #define mmUVD_CTX_INDEX 0x0528
57 #define mmUVD_CTX_DATA 0x0529
58 #define mmUVD_SOFT_RESET 0x05a0
59
60 #define vcnipUVD_JPEG_DEC_SOFT_RST 0x402f
61 #define vcnipUVD_JRBC_IB_COND_RD_TIMER 0x408e
62 #define vcnipUVD_JRBC_IB_REF_DATA 0x408f
63 #define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x40e1
64 #define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x40e0
65 #define vcnipUVD_JPEG_RB_BASE 0x4001
66 #define vcnipUVD_JPEG_RB_SIZE 0x4004
67 #define vcnipUVD_JPEG_RB_WPTR 0x4002
68 #define vcnipUVD_JPEG_PITCH 0x401f
69 #define vcnipUVD_JPEG_UV_PITCH 0x4020
70 #define vcnipJPEG_DEC_ADDR_MODE 0x4027
71 #define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE 0x4024
72 #define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE 0x4025
73 #define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x40e3
74 #define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x40e2
75 #define vcnipUVD_JPEG_INDEX 0x402c
76 #define vcnipUVD_JPEG_DATA 0x402d
77 #define vcnipUVD_JPEG_TIER_CNTL2 0x400f
78 #define vcnipUVD_JPEG_OUTBUF_RPTR 0x401e
79 #define vcnipUVD_JPEG_OUTBUF_CNTL 0x401c
80 #define vcnipUVD_JPEG_INT_EN 0x400a
81 #define vcnipUVD_JPEG_CNTL 0x4000
82 #define vcnipUVD_JPEG_RB_RPTR 0x4003
83 #define vcnipUVD_JPEG_OUTBUF_WPTR 0x401d
84
85
86 #define RDECODE_PKT_REG_J(x) ((unsigned)(x)&0x3FFFF)
87 #define RDECODE_PKT_RES_J(x) (((unsigned)(x)&0x3F) << 18)
88 #define RDECODE_PKT_COND_J(x) (((unsigned)(x)&0xF) << 24)
89 #define RDECODE_PKT_TYPE_J(x) (((unsigned)(x)&0xF) << 28)
90 #define RDECODE_PKTJ(reg, cond, type) (RDECODE_PKT_REG_J(reg) | \
91 RDECODE_PKT_RES_J(0) | \
92 RDECODE_PKT_COND_J(cond) | \
93 RDECODE_PKT_TYPE_J(type))
94
95 #define UVD_BASE_INST0_SEG1 0x00007E00
96 #define SOC15_REG_ADDR(reg) (UVD_BASE_INST0_SEG1 + reg)
97
98 #define COND0 0
99 #define COND1 1
100 #define COND3 3
101 #define TYPE0 0
102 #define TYPE1 1
103 #define TYPE3 3
104 #define JPEG_DEC_DT_PITCH 0x100
105 #define JPEG_DEC_BSD_SIZE 0x180
106 #define JPEG_DEC_LUMA_OFFSET 0
107 #define JPEG_DEC_CHROMA_OFFSET 0x1000
108 #define JPEG_DEC_SUM 4096
109 #define IB_SIZE 4096
110 #define MAX_RESOURCES 16
111
112 struct amdgpu_jpeg_bo {
113 amdgpu_bo_handle handle;
114 amdgpu_va_handle va_handle;
115 uint64_t addr;
116 uint64_t size;
117 uint8_t *ptr;
118 };
119
120 static amdgpu_device_handle device_handle;
121 static uint32_t major_version;
122 static uint32_t minor_version;
123 static uint32_t family_id;
124 static uint32_t chip_rev;
125 static uint32_t chip_id;
126 static uint32_t asic_id;
127 static uint32_t chip_rev;
128 static uint32_t chip_id;
129
130 static amdgpu_context_handle context_handle;
131 static amdgpu_bo_handle ib_handle;
132 static amdgpu_va_handle ib_va_handle;
133 static uint64_t ib_mc_address;
134 static uint32_t *ib_cpu;
135 static uint32_t len;
136
137 static amdgpu_bo_handle resources[MAX_RESOURCES];
138 static unsigned num_resources;
139 bool jpeg_direct_reg;
140
141 static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type,
142 uint32_t val);
143 static void send_cmd_bitstream(uint64_t addr);
144 static void send_cmd_target(uint64_t addr);
145 static void send_cmd_bitstream_direct(uint64_t addr);
146 static void send_cmd_target_direct(uint64_t addr);
147
148 static void amdgpu_cs_jpeg_decode(void);
149
150 CU_TestInfo jpeg_tests[] = {
151 {"JPEG decode", amdgpu_cs_jpeg_decode},
152 CU_TEST_INFO_NULL,
153 };
154
suite_jpeg_tests_enable(void)155 CU_BOOL suite_jpeg_tests_enable(void)
156 {
157 struct drm_amdgpu_info_hw_ip info;
158 int r;
159
160 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version,
161 &device_handle))
162 return CU_FALSE;
163
164 family_id = device_handle->info.family_id;
165 asic_id = device_handle->info.asic_id;
166 chip_rev = device_handle->info.chip_rev;
167 chip_id = device_handle->info.chip_external_rev;
168
169 r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_JPEG, 0, &info);
170
171 if (amdgpu_device_deinitialize(device_handle))
172 return CU_FALSE;
173
174 if (r != 0 || !info.available_rings ||
175 (family_id < AMDGPU_FAMILY_RV &&
176 (family_id == AMDGPU_FAMILY_AI &&
177 (chip_id - chip_rev) < 0x32))) { /* Arcturus */
178 printf("\n\nThe ASIC NOT support JPEG, suite disabled\n");
179 return CU_FALSE;
180 }
181
182 if (family_id == AMDGPU_FAMILY_RV) {
183 if (chip_id >= (chip_rev + 0x91))
184 jpeg_direct_reg = true;
185 else
186 jpeg_direct_reg = false;
187 } else if (family_id == AMDGPU_FAMILY_NV)
188 jpeg_direct_reg = true;
189 else
190 return CU_FALSE;
191
192 return CU_TRUE;
193 }
194
suite_jpeg_tests_init(void)195 int suite_jpeg_tests_init(void)
196 {
197 int r;
198
199 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version,
200 &device_handle);
201 if (r)
202 return CUE_SINIT_FAILED;
203
204 family_id = device_handle->info.family_id;
205
206 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
207 if (r)
208 return CUE_SINIT_FAILED;
209
210 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
211 AMDGPU_GEM_DOMAIN_GTT, 0, &ib_handle,
212 (void **)&ib_cpu, &ib_mc_address, &ib_va_handle);
213 if (r)
214 return CUE_SINIT_FAILED;
215
216 return CUE_SUCCESS;
217 }
218
suite_jpeg_tests_clean(void)219 int suite_jpeg_tests_clean(void)
220 {
221 int r;
222
223 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, ib_mc_address, IB_SIZE);
224 if (r)
225 return CUE_SCLEAN_FAILED;
226
227 r = amdgpu_cs_ctx_free(context_handle);
228 if (r)
229 return CUE_SCLEAN_FAILED;
230
231 r = amdgpu_device_deinitialize(device_handle);
232 if (r)
233 return CUE_SCLEAN_FAILED;
234
235 return CUE_SUCCESS;
236 }
237
submit(unsigned ndw,unsigned ip)238 static int submit(unsigned ndw, unsigned ip)
239 {
240 struct amdgpu_cs_request ibs_request = {0};
241 struct amdgpu_cs_ib_info ib_info = {0};
242 struct amdgpu_cs_fence fence_status = {0};
243 uint32_t expired;
244 int r;
245
246 ib_info.ib_mc_address = ib_mc_address;
247 ib_info.size = ndw;
248
249 ibs_request.ip_type = ip;
250
251 r = amdgpu_bo_list_create(device_handle, num_resources, resources, NULL,
252 &ibs_request.resources);
253 if (r)
254 return r;
255
256 ibs_request.number_of_ibs = 1;
257 ibs_request.ibs = &ib_info;
258 ibs_request.fence_info.handle = NULL;
259
260 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
261 if (r)
262 return r;
263
264 r = amdgpu_bo_list_destroy(ibs_request.resources);
265 if (r)
266 return r;
267
268 fence_status.context = context_handle;
269 fence_status.ip_type = ip;
270 fence_status.fence = ibs_request.seq_no;
271
272 r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE, 0,
273 &expired);
274 if (r)
275 return r;
276
277 return 0;
278 }
279
alloc_resource(struct amdgpu_jpeg_bo * jpeg_bo,unsigned size,unsigned domain)280 static void alloc_resource(struct amdgpu_jpeg_bo *jpeg_bo, unsigned size,
281 unsigned domain)
282 {
283 struct amdgpu_bo_alloc_request req = {0};
284 amdgpu_bo_handle buf_handle;
285 amdgpu_va_handle va_handle;
286 uint64_t va = 0;
287 int r;
288
289 req.alloc_size = ALIGN(size, 4096);
290 req.preferred_heap = domain;
291 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
292 CU_ASSERT_EQUAL(r, 0);
293 r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general,
294 req.alloc_size, 1, 0, &va, &va_handle, 0);
295 CU_ASSERT_EQUAL(r, 0);
296 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_MAP);
297 CU_ASSERT_EQUAL(r, 0);
298 jpeg_bo->addr = va;
299 jpeg_bo->handle = buf_handle;
300 jpeg_bo->size = req.alloc_size;
301 jpeg_bo->va_handle = va_handle;
302 r = amdgpu_bo_cpu_map(jpeg_bo->handle, (void **)&jpeg_bo->ptr);
303 CU_ASSERT_EQUAL(r, 0);
304 memset(jpeg_bo->ptr, 0, size);
305 r = amdgpu_bo_cpu_unmap(jpeg_bo->handle);
306 CU_ASSERT_EQUAL(r, 0);
307 }
308
free_resource(struct amdgpu_jpeg_bo * jpeg_bo)309 static void free_resource(struct amdgpu_jpeg_bo *jpeg_bo)
310 {
311 int r;
312
313 r = amdgpu_bo_va_op(jpeg_bo->handle, 0, jpeg_bo->size, jpeg_bo->addr, 0,
314 AMDGPU_VA_OP_UNMAP);
315 CU_ASSERT_EQUAL(r, 0);
316
317 r = amdgpu_va_range_free(jpeg_bo->va_handle);
318 CU_ASSERT_EQUAL(r, 0);
319
320 r = amdgpu_bo_free(jpeg_bo->handle);
321 CU_ASSERT_EQUAL(r, 0);
322 memset(jpeg_bo, 0, sizeof(*jpeg_bo));
323 }
324
set_reg_jpeg(unsigned reg,unsigned cond,unsigned type,uint32_t val)325 static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type,
326 uint32_t val)
327 {
328 ib_cpu[len++] = RDECODE_PKTJ(reg, cond, type);
329 ib_cpu[len++] = val;
330 }
331
332 /* send a bitstream buffer command */
send_cmd_bitstream(uint64_t addr)333 static void send_cmd_bitstream(uint64_t addr)
334 {
335
336 /* jpeg soft reset */
337 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1);
338
339 /* ensuring the Reset is asserted in SCLK domain */
340 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2);
341 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200);
342 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
343 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9));
344 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
345
346 /* wait mem */
347 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0);
348
349 /* ensuring the Reset is de-asserted in SCLK domain */
350 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
351 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
352 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
353
354 /* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */
355 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH), COND0, TYPE0,
356 (addr >> 32));
357 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW), COND0, TYPE0,
358 (unsigned int)addr);
359
360 /* set jpeg_rb_base */
361 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_BASE), COND0, TYPE0, 0);
362
363 /* set jpeg_rb_base */
364 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_SIZE), COND0, TYPE0, 0xFFFFFFF0);
365
366 /* set jpeg_rb_wptr */
367 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_WPTR), COND0, TYPE0,
368 (JPEG_DEC_BSD_SIZE >> 2));
369 }
370
371 /* send a target buffer command */
send_cmd_target(uint64_t addr)372 static void send_cmd_target(uint64_t addr)
373 {
374
375 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_PITCH), COND0, TYPE0,
376 (JPEG_DEC_DT_PITCH >> 4));
377 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_UV_PITCH), COND0, TYPE0,
378 (JPEG_DEC_DT_PITCH >> 4));
379
380 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_TILING_CTRL), COND0, TYPE0, 0);
381 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_UV_TILING_CTRL), COND0, TYPE0, 0);
382
383 /* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */
384 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH), COND0,
385 TYPE0, (addr >> 32));
386 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW), COND0, TYPE0,
387 (unsigned int)addr);
388
389 /* set output buffer data address */
390 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 0);
391 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0,
392 JPEG_DEC_LUMA_OFFSET);
393 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 1);
394 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0,
395 JPEG_DEC_CHROMA_OFFSET);
396 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_TIER_CNTL2), COND0, TYPE3, 0);
397
398 /* set output buffer read pointer */
399 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_RPTR), COND0, TYPE0, 0);
400
401 /* enable error interrupts */
402 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INT_EN), COND0, TYPE0, 0xFFFFFFFE);
403
404 /* start engine command */
405 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x6);
406
407 /* wait for job completion, wait for job JBSI fetch done */
408 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
409 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0,
410 (JPEG_DEC_BSD_SIZE >> 2));
411 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2);
412 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200);
413 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_RPTR), COND0, TYPE3, 0xFFFFFFFF);
414
415 /* wait for job jpeg outbuf idle */
416 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
417 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0xFFFFFFFF);
418 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_WPTR), COND0, TYPE3,
419 0x00000001);
420
421 /* stop engine */
422 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x4);
423
424 /* asserting jpeg lmi drop */
425 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005);
426 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0,
427 (1 << 23 | 1 << 0));
428 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE1, 0);
429 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0);
430
431 /* asserting jpeg reset */
432 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1);
433
434 /* ensure reset is asserted in sclk domain */
435 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
436 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9));
437 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
438
439 /* de-assert jpeg reset */
440 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0);
441
442 /* ensure reset is de-asserted in sclk domain */
443 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3);
444 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9));
445 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9));
446
447 /* de-asserting jpeg lmi drop */
448 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005);
449 set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0);
450 }
451
452 /* send a bitstream buffer command */
send_cmd_bitstream_direct(uint64_t addr)453 static void send_cmd_bitstream_direct(uint64_t addr)
454 {
455
456 /* jpeg soft reset */
457 set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 1);
458
459 /* ensuring the Reset is asserted in SCLK domain */
460 set_reg_jpeg(vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200);
461 set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0x1 << 0x10));
462 set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10));
463
464 /* wait mem */
465 set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 0);
466
467 /* ensuring the Reset is de-asserted in SCLK domain */
468 set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10));
469 set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10));
470
471 /* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */
472 set_reg_jpeg(vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0,
473 (addr >> 32));
474 set_reg_jpeg(vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0, addr);
475
476 /* set jpeg_rb_base */
477 set_reg_jpeg(vcnipUVD_JPEG_RB_BASE, COND0, TYPE0, 0);
478
479 /* set jpeg_rb_base */
480 set_reg_jpeg(vcnipUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFFFFFF0);
481
482 /* set jpeg_rb_wptr */
483 set_reg_jpeg(vcnipUVD_JPEG_RB_WPTR, COND0, TYPE0, (JPEG_DEC_BSD_SIZE >> 2));
484 }
485
486 /* send a target buffer command */
send_cmd_target_direct(uint64_t addr)487 static void send_cmd_target_direct(uint64_t addr)
488 {
489
490 set_reg_jpeg(vcnipUVD_JPEG_PITCH, COND0, TYPE0, (JPEG_DEC_DT_PITCH >> 4));
491 set_reg_jpeg(vcnipUVD_JPEG_UV_PITCH, COND0, TYPE0, (JPEG_DEC_DT_PITCH >> 4));
492
493 set_reg_jpeg(vcnipJPEG_DEC_ADDR_MODE, COND0, TYPE0, 0);
494 set_reg_jpeg(vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0, 0);
495 set_reg_jpeg(vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0, 0);
496
497 /* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */
498 set_reg_jpeg(vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0,
499 (addr >> 32));
500 set_reg_jpeg(vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, addr);
501
502 /* set output buffer data address */
503 set_reg_jpeg(vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0);
504 set_reg_jpeg(vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_LUMA_OFFSET);
505 set_reg_jpeg(vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1);
506 set_reg_jpeg(vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_CHROMA_OFFSET);
507 set_reg_jpeg(vcnipUVD_JPEG_TIER_CNTL2, COND0, 0, 0);
508
509 /* set output buffer read pointer */
510 set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0);
511 set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0,
512 ((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)));
513
514 /* enable error interrupts */
515 set_reg_jpeg(vcnipUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFFFFFE);
516
517 /* start engine command */
518 set_reg_jpeg(vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0xE);
519
520 /* wait for job completion, wait for job JBSI fetch done */
521 set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0,
522 (JPEG_DEC_BSD_SIZE >> 2));
523 set_reg_jpeg(vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200);
524 set_reg_jpeg(vcnipUVD_JPEG_RB_RPTR, COND3, TYPE3, 0xFFFFFFFF);
525
526 /* wait for job jpeg outbuf idle */
527 set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, 0xFFFFFFFF);
528 set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_WPTR, COND3, TYPE3, 0x00000001);
529
530 /* stop engine */
531 set_reg_jpeg(vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0x4);
532 }
533
amdgpu_cs_jpeg_decode(void)534 static void amdgpu_cs_jpeg_decode(void)
535 {
536
537 struct amdgpu_jpeg_bo dec_buf;
538 int size, r;
539 uint8_t *dec;
540 int sum = 0, i, j;
541
542 size = 16 * 1024; /* 8K bitstream + 8K output */
543 num_resources = 0;
544 alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_VRAM);
545 resources[num_resources++] = dec_buf.handle;
546 resources[num_resources++] = ib_handle;
547 r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
548 CU_ASSERT_EQUAL(r, 0);
549 memcpy(dec_buf.ptr, jpeg_bitstream, sizeof(jpeg_bitstream));
550
551 len = 0;
552
553 if (jpeg_direct_reg == true) {
554 send_cmd_bitstream_direct(dec_buf.addr);
555 send_cmd_target_direct(dec_buf.addr + (size / 2));
556 } else {
557 send_cmd_bitstream(dec_buf.addr);
558 send_cmd_target(dec_buf.addr + (size / 2));
559 }
560
561 amdgpu_bo_cpu_unmap(dec_buf.handle);
562 r = submit(len, AMDGPU_HW_IP_VCN_JPEG);
563 CU_ASSERT_EQUAL(r, 0);
564
565 r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
566 CU_ASSERT_EQUAL(r, 0);
567
568 dec = dec_buf.ptr + (size / 2);
569
570 /* calculate result checksum */
571 for (i = 0; i < 8; i++)
572 for (j = 0; j < 8; j++)
573 sum += *((dec + JPEG_DEC_LUMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j);
574 for (i = 0; i < 4; i++)
575 for (j = 0; j < 8; j++)
576 sum += *((dec + JPEG_DEC_CHROMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j);
577
578 amdgpu_bo_cpu_unmap(dec_buf.handle);
579 CU_ASSERT_EQUAL(sum, JPEG_DEC_SUM);
580
581 free_resource(&dec_buf);
582 }
583