1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <stdio.h>
25 #include <inttypes.h>
26
27 #include "CUnit/Basic.h"
28
29 #include "util_math.h"
30
31 #include "amdgpu_test.h"
32 #include "amdgpu_drm.h"
33 #include "amdgpu_internal.h"
34 #include "decode_messages.h"
35
36 #define IB_SIZE 4096
37 #define MAX_RESOURCES 16
38
39 struct amdgpu_vcn_bo {
40 amdgpu_bo_handle handle;
41 amdgpu_va_handle va_handle;
42 uint64_t addr;
43 uint64_t size;
44 uint8_t *ptr;
45 };
46
47 struct amdgpu_vcn_reg {
48 uint32_t data0;
49 uint32_t data1;
50 uint32_t cmd;
51 uint32_t nop;
52 uint32_t cntl;
53 };
54
55 static amdgpu_device_handle device_handle;
56 static uint32_t major_version;
57 static uint32_t minor_version;
58 static uint32_t family_id;
59 static uint32_t chip_rev;
60 static uint32_t chip_id;
61 static uint32_t asic_id;
62 static uint32_t chip_rev;
63 static uint32_t chip_id;
64
65 static amdgpu_context_handle context_handle;
66 static amdgpu_bo_handle ib_handle;
67 static amdgpu_va_handle ib_va_handle;
68 static uint64_t ib_mc_address;
69 static uint32_t *ib_cpu;
70
71 static amdgpu_bo_handle resources[MAX_RESOURCES];
72 static unsigned num_resources;
73 static struct amdgpu_vcn_reg reg;
74
75 static void amdgpu_cs_vcn_dec_create(void);
76 static void amdgpu_cs_vcn_dec_decode(void);
77 static void amdgpu_cs_vcn_dec_destroy(void);
78
79 static void amdgpu_cs_vcn_enc_create(void);
80 static void amdgpu_cs_vcn_enc_encode(void);
81 static void amdgpu_cs_vcn_enc_destroy(void);
82
83 CU_TestInfo vcn_tests[] = {
84
85 { "VCN DEC create", amdgpu_cs_vcn_dec_create },
86 { "VCN DEC decode", amdgpu_cs_vcn_dec_decode },
87 { "VCN DEC destroy", amdgpu_cs_vcn_dec_destroy },
88
89 { "VCN ENC create", amdgpu_cs_vcn_enc_create },
90 { "VCN ENC decode", amdgpu_cs_vcn_enc_encode },
91 { "VCN ENC destroy", amdgpu_cs_vcn_enc_destroy },
92 CU_TEST_INFO_NULL,
93 };
94
suite_vcn_tests_enable(void)95 CU_BOOL suite_vcn_tests_enable(void)
96 {
97 struct drm_amdgpu_info_hw_ip info;
98 int r;
99
100 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
101 &minor_version, &device_handle))
102 return CU_FALSE;
103
104 family_id = device_handle->info.family_id;
105 asic_id = device_handle->info.asic_id;
106 chip_rev = device_handle->info.chip_rev;
107 chip_id = device_handle->info.chip_external_rev;
108
109 r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_DEC, 0, &info);
110
111 if (amdgpu_device_deinitialize(device_handle))
112 return CU_FALSE;
113
114 if (r != 0 || !info.available_rings ||
115 (family_id < AMDGPU_FAMILY_RV &&
116 (family_id == AMDGPU_FAMILY_AI &&
117 (chip_id - chip_rev) < 0x32))) { /* Arcturus */
118 printf("\n\nThe ASIC NOT support VCN, suite disabled\n");
119 return CU_FALSE;
120 }
121
122 if (family_id == AMDGPU_FAMILY_AI) {
123 amdgpu_set_test_active("VCN Tests", "VCN ENC create", CU_FALSE);
124 amdgpu_set_test_active("VCN Tests", "VCN ENC decode", CU_FALSE);
125 amdgpu_set_test_active("VCN Tests", "VCN ENC destroy", CU_FALSE);
126 }
127
128 if (family_id == AMDGPU_FAMILY_RV) {
129 if (chip_id >= (chip_rev + 0x91)) {
130 reg.data0 = 0x504;
131 reg.data1 = 0x505;
132 reg.cmd = 0x503;
133 reg.nop = 0x53f;
134 reg.cntl = 0x506;
135 } else {
136 reg.data0 = 0x81c4;
137 reg.data1 = 0x81c5;
138 reg.cmd = 0x81c3;
139 reg.nop = 0x81ff;
140 reg.cntl = 0x81c6;
141 }
142 } else if (family_id == AMDGPU_FAMILY_NV) {
143 if (chip_id == (chip_rev + 0x28) ||
144 chip_id == (chip_rev + 0x32) ||
145 chip_id == (chip_rev + 0x3c) ||
146 chip_id == (chip_rev + 0x46)) {
147 reg.data0 = 0x10;
148 reg.data1 = 0x11;
149 reg.cmd = 0xf;
150 reg.nop = 0x29;
151 reg.cntl = 0x26d;
152 }
153 else {
154 reg.data0 = 0x504;
155 reg.data1 = 0x505;
156 reg.cmd = 0x503;
157 reg.nop = 0x53f;
158 reg.cntl = 0x506;
159 }
160 } else if (family_id == AMDGPU_FAMILY_AI) {
161 reg.data0 = 0x10;
162 reg.data1 = 0x11;
163 reg.cmd = 0xf;
164 reg.nop = 0x29;
165 reg.cntl = 0x26d;
166 } else
167 return CU_FALSE;
168
169 return CU_TRUE;
170 }
171
suite_vcn_tests_init(void)172 int suite_vcn_tests_init(void)
173 {
174 int r;
175
176 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
177 &minor_version, &device_handle);
178 if (r)
179 return CUE_SINIT_FAILED;
180
181 family_id = device_handle->info.family_id;
182
183 r = amdgpu_cs_ctx_create(device_handle, &context_handle);
184 if (r)
185 return CUE_SINIT_FAILED;
186
187 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
188 AMDGPU_GEM_DOMAIN_GTT, 0,
189 &ib_handle, (void**)&ib_cpu,
190 &ib_mc_address, &ib_va_handle);
191 if (r)
192 return CUE_SINIT_FAILED;
193
194 return CUE_SUCCESS;
195 }
196
suite_vcn_tests_clean(void)197 int suite_vcn_tests_clean(void)
198 {
199 int r;
200
201 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
202 ib_mc_address, IB_SIZE);
203 if (r)
204 return CUE_SCLEAN_FAILED;
205
206 r = amdgpu_cs_ctx_free(context_handle);
207 if (r)
208 return CUE_SCLEAN_FAILED;
209
210 r = amdgpu_device_deinitialize(device_handle);
211 if (r)
212 return CUE_SCLEAN_FAILED;
213
214 return CUE_SUCCESS;
215 }
216
submit(unsigned ndw,unsigned ip)217 static int submit(unsigned ndw, unsigned ip)
218 {
219 struct amdgpu_cs_request ibs_request = {0};
220 struct amdgpu_cs_ib_info ib_info = {0};
221 struct amdgpu_cs_fence fence_status = {0};
222 uint32_t expired;
223 int r;
224
225 ib_info.ib_mc_address = ib_mc_address;
226 ib_info.size = ndw;
227
228 ibs_request.ip_type = ip;
229
230 r = amdgpu_bo_list_create(device_handle, num_resources, resources,
231 NULL, &ibs_request.resources);
232 if (r)
233 return r;
234
235 ibs_request.number_of_ibs = 1;
236 ibs_request.ibs = &ib_info;
237 ibs_request.fence_info.handle = NULL;
238
239 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
240 if (r)
241 return r;
242
243 r = amdgpu_bo_list_destroy(ibs_request.resources);
244 if (r)
245 return r;
246
247 fence_status.context = context_handle;
248 fence_status.ip_type = ip;
249 fence_status.fence = ibs_request.seq_no;
250
251 r = amdgpu_cs_query_fence_status(&fence_status,
252 AMDGPU_TIMEOUT_INFINITE,
253 0, &expired);
254 if (r)
255 return r;
256
257 return 0;
258 }
259
alloc_resource(struct amdgpu_vcn_bo * vcn_bo,unsigned size,unsigned domain)260 static void alloc_resource(struct amdgpu_vcn_bo *vcn_bo,
261 unsigned size, unsigned domain)
262 {
263 struct amdgpu_bo_alloc_request req = {0};
264 amdgpu_bo_handle buf_handle;
265 amdgpu_va_handle va_handle;
266 uint64_t va = 0;
267 int r;
268
269 req.alloc_size = ALIGN(size, 4096);
270 req.preferred_heap = domain;
271 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
272 CU_ASSERT_EQUAL(r, 0);
273 r = amdgpu_va_range_alloc(device_handle,
274 amdgpu_gpu_va_range_general,
275 req.alloc_size, 1, 0, &va,
276 &va_handle, 0);
277 CU_ASSERT_EQUAL(r, 0);
278 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
279 AMDGPU_VA_OP_MAP);
280 CU_ASSERT_EQUAL(r, 0);
281 vcn_bo->addr = va;
282 vcn_bo->handle = buf_handle;
283 vcn_bo->size = req.alloc_size;
284 vcn_bo->va_handle = va_handle;
285 r = amdgpu_bo_cpu_map(vcn_bo->handle, (void **)&vcn_bo->ptr);
286 CU_ASSERT_EQUAL(r, 0);
287 memset(vcn_bo->ptr, 0, size);
288 r = amdgpu_bo_cpu_unmap(vcn_bo->handle);
289 CU_ASSERT_EQUAL(r, 0);
290 }
291
free_resource(struct amdgpu_vcn_bo * vcn_bo)292 static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
293 {
294 int r;
295
296 r = amdgpu_bo_va_op(vcn_bo->handle, 0, vcn_bo->size,
297 vcn_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
298 CU_ASSERT_EQUAL(r, 0);
299
300 r = amdgpu_va_range_free(vcn_bo->va_handle);
301 CU_ASSERT_EQUAL(r, 0);
302
303 r = amdgpu_bo_free(vcn_bo->handle);
304 CU_ASSERT_EQUAL(r, 0);
305 memset(vcn_bo, 0, sizeof(*vcn_bo));
306 }
307
vcn_dec_cmd(uint64_t addr,unsigned cmd,int * idx)308 static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
309 {
310 ib_cpu[(*idx)++] = reg.data0;
311 ib_cpu[(*idx)++] = addr;
312 ib_cpu[(*idx)++] = reg.data1;
313 ib_cpu[(*idx)++] = addr >> 32;
314 ib_cpu[(*idx)++] = reg.cmd;
315 ib_cpu[(*idx)++] = cmd << 1;
316 }
317
amdgpu_cs_vcn_dec_create(void)318 static void amdgpu_cs_vcn_dec_create(void)
319 {
320 struct amdgpu_vcn_bo msg_buf;
321 int len, r;
322
323 num_resources = 0;
324 alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
325 resources[num_resources++] = msg_buf.handle;
326 resources[num_resources++] = ib_handle;
327
328 r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
329 CU_ASSERT_EQUAL(r, 0);
330
331 memset(msg_buf.ptr, 0, 4096);
332 memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
333
334 len = 0;
335 ib_cpu[len++] = reg.data0;
336 ib_cpu[len++] = msg_buf.addr;
337 ib_cpu[len++] = reg.data1;
338 ib_cpu[len++] = msg_buf.addr >> 32;
339 ib_cpu[len++] = reg.cmd;
340 ib_cpu[len++] = 0;
341 for (; len % 16; ) {
342 ib_cpu[len++] = reg.nop;
343 ib_cpu[len++] = 0;
344 }
345
346 r = submit(len, AMDGPU_HW_IP_VCN_DEC);
347 CU_ASSERT_EQUAL(r, 0);
348
349 free_resource(&msg_buf);
350 }
351
amdgpu_cs_vcn_dec_decode(void)352 static void amdgpu_cs_vcn_dec_decode(void)
353 {
354 const unsigned dpb_size = 15923584, dt_size = 737280;
355 uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum;
356 struct amdgpu_vcn_bo dec_buf;
357 int size, len, i, r;
358 uint8_t *dec;
359
360 size = 4*1024; /* msg */
361 size += 4*1024; /* fb */
362 size += 4096; /*it_scaling_table*/
363 size += ALIGN(sizeof(uvd_bitstream), 4*1024);
364 size += ALIGN(dpb_size, 4*1024);
365 size += ALIGN(dt_size, 4*1024);
366
367 num_resources = 0;
368 alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_GTT);
369 resources[num_resources++] = dec_buf.handle;
370 resources[num_resources++] = ib_handle;
371
372 r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
373 dec = dec_buf.ptr;
374
375 CU_ASSERT_EQUAL(r, 0);
376 memset(dec_buf.ptr, 0, size);
377 memcpy(dec_buf.ptr, vcn_dec_decode_msg, sizeof(vcn_dec_decode_msg));
378 memcpy(dec_buf.ptr + sizeof(vcn_dec_decode_msg),
379 avc_decode_msg, sizeof(avc_decode_msg));
380
381 dec += 4*1024;
382 memcpy(dec, feedback_msg, sizeof(feedback_msg));
383 dec += 4*1024;
384 memcpy(dec, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
385
386 dec += 4*1024;
387 memcpy(dec, uvd_bitstream, sizeof(uvd_bitstream));
388
389 dec += ALIGN(sizeof(uvd_bitstream), 4*1024);
390
391 dec += ALIGN(dpb_size, 4*1024);
392
393 msg_addr = dec_buf.addr;
394 fb_addr = msg_addr + 4*1024;
395 it_addr = fb_addr + 4*1024;
396 bs_addr = it_addr + 4*1024;
397 dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
398 ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
399 dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
400
401 len = 0;
402 vcn_dec_cmd(msg_addr, 0x0, &len);
403 vcn_dec_cmd(dpb_addr, 0x1, &len);
404 vcn_dec_cmd(dt_addr, 0x2, &len);
405 vcn_dec_cmd(fb_addr, 0x3, &len);
406 vcn_dec_cmd(bs_addr, 0x100, &len);
407 vcn_dec_cmd(it_addr, 0x204, &len);
408 vcn_dec_cmd(ctx_addr, 0x206, &len);
409
410 ib_cpu[len++] = reg.cntl;
411 ib_cpu[len++] = 0x1;
412 for (; len % 16; ) {
413 ib_cpu[len++] = reg.nop;
414 ib_cpu[len++] = 0;
415 }
416
417 r = submit(len, AMDGPU_HW_IP_VCN_DEC);
418 CU_ASSERT_EQUAL(r, 0);
419
420 for (i = 0, sum = 0; i < dt_size; ++i)
421 sum += dec[i];
422
423 CU_ASSERT_EQUAL(sum, SUM_DECODE);
424
425 free_resource(&dec_buf);
426 }
427
amdgpu_cs_vcn_dec_destroy(void)428 static void amdgpu_cs_vcn_dec_destroy(void)
429 {
430 struct amdgpu_vcn_bo msg_buf;
431 int len, r;
432
433 num_resources = 0;
434 alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
435 resources[num_resources++] = msg_buf.handle;
436 resources[num_resources++] = ib_handle;
437
438 r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
439 CU_ASSERT_EQUAL(r, 0);
440
441 memset(msg_buf.ptr, 0, 1024);
442 memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
443
444 len = 0;
445 ib_cpu[len++] = reg.data0;
446 ib_cpu[len++] = msg_buf.addr;
447 ib_cpu[len++] = reg.data1;
448 ib_cpu[len++] = msg_buf.addr >> 32;
449 ib_cpu[len++] = reg.cmd;
450 ib_cpu[len++] = 0;
451 for (; len % 16; ) {
452 ib_cpu[len++] = reg.nop;
453 ib_cpu[len++] = 0;
454 }
455
456 r = submit(len, AMDGPU_HW_IP_VCN_DEC);
457 CU_ASSERT_EQUAL(r, 0);
458
459 free_resource(&msg_buf);
460 }
461
amdgpu_cs_vcn_enc_create(void)462 static void amdgpu_cs_vcn_enc_create(void)
463 {
464 /* TODO */
465 }
466
amdgpu_cs_vcn_enc_encode(void)467 static void amdgpu_cs_vcn_enc_encode(void)
468 {
469 /* TODO */
470 }
471
amdgpu_cs_vcn_enc_destroy(void)472 static void amdgpu_cs_vcn_enc_destroy(void)
473 {
474 /* TODO */
475 }
476