1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_DRM_H_ 7 #define _XE_DRM_H_ 8 9 #include "drm.h" 10 11 #if defined(__cplusplus) 12 extern "C" { 13 #endif 14 15 /* 16 * Please note that modifications to all structs defined here are 17 * subject to backwards-compatibility constraints. 18 * Sections in this file are organized as follows: 19 * 1. IOCTL definition 20 * 2. Extension definition and helper structs 21 * 3. IOCTL's Query structs in the order of the Query's entries. 22 * 4. The rest of IOCTL structs in the order of IOCTL declaration. 23 */ 24 25 /** 26 * DOC: Xe Device Block Diagram 27 * 28 * The diagram below represents a high-level simplification of a discrete 29 * GPU supported by the Xe driver. It shows some device components which 30 * are necessary to understand this API, as well as how their relations 31 * to each other. This diagram does not represent real hardware:: 32 * 33 * ┌──────────────────────────────────────────────────────────────────┐ 34 * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │ 35 * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │ 36 * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │ 37 * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │ 38 * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │ 39 * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │ 40 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 41 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │ 42 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 43 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 44 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │ 45 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 46 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 47 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │ 48 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 49 * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 50 * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │ 51 * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 52 * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │ 53 * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │ 54 * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │ 55 * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │ 56 * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │ 57 * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │ 58 * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │ 59 * └─────────────────────────────Device0───────┬──────────────────────┘ 60 * │ 61 * ───────────────────────┴────────── PCI bus 62 */ 63 64 /** 65 * DOC: Xe uAPI Overview 66 * 67 * This section aims to describe the Xe's IOCTL entries, its structs, and other 68 * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related 69 * entries and usage. 70 * 71 * List of supported IOCTLs: 72 * - &DRM_IOCTL_XE_DEVICE_QUERY 73 * - &DRM_IOCTL_XE_GEM_CREATE 74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET 75 * - &DRM_IOCTL_XE_VM_CREATE 76 * - &DRM_IOCTL_XE_VM_DESTROY 77 * - &DRM_IOCTL_XE_VM_BIND 78 * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE 79 * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY 80 * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY 81 * - &DRM_IOCTL_XE_EXEC 82 * - &DRM_IOCTL_XE_WAIT_USER_FENCE 83 */ 84 85 /* 86 * xe specific ioctls. 87 * 88 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie 89 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset 90 * against DRM_COMMAND_BASE and should be between [0x0, 0x60). 91 */ 92 #define DRM_XE_DEVICE_QUERY 0x00 93 #define DRM_XE_GEM_CREATE 0x01 94 #define DRM_XE_GEM_MMAP_OFFSET 0x02 95 #define DRM_XE_VM_CREATE 0x03 96 #define DRM_XE_VM_DESTROY 0x04 97 #define DRM_XE_VM_BIND 0x05 98 #define DRM_XE_EXEC_QUEUE_CREATE 0x06 99 #define DRM_XE_EXEC_QUEUE_DESTROY 0x07 100 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08 101 #define DRM_XE_EXEC 0x09 102 #define DRM_XE_WAIT_USER_FENCE 0x0a 103 /* Must be kept compact -- no holes */ 104 105 #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) 106 #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create) 107 #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset) 108 #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) 109 #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) 110 #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) 111 #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) 112 #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) 113 #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) 114 #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) 115 #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) 116 117 /** 118 * DOC: Xe IOCTL Extensions 119 * 120 * Before detailing the IOCTLs and its structs, it is important to highlight 121 * that every IOCTL in Xe is extensible. 122 * 123 * Many interfaces need to grow over time. In most cases we can simply 124 * extend the struct and have userspace pass in more data. Another option, 125 * as demonstrated by Vulkan's approach to providing extensions for forward 126 * and backward compatibility, is to use a list of optional structs to 127 * provide those extra details. 128 * 129 * The key advantage to using an extension chain is that it allows us to 130 * redefine the interface more easily than an ever growing struct of 131 * increasing complexity, and for large parts of that interface to be 132 * entirely optional. The downside is more pointer chasing; chasing across 133 * the boundary with pointers encapsulated inside u64. 134 * 135 * Example chaining: 136 * 137 * .. code-block:: C 138 * 139 * struct drm_xe_user_extension ext3 { 140 * .next_extension = 0, // end 141 * .name = ..., 142 * }; 143 * struct drm_xe_user_extension ext2 { 144 * .next_extension = (uintptr_t)&ext3, 145 * .name = ..., 146 * }; 147 * struct drm_xe_user_extension ext1 { 148 * .next_extension = (uintptr_t)&ext2, 149 * .name = ..., 150 * }; 151 * 152 * Typically the struct drm_xe_user_extension would be embedded in some uAPI 153 * struct, and in this case we would feed it the head of the chain(i.e ext1), 154 * which would then apply all of the above extensions. 155 */ 156 157 /** 158 * struct drm_xe_user_extension - Base class for defining a chain of extensions 159 */ 160 struct drm_xe_user_extension { 161 /** 162 * @next_extension: 163 * 164 * Pointer to the next struct drm_xe_user_extension, or zero if the end. 165 */ 166 __u64 next_extension; 167 168 /** 169 * @name: Name of the extension. 170 * 171 * Note that the name here is just some integer. 172 * 173 * Also note that the name space for this is not global for the whole 174 * driver, but rather its scope/meaning is limited to the specific piece 175 * of uAPI which has embedded the struct drm_xe_user_extension. 176 */ 177 __u32 name; 178 179 /** 180 * @pad: MBZ 181 * 182 * All undefined bits must be zero. 183 */ 184 __u32 pad; 185 }; 186 187 /** 188 * struct drm_xe_ext_set_property - Generic set property extension 189 * 190 * A generic struct that allows any of the Xe's IOCTL to be extended 191 * with a set_property operation. 192 */ 193 struct drm_xe_ext_set_property { 194 /** @base: base user extension */ 195 struct drm_xe_user_extension base; 196 197 /** @property: property to set */ 198 __u32 property; 199 200 /** @pad: MBZ */ 201 __u32 pad; 202 203 /** @value: property value */ 204 __u64 value; 205 206 /** @reserved: Reserved */ 207 __u64 reserved[2]; 208 }; 209 210 /** 211 * struct drm_xe_engine_class_instance - instance of an engine class 212 * 213 * It is returned as part of the @drm_xe_engine, but it also is used as 214 * the input of engine selection for both @drm_xe_exec_queue_create and 215 * @drm_xe_query_engine_cycles 216 * 217 * The @engine_class can be: 218 * - %DRM_XE_ENGINE_CLASS_RENDER 219 * - %DRM_XE_ENGINE_CLASS_COPY 220 * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE 221 * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 222 * - %DRM_XE_ENGINE_CLASS_COMPUTE 223 * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual 224 * hardware engine class). Used for creating ordered queues of VM 225 * bind operations. 226 */ 227 struct drm_xe_engine_class_instance { 228 #define DRM_XE_ENGINE_CLASS_RENDER 0 229 #define DRM_XE_ENGINE_CLASS_COPY 1 230 #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2 231 #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3 232 #define DRM_XE_ENGINE_CLASS_COMPUTE 4 233 #define DRM_XE_ENGINE_CLASS_VM_BIND 5 234 /** @engine_class: engine class id */ 235 __u16 engine_class; 236 /** @engine_instance: engine instance id */ 237 __u16 engine_instance; 238 /** @gt_id: Unique ID of this GT within the PCI Device */ 239 __u16 gt_id; 240 /** @pad: MBZ */ 241 __u16 pad; 242 }; 243 244 /** 245 * struct drm_xe_engine - describe hardware engine 246 */ 247 struct drm_xe_engine { 248 /** @instance: The @drm_xe_engine_class_instance */ 249 struct drm_xe_engine_class_instance instance; 250 251 /** @reserved: Reserved */ 252 __u64 reserved[3]; 253 }; 254 255 /** 256 * struct drm_xe_query_engines - describe engines 257 * 258 * If a query is made with a struct @drm_xe_device_query where .query 259 * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of 260 * struct @drm_xe_query_engines in .data. 261 */ 262 struct drm_xe_query_engines { 263 /** @num_engines: number of engines returned in @engines */ 264 __u32 num_engines; 265 /** @pad: MBZ */ 266 __u32 pad; 267 /** @engines: The returned engines for this device */ 268 struct drm_xe_engine engines[]; 269 }; 270 271 /** 272 * enum drm_xe_memory_class - Supported memory classes. 273 */ 274 enum drm_xe_memory_class { 275 /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */ 276 DRM_XE_MEM_REGION_CLASS_SYSMEM = 0, 277 /** 278 * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this 279 * represents the memory that is local to the device, which we 280 * call VRAM. Not valid on integrated platforms. 281 */ 282 DRM_XE_MEM_REGION_CLASS_VRAM 283 }; 284 285 /** 286 * struct drm_xe_mem_region - Describes some region as known to 287 * the driver. 288 */ 289 struct drm_xe_mem_region { 290 /** 291 * @mem_class: The memory class describing this region. 292 * 293 * See enum drm_xe_memory_class for supported values. 294 */ 295 __u16 mem_class; 296 /** 297 * @instance: The unique ID for this region, which serves as the 298 * index in the placement bitmask used as argument for 299 * &DRM_IOCTL_XE_GEM_CREATE 300 */ 301 __u16 instance; 302 /** 303 * @min_page_size: Min page-size in bytes for this region. 304 * 305 * When the kernel allocates memory for this region, the 306 * underlying pages will be at least @min_page_size in size. 307 * Buffer objects with an allowable placement in this region must be 308 * created with a size aligned to this value. 309 * GPU virtual address mappings of (parts of) buffer objects that 310 * may be placed in this region must also have their GPU virtual 311 * address and range aligned to this value. 312 * Affected IOCTLS will return %-EINVAL if alignment restrictions are 313 * not met. 314 */ 315 __u32 min_page_size; 316 /** 317 * @total_size: The usable size in bytes for this region. 318 */ 319 __u64 total_size; 320 /** 321 * @used: Estimate of the memory used in bytes for this region. 322 * 323 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable 324 * accounting. Without this the value here will always equal 325 * zero. 326 */ 327 __u64 used; 328 /** 329 * @cpu_visible_size: How much of this region can be CPU 330 * accessed, in bytes. 331 * 332 * This will always be <= @total_size, and the remainder (if 333 * any) will not be CPU accessible. If the CPU accessible part 334 * is smaller than @total_size then this is referred to as a 335 * small BAR system. 336 * 337 * On systems without small BAR (full BAR), the probed_size will 338 * always equal the @total_size, since all of it will be CPU 339 * accessible. 340 * 341 * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM 342 * regions (for other types the value here will always equal 343 * zero). 344 */ 345 __u64 cpu_visible_size; 346 /** 347 * @cpu_visible_used: Estimate of CPU visible memory used, in 348 * bytes. 349 * 350 * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable 351 * accounting. Without this the value here will always equal 352 * zero. Note this is only currently tracked for 353 * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value 354 * here will always be zero). 355 */ 356 __u64 cpu_visible_used; 357 /** @reserved: Reserved */ 358 __u64 reserved[6]; 359 }; 360 361 /** 362 * struct drm_xe_query_mem_regions - describe memory regions 363 * 364 * If a query is made with a struct drm_xe_device_query where .query 365 * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses 366 * struct drm_xe_query_mem_regions in .data. 367 */ 368 struct drm_xe_query_mem_regions { 369 /** @num_mem_regions: number of memory regions returned in @mem_regions */ 370 __u32 num_mem_regions; 371 /** @pad: MBZ */ 372 __u32 pad; 373 /** @mem_regions: The returned memory regions for this device */ 374 struct drm_xe_mem_region mem_regions[]; 375 }; 376 377 /** 378 * struct drm_xe_query_config - describe the device configuration 379 * 380 * If a query is made with a struct drm_xe_device_query where .query 381 * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses 382 * struct drm_xe_query_config in .data. 383 * 384 * The index in @info can be: 385 * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits) 386 * and the device revision (next 8 bits) 387 * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device 388 * configuration, see list below 389 * 390 * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device 391 * has usable VRAM 392 * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment 393 * required by this device, typically SZ_4K or SZ_64K 394 * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address 395 * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest 396 * available exec queue priority 397 */ 398 struct drm_xe_query_config { 399 /** @num_params: number of parameters returned in info */ 400 __u32 num_params; 401 402 /** @pad: MBZ */ 403 __u32 pad; 404 405 #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 406 #define DRM_XE_QUERY_CONFIG_FLAGS 1 407 #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0) 408 #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2 409 #define DRM_XE_QUERY_CONFIG_VA_BITS 3 410 #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 411 /** @info: array of elements containing the config info */ 412 __u64 info[]; 413 }; 414 415 /** 416 * struct drm_xe_gt - describe an individual GT. 417 * 418 * To be used with drm_xe_query_gt_list, which will return a list with all the 419 * existing GT individual descriptions. 420 * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for 421 * implementing graphics and/or media operations. 422 * 423 * The index in @type can be: 424 * - %DRM_XE_QUERY_GT_TYPE_MAIN 425 * - %DRM_XE_QUERY_GT_TYPE_MEDIA 426 */ 427 struct drm_xe_gt { 428 #define DRM_XE_QUERY_GT_TYPE_MAIN 0 429 #define DRM_XE_QUERY_GT_TYPE_MEDIA 1 430 /** @type: GT type: Main or Media */ 431 __u16 type; 432 /** @tile_id: Tile ID where this GT lives (Information only) */ 433 __u16 tile_id; 434 /** @gt_id: Unique ID of this GT within the PCI Device */ 435 __u16 gt_id; 436 /** @pad: MBZ */ 437 __u16 pad[3]; 438 /** @reference_clock: A clock frequency for timestamp */ 439 __u32 reference_clock; 440 /** 441 * @near_mem_regions: Bit mask of instances from 442 * drm_xe_query_mem_regions that are nearest to the current engines 443 * of this GT. 444 * Each index in this mask refers directly to the struct 445 * drm_xe_query_mem_regions' instance, no assumptions should 446 * be made about order. The type of each region is described 447 * by struct drm_xe_query_mem_regions' mem_class. 448 */ 449 __u64 near_mem_regions; 450 /** 451 * @far_mem_regions: Bit mask of instances from 452 * drm_xe_query_mem_regions that are far from the engines of this GT. 453 * In general, they have extra indirections when compared to the 454 * @near_mem_regions. For a discrete device this could mean system 455 * memory and memory living in a different tile. 456 * Each index in this mask refers directly to the struct 457 * drm_xe_query_mem_regions' instance, no assumptions should 458 * be made about order. The type of each region is described 459 * by struct drm_xe_query_mem_regions' mem_class. 460 */ 461 __u64 far_mem_regions; 462 /** @reserved: Reserved */ 463 __u64 reserved[8]; 464 }; 465 466 /** 467 * struct drm_xe_query_gt_list - A list with GT description items. 468 * 469 * If a query is made with a struct drm_xe_device_query where .query 470 * is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct 471 * drm_xe_query_gt_list in .data. 472 */ 473 struct drm_xe_query_gt_list { 474 /** @num_gt: number of GT items returned in gt_list */ 475 __u32 num_gt; 476 /** @pad: MBZ */ 477 __u32 pad; 478 /** @gt_list: The GT list returned for this device */ 479 struct drm_xe_gt gt_list[]; 480 }; 481 482 /** 483 * struct drm_xe_query_topology_mask - describe the topology mask of a GT 484 * 485 * This is the hardware topology which reflects the internal physical 486 * structure of the GPU. 487 * 488 * If a query is made with a struct drm_xe_device_query where .query 489 * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses 490 * struct drm_xe_query_topology_mask in .data. 491 * 492 * The @type can be: 493 * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices 494 * (DSS) available for geometry operations. For example a query response 495 * containing the following in mask: 496 * ``DSS_GEOMETRY ff ff ff ff 00 00 00 00`` 497 * means 32 DSS are available for geometry. 498 * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices 499 * (DSS) available for compute operations. For example a query response 500 * containing the following in mask: 501 * ``DSS_COMPUTE ff ff ff ff 00 00 00 00`` 502 * means 32 DSS are available for compute. 503 * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU) 504 * available per Dual Sub Slices (DSS). For example a query response 505 * containing the following in mask: 506 * ``EU_PER_DSS ff ff 00 00 00 00 00 00`` 507 * means each DSS has 16 EU. 508 */ 509 struct drm_xe_query_topology_mask { 510 /** @gt_id: GT ID the mask is associated with */ 511 __u16 gt_id; 512 513 #define DRM_XE_TOPO_DSS_GEOMETRY (1 << 0) 514 #define DRM_XE_TOPO_DSS_COMPUTE (1 << 1) 515 #define DRM_XE_TOPO_EU_PER_DSS (1 << 2) 516 /** @type: type of mask */ 517 __u16 type; 518 519 /** @num_bytes: number of bytes in requested mask */ 520 __u32 num_bytes; 521 522 /** @mask: little-endian mask of @num_bytes */ 523 __u8 mask[]; 524 }; 525 526 /** 527 * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps 528 * 529 * If a query is made with a struct drm_xe_device_query where .query is equal to 530 * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles 531 * in .data. struct drm_xe_query_engine_cycles is allocated by the user and 532 * .data points to this allocated structure. 533 * 534 * The query returns the engine cycles, which along with GT's @reference_clock, 535 * can be used to calculate the engine timestamp. In addition the 536 * query returns a set of cpu timestamps that indicate when the command 537 * streamer cycle count was captured. 538 */ 539 struct drm_xe_query_engine_cycles { 540 /** 541 * @eci: This is input by the user and is the engine for which command 542 * streamer cycles is queried. 543 */ 544 struct drm_xe_engine_class_instance eci; 545 546 /** 547 * @clockid: This is input by the user and is the reference clock id for 548 * CPU timestamp. For definition, see clock_gettime(2) and 549 * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC, 550 * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI. 551 */ 552 __s32 clockid; 553 554 /** @width: Width of the engine cycle counter in bits. */ 555 __u32 width; 556 557 /** 558 * @engine_cycles: Engine cycles as read from its register 559 * at 0x358 offset. 560 */ 561 __u64 engine_cycles; 562 563 /** 564 * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before 565 * reading the engine_cycles register using the reference clockid set by the 566 * user. 567 */ 568 __u64 cpu_timestamp; 569 570 /** 571 * @cpu_delta: Time delta in ns captured around reading the lower dword 572 * of the engine_cycles register. 573 */ 574 __u64 cpu_delta; 575 }; 576 577 /** 578 * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version 579 * 580 * Given a uc_type this will return the branch, major, minor and patch version 581 * of the micro-controller firmware. 582 */ 583 struct drm_xe_query_uc_fw_version { 584 /** @uc_type: The micro-controller type to query firmware version */ 585 #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0 586 #define XE_QUERY_UC_TYPE_HUC 1 587 __u16 uc_type; 588 589 /** @pad: MBZ */ 590 __u16 pad; 591 592 /** @branch_ver: branch uc fw version */ 593 __u32 branch_ver; 594 /** @major_ver: major uc fw version */ 595 __u32 major_ver; 596 /** @minor_ver: minor uc fw version */ 597 __u32 minor_ver; 598 /** @patch_ver: patch uc fw version */ 599 __u32 patch_ver; 600 601 /** @pad2: MBZ */ 602 __u32 pad2; 603 604 /** @reserved: Reserved */ 605 __u64 reserved; 606 }; 607 608 /** 609 * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main 610 * structure to query device information 611 * 612 * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_* 613 * and sets the value in the query member. This determines the type of 614 * the structure provided by the driver in data, among struct drm_xe_query_*. 615 * 616 * The @query can be: 617 * - %DRM_XE_DEVICE_QUERY_ENGINES 618 * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS 619 * - %DRM_XE_DEVICE_QUERY_CONFIG 620 * - %DRM_XE_DEVICE_QUERY_GT_LIST 621 * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware 622 * configuration of the device such as information on slices, memory, 623 * caches, and so on. It is provided as a table of key / value 624 * attributes. 625 * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 626 * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 627 * 628 * If size is set to 0, the driver fills it with the required size for 629 * the requested type of data to query. If size is equal to the required 630 * size, the queried information is copied into data. If size is set to 631 * a value different from 0 and different from the required size, the 632 * IOCTL call returns -EINVAL. 633 * 634 * For example the following code snippet allows retrieving and printing 635 * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES: 636 * 637 * .. code-block:: C 638 * 639 * struct drm_xe_query_engines *engines; 640 * struct drm_xe_device_query query = { 641 * .extensions = 0, 642 * .query = DRM_XE_DEVICE_QUERY_ENGINES, 643 * .size = 0, 644 * .data = 0, 645 * }; 646 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 647 * engines = malloc(query.size); 648 * query.data = (uintptr_t)engines; 649 * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query); 650 * for (int i = 0; i < engines->num_engines; i++) { 651 * printf("Engine %d: %s\n", i, 652 * engines->engines[i].instance.engine_class == 653 * DRM_XE_ENGINE_CLASS_RENDER ? "RENDER": 654 * engines->engines[i].instance.engine_class == 655 * DRM_XE_ENGINE_CLASS_COPY ? "COPY": 656 * engines->engines[i].instance.engine_class == 657 * DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE": 658 * engines->engines[i].instance.engine_class == 659 * DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE": 660 * engines->engines[i].instance.engine_class == 661 * DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE": 662 * "UNKNOWN"); 663 * } 664 * free(engines); 665 */ 666 struct drm_xe_device_query { 667 /** @extensions: Pointer to the first extension struct, if any */ 668 __u64 extensions; 669 670 #define DRM_XE_DEVICE_QUERY_ENGINES 0 671 #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1 672 #define DRM_XE_DEVICE_QUERY_CONFIG 2 673 #define DRM_XE_DEVICE_QUERY_GT_LIST 3 674 #define DRM_XE_DEVICE_QUERY_HWCONFIG 4 675 #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5 676 #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6 677 #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7 678 /** @query: The type of data to query */ 679 __u32 query; 680 681 /** @size: Size of the queried data */ 682 __u32 size; 683 684 /** @data: Queried data is placed here */ 685 __u64 data; 686 687 /** @reserved: Reserved */ 688 __u64 reserved[2]; 689 }; 690 691 /** 692 * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for 693 * gem creation 694 * 695 * The @flags can be: 696 * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING 697 * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT 698 * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a 699 * possible placement, ensure that the corresponding VRAM allocation 700 * will always use the CPU accessible part of VRAM. This is important 701 * for small-bar systems (on full-bar systems this gets turned into a 702 * noop). 703 * Note1: System memory can be used as an extra placement if the kernel 704 * should spill the allocation to system memory, if space can't be made 705 * available in the CPU accessible part of VRAM (giving the same 706 * behaviour as the i915 interface, see 707 * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS). 708 * Note2: For clear-color CCS surfaces the kernel needs to read the 709 * clear-color value stored in the buffer, and on discrete platforms we 710 * need to use VRAM for display surfaces, therefore the kernel requires 711 * setting this flag for such objects, otherwise an error is thrown on 712 * small-bar systems. 713 * 714 * @cpu_caching supports the following values: 715 * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back 716 * caching. On iGPU this can't be used for scanout surfaces. Currently 717 * not allowed for objects placed in VRAM. 718 * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This 719 * is uncached. Scanout surfaces should likely use this. All objects 720 * that can be placed in VRAM must use this. 721 */ 722 struct drm_xe_gem_create { 723 /** @extensions: Pointer to the first extension struct, if any */ 724 __u64 extensions; 725 726 /** 727 * @size: Size of the object to be created, must match region 728 * (system or vram) minimum alignment (&min_page_size). 729 */ 730 __u64 size; 731 732 /** 733 * @placement: A mask of memory instances of where BO can be placed. 734 * Each index in this mask refers directly to the struct 735 * drm_xe_query_mem_regions' instance, no assumptions should 736 * be made about order. The type of each region is described 737 * by struct drm_xe_query_mem_regions' mem_class. 738 */ 739 __u32 placement; 740 741 #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0) 742 #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1) 743 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2) 744 /** 745 * @flags: Flags, currently a mask of memory instances of where BO can 746 * be placed 747 */ 748 __u32 flags; 749 750 /** 751 * @vm_id: Attached VM, if any 752 * 753 * If a VM is specified, this BO must: 754 * 755 * 1. Only ever be bound to that VM. 756 * 2. Cannot be exported as a PRIME fd. 757 */ 758 __u32 vm_id; 759 760 /** 761 * @handle: Returned handle for the object. 762 * 763 * Object handles are nonzero. 764 */ 765 __u32 handle; 766 767 #define DRM_XE_GEM_CPU_CACHING_WB 1 768 #define DRM_XE_GEM_CPU_CACHING_WC 2 769 /** 770 * @cpu_caching: The CPU caching mode to select for this object. If 771 * mmaping the object the mode selected here will also be used. 772 */ 773 __u16 cpu_caching; 774 /** @pad: MBZ */ 775 __u16 pad[3]; 776 777 /** @reserved: Reserved */ 778 __u64 reserved[2]; 779 }; 780 781 /** 782 * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET 783 */ 784 struct drm_xe_gem_mmap_offset { 785 /** @extensions: Pointer to the first extension struct, if any */ 786 __u64 extensions; 787 788 /** @handle: Handle for the object being mapped. */ 789 __u32 handle; 790 791 /** @flags: Must be zero */ 792 __u32 flags; 793 794 /** @offset: The fake offset to use for subsequent mmap call */ 795 __u64 offset; 796 797 /** @reserved: Reserved */ 798 __u64 reserved[2]; 799 }; 800 801 /** 802 * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE 803 * 804 * The @flags can be: 805 * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE 806 * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts 807 * exec submissions to its exec_queues that don't have an upper time 808 * limit on the job execution time. But exec submissions to these 809 * don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ, 810 * DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF, 811 * used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL. 812 * LR VMs can be created in recoverable page-fault mode using 813 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it. 814 * If that flag is omitted, the UMD can not rely on the slightly 815 * different per-VM overcommit semantics that are enabled by 816 * DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may 817 * still enable recoverable pagefaults if supported by the device. 818 * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also 819 * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on 820 * demand when accessed, and also allows per-VM overcommit of memory. 821 * The xe driver internally uses recoverable pagefaults to implement 822 * this. 823 */ 824 struct drm_xe_vm_create { 825 /** @extensions: Pointer to the first extension struct, if any */ 826 __u64 extensions; 827 828 #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0) 829 #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1) 830 #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2) 831 /** @flags: Flags */ 832 __u32 flags; 833 834 /** @vm_id: Returned VM ID */ 835 __u32 vm_id; 836 837 /** @reserved: Reserved */ 838 __u64 reserved[2]; 839 }; 840 841 /** 842 * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY 843 */ 844 struct drm_xe_vm_destroy { 845 /** @vm_id: VM ID */ 846 __u32 vm_id; 847 848 /** @pad: MBZ */ 849 __u32 pad; 850 851 /** @reserved: Reserved */ 852 __u64 reserved[2]; 853 }; 854 855 /** 856 * struct drm_xe_vm_bind_op - run bind operations 857 * 858 * The @op can be: 859 * - %DRM_XE_VM_BIND_OP_MAP 860 * - %DRM_XE_VM_BIND_OP_UNMAP 861 * - %DRM_XE_VM_BIND_OP_MAP_USERPTR 862 * - %DRM_XE_VM_BIND_OP_UNMAP_ALL 863 * - %DRM_XE_VM_BIND_OP_PREFETCH 864 * 865 * and the @flags can be: 866 * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page 867 * tables are setup with a special bit which indicates writes are 868 * dropped and all reads return zero. In the future, the NULL flags 869 * will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO 870 * handle MBZ, and the BO offset MBZ. This flag is intended to 871 * implement VK sparse bindings. 872 */ 873 struct drm_xe_vm_bind_op { 874 /** @extensions: Pointer to the first extension struct, if any */ 875 __u64 extensions; 876 877 /** 878 * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP 879 */ 880 __u32 obj; 881 882 /** 883 * @pat_index: The platform defined @pat_index to use for this mapping. 884 * The index basically maps to some predefined memory attributes, 885 * including things like caching, coherency, compression etc. The exact 886 * meaning of the pat_index is platform specific and defined in the 887 * Bspec and PRMs. When the KMD sets up the binding the index here is 888 * encoded into the ppGTT PTE. 889 * 890 * For coherency the @pat_index needs to be at least 1way coherent when 891 * drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD 892 * will extract the coherency mode from the @pat_index and reject if 893 * there is a mismatch (see note below for pre-MTL platforms). 894 * 895 * Note: On pre-MTL platforms there is only a caching mode and no 896 * explicit coherency mode, but on such hardware there is always a 897 * shared-LLC (or is dgpu) so all GT memory accesses are coherent with 898 * CPU caches even with the caching mode set as uncached. It's only the 899 * display engine that is incoherent (on dgpu it must be in VRAM which 900 * is always mapped as WC on the CPU). However to keep the uapi somewhat 901 * consistent with newer platforms the KMD groups the different cache 902 * levels into the following coherency buckets on all pre-MTL platforms: 903 * 904 * ppGTT UC -> COH_NONE 905 * ppGTT WC -> COH_NONE 906 * ppGTT WT -> COH_NONE 907 * ppGTT WB -> COH_AT_LEAST_1WAY 908 * 909 * In practice UC/WC/WT should only ever used for scanout surfaces on 910 * such platforms (or perhaps in general for dma-buf if shared with 911 * another device) since it is only the display engine that is actually 912 * incoherent. Everything else should typically use WB given that we 913 * have a shared-LLC. On MTL+ this completely changes and the HW 914 * defines the coherency mode as part of the @pat_index, where 915 * incoherent GT access is possible. 916 * 917 * Note: For userptr and externally imported dma-buf the kernel expects 918 * either 1WAY or 2WAY for the @pat_index. 919 * 920 * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions 921 * on the @pat_index. For such mappings there is no actual memory being 922 * mapped (the address in the PTE is invalid), so the various PAT memory 923 * attributes likely do not apply. Simply leaving as zero is one 924 * option (still a valid pat_index). 925 */ 926 __u16 pat_index; 927 928 /** @pad: MBZ */ 929 __u16 pad; 930 931 union { 932 /** 933 * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE, 934 * ignored for unbind 935 */ 936 __u64 obj_offset; 937 938 /** @userptr: user pointer to bind on */ 939 __u64 userptr; 940 }; 941 942 /** 943 * @range: Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL 944 */ 945 __u64 range; 946 947 /** @addr: Address to operate on, MBZ for UNMAP_ALL */ 948 __u64 addr; 949 950 #define DRM_XE_VM_BIND_OP_MAP 0x0 951 #define DRM_XE_VM_BIND_OP_UNMAP 0x1 952 #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2 953 #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3 954 #define DRM_XE_VM_BIND_OP_PREFETCH 0x4 955 /** @op: Bind operation to perform */ 956 __u32 op; 957 958 #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2) 959 #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3) 960 /** @flags: Bind flags */ 961 __u32 flags; 962 963 /** 964 * @prefetch_mem_region_instance: Memory region to prefetch VMA to. 965 * It is a region instance, not a mask. 966 * To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation. 967 */ 968 __u32 prefetch_mem_region_instance; 969 970 /** @pad2: MBZ */ 971 __u32 pad2; 972 973 /** @reserved: Reserved */ 974 __u64 reserved[3]; 975 }; 976 977 /** 978 * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND 979 * 980 * Below is an example of a minimal use of @drm_xe_vm_bind to 981 * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to 982 * illustrate `userptr`. It can be synchronized by using the example 983 * provided for @drm_xe_sync. 984 * 985 * .. code-block:: C 986 * 987 * data = aligned_alloc(ALIGNMENT, BO_SIZE); 988 * struct drm_xe_vm_bind bind = { 989 * .vm_id = vm, 990 * .num_binds = 1, 991 * .bind.obj = 0, 992 * .bind.obj_offset = to_user_pointer(data), 993 * .bind.range = BO_SIZE, 994 * .bind.addr = BIND_ADDRESS, 995 * .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR, 996 * .bind.flags = 0, 997 * .num_syncs = 1, 998 * .syncs = &sync, 999 * .exec_queue_id = 0, 1000 * }; 1001 * ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind); 1002 * 1003 */ 1004 struct drm_xe_vm_bind { 1005 /** @extensions: Pointer to the first extension struct, if any */ 1006 __u64 extensions; 1007 1008 /** @vm_id: The ID of the VM to bind to */ 1009 __u32 vm_id; 1010 1011 /** 1012 * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND 1013 * and exec queue must have same vm_id. If zero, the default VM bind engine 1014 * is used. 1015 */ 1016 __u32 exec_queue_id; 1017 1018 /** @pad: MBZ */ 1019 __u32 pad; 1020 1021 /** @num_binds: number of binds in this IOCTL */ 1022 __u32 num_binds; 1023 1024 union { 1025 /** @bind: used if num_binds == 1 */ 1026 struct drm_xe_vm_bind_op bind; 1027 1028 /** 1029 * @vector_of_binds: userptr to array of struct 1030 * drm_xe_vm_bind_op if num_binds > 1 1031 */ 1032 __u64 vector_of_binds; 1033 }; 1034 1035 /** @pad2: MBZ */ 1036 __u32 pad2; 1037 1038 /** @num_syncs: amount of syncs to wait on */ 1039 __u32 num_syncs; 1040 1041 /** @syncs: pointer to struct drm_xe_sync array */ 1042 __u64 syncs; 1043 1044 /** @reserved: Reserved */ 1045 __u64 reserved[2]; 1046 }; 1047 1048 /** 1049 * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE 1050 * 1051 * The example below shows how to use @drm_xe_exec_queue_create to create 1052 * a simple exec_queue (no parallel submission) of class 1053 * &DRM_XE_ENGINE_CLASS_RENDER. 1054 * 1055 * .. code-block:: C 1056 * 1057 * struct drm_xe_engine_class_instance instance = { 1058 * .engine_class = DRM_XE_ENGINE_CLASS_RENDER, 1059 * }; 1060 * struct drm_xe_exec_queue_create exec_queue_create = { 1061 * .extensions = 0, 1062 * .vm_id = vm, 1063 * .num_bb_per_exec = 1, 1064 * .num_eng_per_bb = 1, 1065 * .instances = to_user_pointer(&instance), 1066 * }; 1067 * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create); 1068 * 1069 */ 1070 struct drm_xe_exec_queue_create { 1071 #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 1072 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 1073 #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 1074 1075 /** @extensions: Pointer to the first extension struct, if any */ 1076 __u64 extensions; 1077 1078 /** @width: submission width (number BB per exec) for this exec queue */ 1079 __u16 width; 1080 1081 /** @num_placements: number of valid placements for this exec queue */ 1082 __u16 num_placements; 1083 1084 /** @vm_id: VM to use for this exec queue */ 1085 __u32 vm_id; 1086 1087 /** @flags: MBZ */ 1088 __u32 flags; 1089 1090 /** @exec_queue_id: Returned exec queue ID */ 1091 __u32 exec_queue_id; 1092 1093 /** 1094 * @instances: user pointer to a 2-d array of struct 1095 * drm_xe_engine_class_instance 1096 * 1097 * length = width (i) * num_placements (j) 1098 * index = j + i * width 1099 */ 1100 __u64 instances; 1101 1102 /** @reserved: Reserved */ 1103 __u64 reserved[2]; 1104 }; 1105 1106 /** 1107 * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY 1108 */ 1109 struct drm_xe_exec_queue_destroy { 1110 /** @exec_queue_id: Exec queue ID */ 1111 __u32 exec_queue_id; 1112 1113 /** @pad: MBZ */ 1114 __u32 pad; 1115 1116 /** @reserved: Reserved */ 1117 __u64 reserved[2]; 1118 }; 1119 1120 /** 1121 * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY 1122 * 1123 * The @property can be: 1124 * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 1125 */ 1126 struct drm_xe_exec_queue_get_property { 1127 /** @extensions: Pointer to the first extension struct, if any */ 1128 __u64 extensions; 1129 1130 /** @exec_queue_id: Exec queue ID */ 1131 __u32 exec_queue_id; 1132 1133 #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 1134 /** @property: property to get */ 1135 __u32 property; 1136 1137 /** @value: property value */ 1138 __u64 value; 1139 1140 /** @reserved: Reserved */ 1141 __u64 reserved[2]; 1142 }; 1143 1144 /** 1145 * struct drm_xe_sync - sync object 1146 * 1147 * The @type can be: 1148 * - %DRM_XE_SYNC_TYPE_SYNCOBJ 1149 * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 1150 * - %DRM_XE_SYNC_TYPE_USER_FENCE 1151 * 1152 * and the @flags can be: 1153 * - %DRM_XE_SYNC_FLAG_SIGNAL 1154 * 1155 * A minimal use of @drm_xe_sync looks like this: 1156 * 1157 * .. code-block:: C 1158 * 1159 * struct drm_xe_sync sync = { 1160 * .flags = DRM_XE_SYNC_FLAG_SIGNAL, 1161 * .type = DRM_XE_SYNC_TYPE_SYNCOBJ, 1162 * }; 1163 * struct drm_syncobj_create syncobj_create = { 0 }; 1164 * ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create); 1165 * sync.handle = syncobj_create.handle; 1166 * ... 1167 * use of &sync in drm_xe_exec or drm_xe_vm_bind 1168 * ... 1169 * struct drm_syncobj_wait wait = { 1170 * .handles = &sync.handle, 1171 * .timeout_nsec = INT64_MAX, 1172 * .count_handles = 1, 1173 * .flags = 0, 1174 * .first_signaled = 0, 1175 * .pad = 0, 1176 * }; 1177 * ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait); 1178 */ 1179 struct drm_xe_sync { 1180 /** @extensions: Pointer to the first extension struct, if any */ 1181 __u64 extensions; 1182 1183 #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0 1184 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1 1185 #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2 1186 /** @type: Type of the this sync object */ 1187 __u32 type; 1188 1189 #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0) 1190 /** @flags: Sync Flags */ 1191 __u32 flags; 1192 1193 union { 1194 /** @handle: Handle for the object */ 1195 __u32 handle; 1196 1197 /** 1198 * @addr: Address of user fence. When sync is passed in via exec 1199 * IOCTL this is a GPU address in the VM. When sync passed in via 1200 * VM bind IOCTL this is a user pointer. In either case, it is 1201 * the users responsibility that this address is present and 1202 * mapped when the user fence is signalled. Must be qword 1203 * aligned. 1204 */ 1205 __u64 addr; 1206 }; 1207 1208 /** 1209 * @timeline_value: Input for the timeline sync object. Needs to be 1210 * different than 0 when used with %DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ. 1211 */ 1212 __u64 timeline_value; 1213 1214 /** @reserved: Reserved */ 1215 __u64 reserved[2]; 1216 }; 1217 1218 /** 1219 * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC 1220 * 1221 * This is an example to use @drm_xe_exec for execution of the object 1222 * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue 1223 * (see example in @drm_xe_exec_queue_create). It can be synchronized 1224 * by using the example provided for @drm_xe_sync. 1225 * 1226 * .. code-block:: C 1227 * 1228 * struct drm_xe_exec exec = { 1229 * .exec_queue_id = exec_queue, 1230 * .syncs = &sync, 1231 * .num_syncs = 1, 1232 * .address = BIND_ADDRESS, 1233 * .num_batch_buffer = 1, 1234 * }; 1235 * ioctl(fd, DRM_IOCTL_XE_EXEC, &exec); 1236 * 1237 */ 1238 struct drm_xe_exec { 1239 /** @extensions: Pointer to the first extension struct, if any */ 1240 __u64 extensions; 1241 1242 /** @exec_queue_id: Exec queue ID for the batch buffer */ 1243 __u32 exec_queue_id; 1244 1245 /** @num_syncs: Amount of struct drm_xe_sync in array. */ 1246 __u32 num_syncs; 1247 1248 /** @syncs: Pointer to struct drm_xe_sync array. */ 1249 __u64 syncs; 1250 1251 /** 1252 * @address: address of batch buffer if num_batch_buffer == 1 or an 1253 * array of batch buffer addresses 1254 */ 1255 __u64 address; 1256 1257 /** 1258 * @num_batch_buffer: number of batch buffer in this exec, must match 1259 * the width of the engine 1260 */ 1261 __u16 num_batch_buffer; 1262 1263 /** @pad: MBZ */ 1264 __u16 pad[3]; 1265 1266 /** @reserved: Reserved */ 1267 __u64 reserved[2]; 1268 }; 1269 1270 /** 1271 * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE 1272 * 1273 * Wait on user fence, XE will wake-up on every HW engine interrupt in the 1274 * instances list and check if user fence is complete:: 1275 * 1276 * (*addr & MASK) OP (VALUE & MASK) 1277 * 1278 * Returns to user on user fence completion or timeout. 1279 * 1280 * The @op can be: 1281 * - %DRM_XE_UFENCE_WAIT_OP_EQ 1282 * - %DRM_XE_UFENCE_WAIT_OP_NEQ 1283 * - %DRM_XE_UFENCE_WAIT_OP_GT 1284 * - %DRM_XE_UFENCE_WAIT_OP_GTE 1285 * - %DRM_XE_UFENCE_WAIT_OP_LT 1286 * - %DRM_XE_UFENCE_WAIT_OP_LTE 1287 * 1288 * and the @flags can be: 1289 * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME 1290 * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP 1291 * 1292 * The @mask values can be for example: 1293 * - 0xffu for u8 1294 * - 0xffffu for u16 1295 * - 0xffffffffu for u32 1296 * - 0xffffffffffffffffu for u64 1297 */ 1298 struct drm_xe_wait_user_fence { 1299 /** @extensions: Pointer to the first extension struct, if any */ 1300 __u64 extensions; 1301 1302 /** 1303 * @addr: user pointer address to wait on, must qword aligned 1304 */ 1305 __u64 addr; 1306 1307 #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0 1308 #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1 1309 #define DRM_XE_UFENCE_WAIT_OP_GT 0x2 1310 #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3 1311 #define DRM_XE_UFENCE_WAIT_OP_LT 0x4 1312 #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5 1313 /** @op: wait operation (type of comparison) */ 1314 __u16 op; 1315 1316 #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0) 1317 /** @flags: wait flags */ 1318 __u16 flags; 1319 1320 /** @pad: MBZ */ 1321 __u32 pad; 1322 1323 /** @value: compare value */ 1324 __u64 value; 1325 1326 /** @mask: comparison mask */ 1327 __u64 mask; 1328 1329 /** 1330 * @timeout: how long to wait before bailing, value in nanoseconds. 1331 * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout) 1332 * it contains timeout expressed in nanoseconds to wait (fence will 1333 * expire at now() + timeout). 1334 * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait 1335 * will end at timeout (uses system MONOTONIC_CLOCK). 1336 * Passing negative timeout leads to neverending wait. 1337 * 1338 * On relative timeout this value is updated with timeout left 1339 * (for restarting the call in case of signal delivery). 1340 * On absolute timeout this value stays intact (restarted call still 1341 * expire at the same point of time). 1342 */ 1343 __s64 timeout; 1344 1345 /** @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl */ 1346 __u32 exec_queue_id; 1347 1348 /** @pad2: MBZ */ 1349 __u32 pad2; 1350 1351 /** @reserved: Reserved */ 1352 __u64 reserved[2]; 1353 }; 1354 1355 #if defined(__cplusplus) 1356 } 1357 #endif 1358 1359 #endif /* _XE_DRM_H_ */ 1360