1 /*
2 * Copyright © 2021 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * SPDX-License-Identifier: MIT
6 */
7
8 #ifndef AC_SURFACE_TEST_COMMON_H
9 #define AC_SURFACE_TEST_COMMON_H
10
11 #include "ac_gpu_info.h"
12 #include "amdgfxregs.h"
13 #include "addrlib/src/amdgpu_asic_addr.h"
14
15 typedef void (*gpu_init_func)(struct radeon_info *info);
16
init_vega10(struct radeon_info * info)17 static void init_vega10(struct radeon_info *info)
18 {
19 info->family = CHIP_VEGA10;
20 info->gfx_level = GFX9;
21 info->family_id = AMDGPU_FAMILY_AI;
22 info->chip_external_rev = 0x01;
23 info->use_display_dcc_unaligned = false;
24 info->use_display_dcc_with_retile_blit = false;
25 info->has_graphics = true;
26 info->tcc_cache_line_size = 64;
27 info->max_render_backends = 16;
28
29 info->gb_addr_config = 0x2a114042;
30 }
31
init_vega20(struct radeon_info * info)32 static void init_vega20(struct radeon_info *info)
33 {
34 info->family = CHIP_VEGA20;
35 info->gfx_level = GFX9;
36 info->family_id = AMDGPU_FAMILY_AI;
37 info->chip_external_rev = 0x30;
38 info->use_display_dcc_unaligned = false;
39 info->use_display_dcc_with_retile_blit = false;
40 info->has_graphics = true;
41 info->tcc_cache_line_size = 64;
42 info->max_render_backends = 16;
43
44 info->gb_addr_config = 0x2a114042;
45 }
46
47
init_raven(struct radeon_info * info)48 static void init_raven(struct radeon_info *info)
49 {
50 info->family = CHIP_RAVEN;
51 info->gfx_level = GFX9;
52 info->family_id = AMDGPU_FAMILY_RV;
53 info->chip_external_rev = 0x01;
54 info->use_display_dcc_unaligned = false;
55 info->use_display_dcc_with_retile_blit = true;
56 info->has_graphics = true;
57 info->tcc_cache_line_size = 64;
58 info->max_render_backends = 2;
59
60 info->gb_addr_config = 0x24000042;
61 }
62
init_raven2(struct radeon_info * info)63 static void init_raven2(struct radeon_info *info)
64 {
65 info->family = CHIP_RAVEN2;
66 info->gfx_level = GFX9;
67 info->family_id = AMDGPU_FAMILY_RV;
68 info->chip_external_rev = 0x82;
69 info->use_display_dcc_unaligned = true;
70 info->use_display_dcc_with_retile_blit = false;
71 info->has_graphics = true;
72 info->tcc_cache_line_size = 64;
73 info->max_render_backends = 1;
74
75 info->gb_addr_config = 0x26013041;
76 }
77
init_navi10(struct radeon_info * info)78 static void init_navi10(struct radeon_info *info)
79 {
80 info->family = CHIP_NAVI10;
81 info->gfx_level = GFX10;
82 info->family_id = AMDGPU_FAMILY_NV;
83 info->chip_external_rev = 3;
84 info->use_display_dcc_unaligned = false;
85 info->use_display_dcc_with_retile_blit = false;
86 info->has_graphics = true;
87 info->tcc_cache_line_size = 128;
88
89 info->gb_addr_config = 0x00100044;
90 }
91
init_navi14(struct radeon_info * info)92 static void init_navi14(struct radeon_info *info)
93 {
94 info->family = CHIP_NAVI14;
95 info->gfx_level = GFX10;
96 info->family_id = AMDGPU_FAMILY_NV;
97 info->chip_external_rev = 0x15;
98 info->use_display_dcc_unaligned = false;
99 info->use_display_dcc_with_retile_blit = false;
100 info->has_graphics = true;
101 info->tcc_cache_line_size = 128;
102
103 info->gb_addr_config = 0x00000043;
104 }
105
init_gfx103(struct radeon_info * info)106 static void init_gfx103(struct radeon_info *info)
107 {
108 info->family = CHIP_NAVI21; /* This doesn't affect tests. */
109 info->gfx_level = GFX10_3;
110 info->family_id = AMDGPU_FAMILY_NV;
111 info->chip_external_rev = 0x28;
112 info->use_display_dcc_unaligned = false;
113 info->use_display_dcc_with_retile_blit = true;
114 info->has_graphics = true;
115 info->tcc_cache_line_size = 128;
116 info->has_rbplus = true;
117 info->rbplus_allowed = true;
118
119 info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */
120 }
121
init_gfx11(struct radeon_info * info)122 static void init_gfx11(struct radeon_info *info)
123 {
124 info->family = CHIP_NAVI31;
125 info->gfx_level = GFX11;
126 info->family_id = FAMILY_NV3;
127 info->chip_external_rev = 0x01;
128 info->use_display_dcc_unaligned = false;
129 info->use_display_dcc_with_retile_blit = true;
130 info->has_graphics = true;
131 info->tcc_cache_line_size = 128;
132 info->has_rbplus = true;
133 info->rbplus_allowed = true;
134
135 info->gb_addr_config = 0x00000040; /* Other fields are set by test cases. */
136 }
137
138 struct testcase {
139 const char *name;
140 gpu_init_func init;
141 int banks_or_pkrs;
142 int pipes;
143 int se;
144 int rb_per_se;
145 };
146
147 static struct testcase testcases[] = {
148 {"vega10", init_vega10, 4, 2, 2, 2},
149 {"vega10_diff_bank", init_vega10, 3, 2, 2, 2},
150 {"vega10_diff_rb", init_vega10, 4, 2, 2, 0},
151 {"vega10_diff_pipe", init_vega10, 4, 0, 2, 2},
152 {"vega10_diff_se", init_vega10, 4, 2, 1, 2},
153 {"vega20", init_vega20, 4, 2, 2, 2},
154 {"raven", init_raven, 0, 2, 0, 1},
155 {"raven2", init_raven2, 3, 1, 0, 1},
156 /* Just test a bunch of different numbers. (packers, pipes) */
157 {"navi10", init_navi10, 0, 4},
158 {"navi10_diff_pipe", init_navi10, 0, 3},
159 {"navi10_diff_pkr", init_navi10, 1, 4},
160 {"navi14", init_navi14, 1, 3},
161 {"gfx103_16pipe", init_gfx103, 4, 4},
162 {"gfx103_16pipe_8pkr", init_gfx103, 3, 4},
163 {"gfx103_8pipe", init_gfx103, 3, 3},
164 {"gfx103_4pipe", init_gfx103, 2, 2},
165 {"gfx103_4pipe_2pkr", init_gfx103, 1, 2},
166 {"gfx103_4pipe_1pkr", init_gfx103, 0, 2},
167 {"gfx103_2pipe_1pkr", init_gfx103, 0, 1},
168 {"gfx11_32pipe", init_gfx11, 5, 5},
169 {"gfx11_16pipe", init_gfx11, 4, 4},
170 {"gfx11_8pipe", init_gfx11, 3, 3},
171 {"gfx11_4pipe", init_gfx11, 2, 2},
172 {"gfx11_4pipe_2pkr", init_gfx11, 1, 2},
173 {"gfx11_4pipe_1pkr", init_gfx11, 0, 2},
174 {"gfx11_2pipe_1pkr", init_gfx11, 0, 1},
175 };
176
get_radeon_info(struct testcase * testcase)177 static struct radeon_info get_radeon_info(struct testcase *testcase)
178 {
179 struct radeon_info info = {
180 .drm_major = 3,
181 .drm_minor = 30,
182 };
183
184 testcase->init(&info);
185
186 switch(info.gfx_level) {
187 case GFX9:
188 info.gb_addr_config = (info.gb_addr_config &
189 C_0098F8_NUM_PIPES &
190 C_0098F8_NUM_BANKS &
191 C_0098F8_NUM_SHADER_ENGINES_GFX9 &
192 C_0098F8_NUM_RB_PER_SE) |
193 S_0098F8_NUM_PIPES(testcase->pipes) |
194 S_0098F8_NUM_BANKS(testcase->banks_or_pkrs) |
195 S_0098F8_NUM_SHADER_ENGINES_GFX9(testcase->se) |
196 S_0098F8_NUM_RB_PER_SE(testcase->rb_per_se);
197 break;
198 case GFX10:
199 case GFX10_3:
200 case GFX11:
201 info.gb_addr_config = (info.gb_addr_config &
202 C_0098F8_NUM_PIPES &
203 C_0098F8_NUM_PKRS) |
204 S_0098F8_NUM_PIPES(testcase->pipes) |
205 S_0098F8_NUM_PKRS(testcase->banks_or_pkrs);
206 /* 1 packer implies 1 RB except gfx10 where the field is ignored. */
207 info.max_render_backends = info.gfx_level == GFX10 || testcase->banks_or_pkrs ? 2 : 1;
208 break;
209 default:
210 unreachable("Unhandled generation");
211 }
212
213 return info;
214 }
215
216 #endif
217