1 /* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2010 Marek Olšák <maraeo@gmail.com> 4 * 5 * SPDX-License-Identifier: MIT 6 */ 7 8 #ifndef AMD_FAMILY_H 9 #define AMD_FAMILY_H 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 enum radeon_family 16 { 17 CHIP_UNKNOWN = 0, 18 /* R3xx-based cores. (GFX2) */ 19 CHIP_R300, 20 CHIP_R350, 21 CHIP_RV350, 22 CHIP_RV370, 23 CHIP_RV380, 24 CHIP_RS400, 25 CHIP_RC410, 26 CHIP_RS480, 27 /* R4xx-based cores. (GFX2) */ 28 CHIP_R420, 29 CHIP_R423, 30 CHIP_R430, 31 CHIP_R480, 32 CHIP_R481, 33 CHIP_RV410, 34 CHIP_RS600, 35 CHIP_RS690, 36 CHIP_RS740, 37 /* R5xx-based cores. (GFX2) */ 38 CHIP_RV515, 39 CHIP_R520, 40 CHIP_RV530, 41 CHIP_R580, 42 CHIP_RV560, 43 CHIP_RV570, 44 /* GFX3 (R6xx) */ 45 CHIP_R600, 46 CHIP_RV610, 47 CHIP_RV630, 48 CHIP_RV670, 49 CHIP_RV620, 50 CHIP_RV635, 51 CHIP_RS780, 52 CHIP_RS880, 53 /* GFX3 (R7xx) */ 54 CHIP_RV770, 55 CHIP_RV730, 56 CHIP_RV710, 57 CHIP_RV740, 58 /* GFX4 (Evergreen) */ 59 CHIP_CEDAR, 60 CHIP_REDWOOD, 61 CHIP_JUNIPER, 62 CHIP_CYPRESS, 63 CHIP_HEMLOCK, 64 CHIP_PALM, 65 CHIP_SUMO, 66 CHIP_SUMO2, 67 CHIP_BARTS, 68 CHIP_TURKS, 69 CHIP_CAICOS, 70 /* GFX5 (Northern Islands) */ 71 CHIP_CAYMAN, 72 CHIP_ARUBA, 73 /* GFX6 (Southern Islands) */ 74 CHIP_TAHITI, 75 CHIP_PITCAIRN, 76 CHIP_VERDE, 77 CHIP_OLAND, 78 CHIP_HAINAN, 79 /* GFX7 (Sea Islands) */ 80 CHIP_BONAIRE, 81 CHIP_KAVERI, 82 CHIP_KABINI, 83 CHIP_HAWAII, /* Radeon 290, 390 */ 84 /* GFX8 (Volcanic Islands & Polaris) */ 85 CHIP_TONGA, /* Radeon 285, 380 */ 86 CHIP_ICELAND, 87 CHIP_CARRIZO, 88 CHIP_FIJI, /* Radeon Fury */ 89 CHIP_STONEY, 90 CHIP_POLARIS10, /* Radeon 470, 480, 570, 580, 590 */ 91 CHIP_POLARIS11, /* Radeon 460, 560 */ 92 CHIP_POLARIS12, /* Radeon 540, 550 */ 93 CHIP_VEGAM, 94 /* GFX9 (Vega) */ 95 CHIP_VEGA10, /* Vega 56, 64 */ 96 CHIP_VEGA12, 97 CHIP_VEGA20, /* Radeon VII, MI50 */ 98 CHIP_RAVEN, /* Ryzen 2000, 3000 */ 99 CHIP_RAVEN2, /* Ryzen 2200U, 3200U */ 100 CHIP_RENOIR, /* Ryzen 4000, 5000 */ 101 CHIP_MI100, 102 CHIP_MI200, 103 CHIP_GFX940, 104 /* GFX10.1 (RDNA 1) */ 105 CHIP_NAVI10, /* Radeon 5600, 5700 */ 106 CHIP_NAVI12, /* Radeon Pro 5600M */ 107 CHIP_NAVI14, /* Radeon 5300, 5500 */ 108 /* GFX10.3 (RDNA 2) */ 109 CHIP_NAVI21, /* Radeon 6800, 6900 (formerly "Sienna Cichlid") */ 110 CHIP_NAVI22, /* Radeon 6700 (formerly "Navy Flounder") */ 111 CHIP_VANGOGH, /* Steam Deck */ 112 CHIP_NAVI23, /* Radeon 6600 (formerly "Dimgrey Cavefish") */ 113 CHIP_NAVI24, /* Radeon 6400, 6500 (formerly "Beige Goby") */ 114 CHIP_REMBRANDT, /* Ryzen 6000 (formerly "Yellow Carp") */ 115 CHIP_RAPHAEL_MENDOCINO, /* Ryzen 7000(X), Ryzen 7045, Ryzen 7020 */ 116 /* GFX11 (RDNA 3) */ 117 CHIP_NAVI31, /* Radeon 7900 */ 118 CHIP_NAVI32, /* Radeon 7800, 7700 */ 119 CHIP_NAVI33, /* Radeon 7600, 7700S (mobile) */ 120 CHIP_GFX1103_R1, 121 CHIP_GFX1103_R2, 122 CHIP_GFX1150, 123 CHIP_LAST, 124 }; 125 126 enum amd_gfx_level 127 { 128 CLASS_UNKNOWN = 0, 129 R300, 130 R400, 131 R500, 132 R600, 133 R700, 134 EVERGREEN, 135 CAYMAN, 136 GFX6, 137 GFX7, 138 GFX8, 139 GFX9, 140 GFX10, 141 GFX10_3, 142 GFX11, 143 GFX11_5, 144 145 NUM_GFX_VERSIONS, 146 }; 147 148 enum amd_ip_type 149 { 150 AMD_IP_GFX = 0, 151 AMD_IP_COMPUTE, 152 AMD_IP_SDMA, 153 AMD_IP_UVD, 154 AMD_IP_VCE, 155 AMD_IP_UVD_ENC, 156 AMD_IP_VCN_DEC, 157 AMD_IP_VCN_ENC, 158 AMD_IP_VCN_UNIFIED = AMD_IP_VCN_ENC, 159 AMD_IP_VCN_JPEG, 160 AMD_IP_VPE, 161 AMD_NUM_IP_TYPES, 162 }; 163 164 enum amd_vram_type { 165 AMD_VRAM_TYPE_UNKNOWN = 0, 166 AMD_VRAM_TYPE_GDDR1, 167 AMD_VRAM_TYPE_DDR2, 168 AMD_VRAM_TYPE_GDDR3, 169 AMD_VRAM_TYPE_GDDR4, 170 AMD_VRAM_TYPE_GDDR5, 171 AMD_VRAM_TYPE_HBM, 172 AMD_VRAM_TYPE_DDR3, 173 AMD_VRAM_TYPE_DDR4, 174 AMD_VRAM_TYPE_GDDR6, 175 AMD_VRAM_TYPE_DDR5, 176 AMD_VRAM_TYPE_LPDDR4, 177 AMD_VRAM_TYPE_LPDDR5, 178 }; 179 180 enum vcn_version{ 181 VCN_UNKNOWN, 182 VCN_1_0_0, 183 VCN_1_0_1, 184 185 VCN_2_0_0, 186 VCN_2_0_2, 187 VCN_2_0_3, 188 VCN_2_2_0, 189 VCN_2_5_0, 190 VCN_2_6_0, 191 192 VCN_3_0_0, 193 VCN_3_0_2, 194 VCN_3_0_16, 195 VCN_3_0_33, 196 VCN_3_1_1, 197 VCN_3_1_2, 198 199 VCN_4_0_0, 200 VCN_4_0_2, 201 VCN_4_0_3, 202 VCN_4_0_4, 203 VCN_4_0_5, 204 }; 205 206 #define SDMA_VERSION_VALUE(major, minor) (((major) << 8) | (minor)) 207 208 enum sdma_version { 209 SDMA_UNKNOWN = 0, 210 /* GFX6 */ 211 SDMA_1_0 = SDMA_VERSION_VALUE(1, 0), 212 213 /* GFX7 */ 214 SDMA_2_0 = SDMA_VERSION_VALUE(2, 0), 215 216 /* GFX8 */ 217 SDMA_2_4 = SDMA_VERSION_VALUE(2, 4), 218 SDMA_3_0 = SDMA_VERSION_VALUE(3, 0), 219 SDMA_3_1 = SDMA_VERSION_VALUE(3, 1), 220 221 /* GFX9 */ 222 SDMA_4_0 = SDMA_VERSION_VALUE(4, 0), 223 SDMA_4_1 = SDMA_VERSION_VALUE(4, 1), 224 SDMA_4_2 = SDMA_VERSION_VALUE(4, 2), 225 SDMA_4_4 = SDMA_VERSION_VALUE(4, 4), 226 227 /* GFX10 */ 228 SDMA_5_0 = SDMA_VERSION_VALUE(5, 0), 229 230 /* GFX10.3 */ 231 SDMA_5_2 = SDMA_VERSION_VALUE(5, 2), 232 233 /* GFX11 */ 234 SDMA_6_0 = SDMA_VERSION_VALUE(6, 0), 235 236 /* GFX11.5 */ 237 SDMA_6_1 = SDMA_VERSION_VALUE(6, 1), 238 }; 239 240 const char *ac_get_family_name(enum radeon_family family); 241 enum amd_gfx_level ac_get_gfx_level(enum radeon_family family); 242 unsigned ac_get_family_id(enum radeon_family family); 243 const char *ac_get_llvm_processor_name(enum radeon_family family); 244 245 #ifdef __cplusplus 246 } 247 #endif 248 249 #endif 250