1#!/usr/bin/env python3 2 3import sys, io, re, json 4from canonicalize import json_canonicalize 5 6######### BEGIN HARDCODED CONFIGURATION 7 8gfx_levels = { 9 'gfx6': [ 10 [], 11 'asic_reg/gca/gfx_6_0_d.h', 12 'asic_reg/gca/gfx_6_0_sh_mask.h', 13 'asic_reg/gca/gfx_7_2_enum.h' # the file for gfx6 doesn't exist 14 ], 15 'gfx7': [ 16 [], 17 'asic_reg/gca/gfx_7_2_d.h', 18 'asic_reg/gca/gfx_7_2_sh_mask.h', 19 'asic_reg/gca/gfx_7_2_enum.h' 20 ], 21 'gfx8': [ 22 [], 23 'asic_reg/gca/gfx_8_0_d.h', 24 'asic_reg/gca/gfx_8_0_sh_mask.h', 25 'asic_reg/gca/gfx_8_0_enum.h', 26 ], 27 'gfx81': [ 28 [], 29 'asic_reg/gca/gfx_8_1_d.h', 30 'asic_reg/gca/gfx_8_1_sh_mask.h', 31 'asic_reg/gca/gfx_8_1_enum.h', 32 ], 33 'gfx9': [ 34 [0x00002000, 0x0000A000, 0, 0, 0], # IP_BASE GC_BASE 35 'asic_reg/gc/gc_9_2_1_offset.h', 36 'asic_reg/gc/gc_9_2_1_sh_mask.h', 37 'vega10_enum.h', 38 ], 39 'gfx940': [ 40 [0x00002000, 0x0000A000, 0, 0, 0], # IP_BASE GC_BASE 41 'asic_reg/gc/gc_9_4_3_offset.h', 42 'asic_reg/gc/gc_9_4_3_sh_mask.h', 43 'vega10_enum.h', 44 ], 45 'gfx10': [ 46 [0x00001260, 0x0000A000, 0x02402C00, 0, 0], # IP_BASE GC_BASE 47 'asic_reg/gc/gc_10_1_0_offset.h', 48 'asic_reg/gc/gc_10_1_0_sh_mask.h', 49 'navi10_enum.h', 50 ], 51 'gfx103': [ 52 [0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0], # IP_BASE GC_BASE 53 'asic_reg/gc/gc_10_3_0_offset.h', 54 'asic_reg/gc/gc_10_3_0_sh_mask.h', 55 'navi10_enum.h', # the file for gfx10.3 doesn't exist 56 ], 57 'gfx11': [ 58 [0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0], # IP_BASE GC_BASE 59 'asic_reg/gc/gc_11_0_0_offset.h', 60 'asic_reg/gc/gc_11_0_0_sh_mask.h', 61 'soc21_enum.h', 62 ], 63 'gfx115': [ 64 [0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0], # IP_BASE GC_BASE 65 'asic_reg/gc/gc_11_5_0_offset.h', 66 'asic_reg/gc/gc_11_5_0_sh_mask.h', 67 'soc21_enum.h', 68 ], 69} 70 71# match: #define mmSDMA0_DEC_START 0x0000 72# match: #define ixSDMA0_DEC_START 0x0000 73# match: #define regSDMA0_DEC_START 0x0000 74re_offset = re.compile(r'^#define (?P<mm>(mm|ix|reg))(?P<name>\w+)\s+(?P<value>\w+)\n') 75 76# match: #define SDMA0_DEC_START__START__SHIFT 0x0 77re_shift = re.compile(r'^#define (?P<name>\w+)__(?P<field>\w+)__SHIFT\s+(?P<value>\w+)\n') 78 79# match: #define SDMA0_DEC_START__START_MASK 0xFFFFFFFFL 80# match: #define SDMA0_DEC_START__START_MASK 0xFFFFFFFF 81re_mask = re.compile(r'^#define (?P<name>\w+)__(?P<field>\w+)_MASK\s+(?P<value>[0-9a-fA-Fx]+)L?\n') 82 83def register_filter(gfx_level, name, offset, already_added): 84 group = offset // 0x1000 85 is_cdna = gfx_level in ['gfx940'] 86 87 # Shader and uconfig registers 88 umd_ranges = [0xB, 0x30] 89 90 # Gfx context, other uconfig, and perf counter registers 91 if not is_cdna: 92 umd_ranges += [0x28, 0x31, 0x34, 0x35, 0x36, 0x37] 93 94 # Add all registers in the 0x8000 range for gfx6 95 if gfx_level == 'gfx6': 96 umd_ranges += [0x8] 97 98 # Only accept writeable registers and debug registers 99 return ((group in umd_ranges or 100 # Add SQ_WAVE registers for trap handlers 101 name.startswith('SQ_WAVE_') or 102 # Add registers in the 0x8000 range used by all generations 103 (group == 0x8 and 104 (name.startswith('SQ_IMG_') or 105 name.startswith('SQ_BUF_') or 106 name.startswith('SQ_THREAD') or 107 name.startswith('GRBM_STATUS') or 108 name.startswith('CP_CP'))) or 109 name.startswith('GCVM_L2_PROTECTION_FAULT_STATUS') or 110 # Add registers in the 0x9000 range 111 (group == 0x9 and 112 (name in ['TA_CS_BC_BASE_ADDR', 'GB_ADDR_CONFIG', 'SPI_CONFIG_CNTL'] or 113 (name.startswith('GB') and 'TILE_MODE' in name)))) and 114 # Remove SQ compiler definitions 115 offset // 4 not in (0x23B0, 0x23B1, 0x237F) and 116 # Remove conflicts (multiple definitions for the same offset) 117 not already_added and 118 'PREF_PRI_ACCUM' not in name and 119 # only define SPI and COMPUTE registers in the 0xB000 range. 120 (group != 0xB or name.startswith('SPI') or name.startswith('COMPUTE')) and 121 # only define CP_COHER uconfig registers on CDNA 122 (not is_cdna or group != 0x30 or name.startswith('CP_COHER'))) 123 124# Mapping from field names to enum types 125enum_map = { 126 # Format: 127 # field: [type1] - all registers use the same enum 128 # OR: 129 # field: [type1, reg1, type2, reg2, ...] - apply different enums to different registers 130 "ALPHA_COMB_FCN": ["CombFunc", "CB_BLEND0_CONTROL", "SX_OPT_COMB_FCN", "SX_MRT0_BLEND_OPT"], 131 "ALPHA_DESTBLEND": ["BlendOp"], 132 "ALPHA_DST_OPT": ["SX_BLEND_OPT"], 133 "ALPHA_SRCBLEND": ["BlendOp"], 134 "ALPHA_SRC_OPT": ["SX_BLEND_OPT"], 135 "ARRAY_MODE": ["ArrayMode"], 136 "BANK_HEIGHT": ["BankHeight"], 137 "BANK_WIDTH": ["BankWidth"], 138 "BC_SWIZZLE": ["SQ_IMG_RSRC_WORD4__BC_SWIZZLE"], 139 "BIN_MAPPING_MODE": ["BinMapMode"], 140 "BINNING_MODE": ["BinningMode"], 141 "BIN_SIZE_X_EXTEND": ["BinSizeExtend"], 142 "BIN_SIZE_Y_EXTEND": ["BinSizeExtend"], 143 "BLEND_OPT_DISCARD_PIXEL": ["BlendOpt"], 144 "BLEND_OPT_DONT_RD_DST": ["BlendOpt"], 145 "BORDER_COLOR_TYPE": ["SQ_TEX_BORDER_COLOR"], 146 "BUF_TYPE": ["VGT_DMA_BUF_TYPE"], 147 "CLAMP_X": ["SQ_TEX_CLAMP"], 148 "CLAMP_Y": ["SQ_TEX_CLAMP"], 149 "CLAMP_Z": ["SQ_TEX_CLAMP"], 150 "CLEAR_FILTER_SEL": ["CBPerfClearFilterSel"], 151 "CLIP_RULE": ["CLIP_RULE"], 152 "CMASK_ADDR_TYPE": ["CmaskAddr"], 153 "CMASK_RD_POLICY": ["ReadPolicy"], 154 "CMASK_WR_POLICY": ["WritePolicy"], 155 "COL0_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"], 156 "COL1_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"], 157 "COL2_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"], 158 "COL3_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"], 159 "COL4_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"], 160 "COL5_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"], 161 "COL6_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"], 162 "COL7_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"], 163 "COLOR_COMB_FCN": ["CombFunc", "CB_BLEND0_CONTROL", "SX_OPT_COMB_FCN", "SX_MRT0_BLEND_OPT"], 164 "COLOR_DESTBLEND": ["BlendOp"], 165 "COLOR_DST_OPT": ["SX_BLEND_OPT"], 166 "COLOR_RD_POLICY": ["ReadPolicy"], 167 "COLOR_SRCBLEND": ["BlendOp"], 168 "COLOR_SRC_OPT": ["SX_BLEND_OPT"], 169 "COLOR_WR_POLICY": ["WritePolicy"], 170 "COMPAREFUNC0": ["CompareFrag"], 171 "COMPAREFUNC1": ["CompareFrag"], 172 "COMP_SWAP": ["SurfaceSwap"], 173 "CONSERVATIVE_Z_EXPORT": ["ConservativeZExport"], 174 "COVERAGE_TO_SHADER_SELECT": ["CovToShaderSel"], 175 "CUT_MODE": ["VGT_GS_CUT_MODE"], 176 "DATA_FORMAT": ["BUF_DATA_FORMAT", "SQ_BUF_RSRC_WORD3", "IMG_DATA_FORMAT", "SQ_IMG_RSRC_WORD1"], 177 "DCC_RD_POLICY": ["ReadPolicy"], 178 "DCC_WR_POLICY": ["WritePolicy"], 179 "DEPTH_COMPARE_FUNC": ["SQ_TEX_DEPTH_COMPARE"], 180 "DETECT_ONE": ["VGT_DETECT_ONE"], 181 "DETECT_ZERO": ["VGT_DETECT_ZERO"], 182 "DISTRIBUTION_MODE": ["VGT_DIST_MODE"], 183 "DST_SEL_W": ["SQ_SEL_XYZW01"], 184 "DST_SEL_X": ["SQ_SEL_XYZW01"], 185 "DST_SEL_Y": ["SQ_SEL_XYZW01"], 186 "DST_SEL_Z": ["SQ_SEL_XYZW01"], 187 "ENDIAN": ["SurfaceEndian"], 188 "ES_EN": ["VGT_STAGES_ES_EN"], 189 "EVENT_TYPE": ["VGT_EVENT_TYPE"], 190 "EXCP": ["EXCP_EN"], 191 "EXCP_EN": ["EXCP_EN"], 192 "FAULT_BEHAVIOR": ["DbPRTFaultBehavior"], 193 "FILTER_MODE": ["SQ_IMG_FILTER_TYPE"], 194 "FLOAT_MODE": ["FLOAT_MODE"], 195 "FMASK_RD_POLICY": ["ReadPolicy"], 196 "FMASK_WR_POLICY": ["WritePolicy"], 197 "FORCE_FULL_Z_RANGE": ["ForceControl"], 198 "FORCE_HIS_ENABLE0": ["ForceControl"], 199 "FORCE_HIS_ENABLE1": ["ForceControl"], 200 "FORCE_HIZ_ENABLE": ["ForceControl"], 201 "FORCE_Z_LIMIT_SUMM": ["ZLimitSumm"], 202 "FORMAT": ["ColorFormat", "CB_COLOR0_INFO", "StencilFormat", "DB_STENCIL_INFO", "ZFormat", "DB_Z_INFO"], 203 "GS_EN": ["VGT_STAGES_GS_EN"], 204 "HIZ_ZFUNC": ["CompareFrag"], 205 "HS_EN": ["VGT_STAGES_HS_EN"], 206 "HTILE_RD_POLICY": ["ReadPolicy"], 207 "HTILE_WR_POLICY": ["WritePolicy"], 208 "IDX0_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"], 209 "INDEX_TYPE": ["VGT_INDEX_TYPE_MODE"], 210 "LS_EN": ["VGT_STAGES_LS_EN"], 211 "MACRO_TILE_ASPECT": ["MacroTileAspect"], 212 "MAJOR_MODE": ["VGT_DI_MAJOR_MODE_SELECT"], 213 "MAX_UNCOMPRESSED_BLOCK_SIZE": ["CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE"], 214 "MICRO_TILE_MODE": ["GB_TILE_MODE0__MICRO_TILE_MODE"], 215 "MICRO_TILE_MODE_NEW": ["MicroTileMode"], 216 "MIN_COMPRESSED_BLOCK_SIZE": ["CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE"], 217 "MIP_FILTER": ["SQ_TEX_MIP_FILTER"], 218 "MODE": ["CBMode", "CB_COLOR_CONTROL", "VGT_GS_MODE_TYPE", "VGT_GS_MODE"], 219 "MRT0_EPSILON": ["SX_BLEND_OPT_EPSILON__MRT0_EPSILON"], 220 "MRT0": ["SX_DOWNCONVERT_FORMAT"], 221 "MRT1": ["SX_DOWNCONVERT_FORMAT"], 222 "MRT2": ["SX_DOWNCONVERT_FORMAT"], 223 "MRT3": ["SX_DOWNCONVERT_FORMAT"], 224 "MRT4": ["SX_DOWNCONVERT_FORMAT"], 225 "MRT5": ["SX_DOWNCONVERT_FORMAT"], 226 "MRT6": ["SX_DOWNCONVERT_FORMAT"], 227 "MRT7": ["SX_DOWNCONVERT_FORMAT"], 228 "NUM_BANKS": ["NumBanks"], 229 "NUM_FORMAT": ["BUF_NUM_FORMAT", "SQ_BUF_RSRC_WORD3", "IMG_NUM_FORMAT", "SQ_IMG_RSRC_WORD1"], 230 "NUMBER_TYPE": ["SurfaceNumber"], 231 "OFFCHIP_GRANULARITY": ["VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY"], 232 "OP_FILTER_SEL": ["CBPerfOpFilterSel"], 233 "OREO_MODE": ["OreoMode"], 234 "OUTPRIM_TYPE_1": ["VGT_GS_OUTPRIM_TYPE"], 235 "OUTPRIM_TYPE_2": ["VGT_GS_OUTPRIM_TYPE"], 236 "OUTPRIM_TYPE_3": ["VGT_GS_OUTPRIM_TYPE"], 237 "OUTPRIM_TYPE": ["VGT_GS_OUTPRIM_TYPE"], 238 "PARTIAL_SQUAD_LAUNCH_CONTROL": ["DbPSLControl"], 239 "PARTITIONING": ["VGT_TESS_PARTITION"], 240 "PERFMON_ENABLE_MODE": ["CP_PERFMON_ENABLE_MODE"], 241 "PERFMON_STATE": ["CP_PERFMON_STATE"], 242 "PIPE_CONFIG": ["PipeConfig"], 243 "PKR_MAP": ["PkrMap"], 244 "PKR_XSEL2": ["PkrXsel2"], 245 "PKR_XSEL": ["PkrXsel"], 246 "PKR_YSEL": ["PkrYsel"], 247 "PNT_SPRITE_OVRD_W": ["SPI_PNT_SPRITE_OVERRIDE"], 248 "PNT_SPRITE_OVRD_X": ["SPI_PNT_SPRITE_OVERRIDE"], 249 "PNT_SPRITE_OVRD_Y": ["SPI_PNT_SPRITE_OVERRIDE"], 250 "PNT_SPRITE_OVRD_Z": ["SPI_PNT_SPRITE_OVERRIDE"], 251 "POLYMODE_BACK_PTYPE": ["PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE"], 252 "POLYMODE_FRONT_PTYPE": ["PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE"], 253 "POLY_MODE": ["PA_SU_SC_MODE_CNTL__POLY_MODE"], 254 "POS0_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"], 255 "POS1_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"], 256 "POS2_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"], 257 "POS3_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"], 258 "POS4_EXPORT_FORMAT": ["SPI_SHADER_FORMAT"], 259 "PRIM_TYPE": ["VGT_DI_PRIM_TYPE"], 260 "PUNCHOUT_MODE": ["DB_DFSM_CONTROL__PUNCHOUT_MODE"], 261 "QUANT_MODE": ["QUANT_MODE"], 262 "RB_MAP_PKR0": ["RbMap"], 263 "RB_MAP_PKR1": ["RbMap"], 264 "RB_XSEL2": ["RbXsel2"], 265 "RB_XSEL": ["RbXsel"], 266 "RB_YSEL": ["RbYsel"], 267 "ROP3": ["ROP3"], 268 "RDREQ_POLICY": ["VGT_RDREQ_POLICY"], 269 "REG_INCLUDE": ["ThreadTraceRegInclude"], 270 "ROUND_MODE": ["PA_SU_VTX_CNTL__ROUND_MODE", "PA_SU_VTX_CNTL"], 271 "SC_MAP": ["ScMap"], 272 "SC_XSEL": ["ScXsel"], 273 "SC_YSEL": ["ScYsel"], 274 "SE_MAP": ["SeMap"], 275 "SE_PAIR_MAP": ["SePairMap"], 276 "SE_PAIR_XSEL": ["SePairXsel"], 277 "SE_PAIR_YSEL": ["SePairYsel"], 278 "SE_XSEL": ["SeXsel"], 279 "SE_YSEL": ["SeYsel"], 280 "SOURCE_SELECT": ["VGT_DI_SOURCE_SELECT"], 281 "SPM_PERFMON_STATE": ["SPM_PERFMON_STATE"], 282 "S_RD_POLICY": ["ReadPolicy"], 283 "STENCILFAIL_BF": ["StencilOp"], 284 "STENCILFAIL": ["StencilOp"], 285 "STENCILFUNC_BF": ["CompareFrag"], 286 "STENCILFUNC": ["CompareFrag"], 287 "STENCILZFAIL_BF": ["StencilOp"], 288 "STENCILZFAIL": ["StencilOp"], 289 "STENCILZPASS_BF": ["StencilOp"], 290 "STENCILZPASS": ["StencilOp"], 291 "SWAP_MODE": ["VGT_DMA_SWAP_MODE"], 292 "S_WR_POLICY": ["WritePolicy"], 293 "TILE_SPLIT": ["TileSplit"], 294 "TOKEN_EXCLUDE": ["ThreadTraceTokenExclude"], 295 "TOPOLOGY": ["VGT_TESS_TOPOLOGY"], 296 "TYPE": ["SQ_RSRC_BUF_TYPE", "SQ_BUF_RSRC_WORD3", "SQ_RSRC_IMG_TYPE", "SQ_IMG_RSRC_WORD3", "VGT_TESS_TYPE", "VGT_TF_PARAM"], 297 "UNCERTAINTY_REGION_MODE": ["ScUncertaintyRegionMode"], 298 "VRS_HTILE_ENCODING": ["VRSHtileEncoding"], 299 "VRS_RATE": ["VRSrate"], 300 "VS_EN": ["VGT_STAGES_VS_EN"], 301 "XY_MAG_FILTER": ["SQ_TEX_XY_FILTER"], 302 "XY_MIN_FILTER": ["SQ_TEX_XY_FILTER"], 303 "Z_EXPORT_FORMAT": ["SPI_SHADER_EX_FORMAT"], 304 "Z_FILTER": ["SQ_TEX_Z_FILTER"], 305 "ZFUNC": ["CompareFrag"], 306 "Z_ORDER": ["ZOrder"], 307 "ZPCPSD_WR_POLICY": ["WritePolicy"], 308 "Z_RD_POLICY": ["ReadPolicy"], 309 "Z_WR_POLICY": ["WritePolicy"], 310 311 "VERTEX_RATE_COMBINER_MODE": ["VRSCombinerModeSC"], 312 "PRIMITIVE_RATE_COMBINER_MODE": ["VRSCombinerModeSC"], 313 "HTILE_RATE_COMBINER_MODE": ["VRSCombinerModeSC"], 314 "SAMPLE_ITER_COMBINER_MODE": ["VRSCombinerModeSC"], 315 "VRS_OVERRIDE_RATE_COMBINER_MODE": ["VRSCombinerModeSC"], 316} 317 318# Enum definitions that are incomplete or missing in kernel headers 319DB_DFSM_CONTROL__PUNCHOUT_MODE = { 320 "entries": [ 321 {"name": "AUTO", "value": 0}, 322 {"name": "FORCE_ON", "value": 1}, 323 {"name": "FORCE_OFF", "value": 2}, 324 {"name": "RESERVED", "value": 3} 325 ] 326} 327 328ColorFormat = { 329 "entries": [ 330 {"name": "COLOR_INVALID", "value": 0}, 331 {"name": "COLOR_8", "value": 1}, 332 {"name": "COLOR_16", "value": 2}, 333 {"name": "COLOR_8_8", "value": 3}, 334 {"name": "COLOR_32", "value": 4}, 335 {"name": "COLOR_16_16", "value": 5}, 336 {"name": "COLOR_10_11_11", "value": 6}, 337 {"name": "COLOR_11_11_10", "value": 7}, 338 {"name": "COLOR_10_10_10_2", "value": 8}, 339 {"name": "COLOR_2_10_10_10", "value": 9}, 340 {"name": "COLOR_8_8_8_8", "value": 10}, 341 {"name": "COLOR_32_32", "value": 11}, 342 {"name": "COLOR_16_16_16_16", "value": 12}, 343 {"name": "COLOR_32_32_32_32", "value": 14}, 344 {"name": "COLOR_5_6_5", "value": 16}, 345 {"name": "COLOR_1_5_5_5", "value": 17}, 346 {"name": "COLOR_5_5_5_1", "value": 18}, 347 {"name": "COLOR_4_4_4_4", "value": 19}, 348 {"name": "COLOR_8_24", "value": 20}, 349 {"name": "COLOR_24_8", "value": 21}, 350 {"name": "COLOR_X24_8_32_FLOAT", "value": 22}, 351 {"name": "COLOR_5_9_9_9", "value": 24} 352 ] 353} 354 355SQ_IMG_RSRC_WORD4__BC_SWIZZLE = { 356 "entries": [ 357 {"name": "BC_SWIZZLE_XYZW", "value": 0}, 358 {"name": "BC_SWIZZLE_XWYZ", "value": 1}, 359 {"name": "BC_SWIZZLE_WZYX", "value": 2}, 360 {"name": "BC_SWIZZLE_WXYZ", "value": 3}, 361 {"name": "BC_SWIZZLE_ZYXW", "value": 4}, 362 {"name": "BC_SWIZZLE_YXWZ", "value": 5} 363 ] 364} 365 366SX_DOWNCONVERT_FORMAT = { 367 "entries": [ 368 {"name": "SX_RT_EXPORT_NO_CONVERSION", "value": 0}, 369 {"name": "SX_RT_EXPORT_32_R", "value": 1}, 370 {"name": "SX_RT_EXPORT_32_A", "value": 2}, 371 {"name": "SX_RT_EXPORT_10_11_11", "value": 3}, 372 {"name": "SX_RT_EXPORT_2_10_10_10", "value": 4}, 373 {"name": "SX_RT_EXPORT_8_8_8_8", "value": 5}, 374 {"name": "SX_RT_EXPORT_5_6_5", "value": 6}, 375 {"name": "SX_RT_EXPORT_1_5_5_5", "value": 7}, 376 {"name": "SX_RT_EXPORT_4_4_4_4", "value": 8}, 377 {"name": "SX_RT_EXPORT_16_16_GR", "value": 9}, 378 {"name": "SX_RT_EXPORT_16_16_AR", "value": 10}, 379 {"name": "SX_RT_EXPORT_9_9_9_E5", "value": 11} 380 ] 381} 382 383ThreadTraceRegInclude = { 384 "entries": [ 385 {"name": "REG_INCLUDE_SQDEC", "value": 1}, 386 {"name": "REG_INCLUDE_SHDEC", "value": 2}, 387 {"name": "REG_INCLUDE_GFXUDEC", "value": 4}, 388 {"name": "REG_INCLUDE_COMP", "value": 8}, 389 {"name": "REG_INCLUDE_CONTEXT", "value": 16}, 390 {"name": "REG_INCLUDE_CONFIG", "value": 32}, 391 {"name": "REG_INCLUDE_OTHER", "value": 64}, 392 {"name": "REG_INCLUDE_READS", "value": 128} 393 ] 394} 395 396ThreadTraceTokenExclude = { 397 "entries": [ 398 {"name": "TOKEN_EXCLUDE_VMEMEXEC", "value": 1}, 399 {"name": "TOKEN_EXCLUDE_ALUEXEC", "value": 2}, 400 {"name": "TOKEN_EXCLUDE_VALUINST", "value": 4}, 401 {"name": "TOKEN_EXCLUDE_WAVERDY", "value": 8}, 402 {"name": "TOKEN_EXCLUDE_IMMED1", "value": 16}, 403 {"name": "TOKEN_EXCLUDE_IMMEDIATE", "value": 32}, 404 {"name": "TOKEN_EXCLUDE_REG", "value": 64}, 405 {"name": "TOKEN_EXCLUDE_EVENT", "value": 128}, 406 {"name": "TOKEN_EXCLUDE_INST", "value": 256}, 407 {"name": "TOKEN_EXCLUDE_UTILCTR", "value": 512}, 408 {"name": "TOKEN_EXCLUDE_WAVEALLOC", "value": 1024}, 409 {"name": "TOKEN_EXCLUDE_PERF", "value": 2048} 410 ] 411} 412 413GB_TILE_MODE0__MICRO_TILE_MODE = { 414 "entries": [ 415 {"name": "ADDR_SURF_DISPLAY_MICRO_TILING", "value": 0}, 416 {"name": "ADDR_SURF_THIN_MICRO_TILING", "value": 1}, 417 {"name": "ADDR_SURF_DEPTH_MICRO_TILING", "value": 2}, 418 {"name": "ADDR_SURF_THICK_MICRO_TILING_GFX6", "value": 3} 419 ] 420} 421 422IMG_DATA_FORMAT_STENCIL = { 423 "entries": [ 424 {"name": "IMG_DATA_FORMAT_S8_16", "value": 59}, 425 {"name": "IMG_DATA_FORMAT_S8_32", "value": 60}, 426 ] 427} 428 429VRSCombinerModeSC = { 430 "entries": [ 431 {"name": "SC_VRS_COMB_MODE_PASSTHRU", "value": 0}, 432 {"name": "SC_VRS_COMB_MODE_OVERRIDE", "value": 1}, 433 {"name": "SC_VRS_COMB_MODE_MIN", "value": 2}, 434 {"name": "SC_VRS_COMB_MODE_MAX", "value": 3}, 435 {"name": "SC_VRS_COMB_MODE_SATURATE", "value": 4}, 436 ] 437} 438 439VRSHtileEncoding = { 440 "entries": [ 441 {"name": "VRS_HTILE_DISABLE", "value": 0}, 442 {"name": "VRS_HTILE_2BIT_ENCODING", "value": 1}, 443 {"name": "VRS_HTILE_4BIT_ENCODING", "value": 2}, 444 ] 445} 446 447missing_enums_all = { 448 'FLOAT_MODE': { 449 "entries": [ 450 {"name": "FP_32_ROUND_TOWARDS_ZERO", "value": 3}, 451 {"name": "FP_16_64_ROUND_TOWARDS_ZERO", "value": 12}, 452 {"name": "FP_32_DENORMS", "value": 48}, 453 {"name": "FP_16_64_DENORMS", "value": 192}, 454 ] 455 }, 456 'QUANT_MODE': { 457 "entries": [ 458 {"name": "X_16_8_FIXED_POINT_1_16TH", "value": 0}, 459 {"name": "X_16_8_FIXED_POINT_1_8TH", "value": 1}, 460 {"name": "X_16_8_FIXED_POINT_1_4TH", "value": 2}, 461 {"name": "X_16_8_FIXED_POINT_1_2", "value": 3}, 462 {"name": "X_16_8_FIXED_POINT_1", "value": 4}, 463 {"name": "X_16_8_FIXED_POINT_1_256TH", "value": 5}, 464 {"name": "X_14_10_FIXED_POINT_1_1024TH", "value": 6}, 465 {"name": "X_12_12_FIXED_POINT_1_4096TH", "value": 7} 466 ] 467 }, 468 "CLIP_RULE": { 469 "entries": [ 470 {"name": "OUT", "value": 1}, 471 {"name": "IN_0", "value": 2}, 472 {"name": "IN_1", "value": 4}, 473 {"name": "IN_10", "value": 8}, 474 {"name": "IN_2", "value": 16}, 475 {"name": "IN_20", "value": 32}, 476 {"name": "IN_21", "value": 64}, 477 {"name": "IN_210", "value": 128}, 478 {"name": "IN_3", "value": 256}, 479 {"name": "IN_30", "value": 512}, 480 {"name": "IN_31", "value": 1024}, 481 {"name": "IN_310", "value": 2048}, 482 {"name": "IN_32", "value": 4096}, 483 {"name": "IN_320", "value": 8192}, 484 {"name": "IN_321", "value": 16384}, 485 {"name": "IN_3210", "value": 32768} 486 ] 487 }, 488 'PA_SU_VTX_CNTL__ROUND_MODE': { 489 "entries": [ 490 {"name": "X_TRUNCATE", "value": 0}, 491 {"name": "X_ROUND", "value": 1}, 492 {"name": "X_ROUND_TO_EVEN", "value": 2}, 493 {"name": "X_ROUND_TO_ODD", "value": 3} 494 ] 495 }, 496 "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE": { 497 "entries": [ 498 {"name": "X_DRAW_POINTS", "value": 0}, 499 {"name": "X_DRAW_LINES", "value": 1}, 500 {"name": "X_DRAW_TRIANGLES", "value": 2} 501 ] 502 }, 503 "PA_SU_SC_MODE_CNTL__POLY_MODE": { 504 "entries": [ 505 {"name": "X_DISABLE_POLY_MODE", "value": 0}, 506 {"name": "X_DUAL_MODE", "value": 1} 507 ] 508 }, 509 'VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY': { 510 "entries": [ 511 {"name": "X_8K_DWORDS", "value": 0}, 512 {"name": "X_4K_DWORDS", "value": 1}, 513 {"name": "X_2K_DWORDS", "value": 2}, 514 {"name": "X_1K_DWORDS", "value": 3} 515 ] 516 }, 517 "ROP3": { 518 "entries": [ 519 {"name": "ROP3_CLEAR", "value": 0}, 520 {"name": "X_0X05", "value": 5}, 521 {"name": "X_0X0A", "value": 10}, 522 {"name": "X_0X0F", "value": 15}, 523 {"name": "ROP3_NOR", "value": 17}, 524 {"name": "ROP3_AND_INVERTED", "value": 34}, 525 {"name": "ROP3_COPY_INVERTED", "value": 51}, 526 {"name": "ROP3_AND_REVERSE", "value": 68}, 527 {"name": "X_0X50", "value": 80}, 528 {"name": "ROP3_INVERT", "value": 85}, 529 {"name": "X_0X5A", "value": 90}, 530 {"name": "X_0X5F", "value": 95}, 531 {"name": "ROP3_XOR", "value": 102}, 532 {"name": "ROP3_NAND", "value": 119}, 533 {"name": "ROP3_AND", "value": 136}, 534 {"name": "ROP3_EQUIVALENT", "value": 153}, 535 {"name": "X_0XA0", "value": 160}, 536 {"name": "X_0XA5", "value": 165}, 537 {"name": "ROP3_NO_OP", "value": 170}, 538 {"name": "X_0XAF", "value": 175}, 539 {"name": "ROP3_OR_INVERTED", "value": 187}, 540 {"name": "ROP3_COPY", "value": 204}, 541 {"name": "ROP3_OR_REVERSE", "value": 221}, 542 {"name": "ROP3_OR", "value": 238}, 543 {"name": "X_0XF0", "value": 240}, 544 {"name": "X_0XF5", "value": 245}, 545 {"name": "X_0XFA", "value": 250}, 546 {"name": "ROP3_SET", "value": 255} 547 ] 548 }, 549 "EXCP_EN": { 550 "entries": [ 551 {"name": "INVALID", "value": 1}, 552 {"name": "INPUT_DENORMAL", "value": 2}, 553 {"name": "DIVIDE_BY_ZERO", "value": 4}, 554 {"name": "OVERFLOW", "value": 8}, 555 {"name": "UNDERFLOW", "value": 16}, 556 {"name": "INEXACT", "value": 32}, 557 {"name": "INT_DIVIDE_BY_ZERO", "value": 64}, 558 {"name": "ADDRESS_WATCH", "value": 128}, 559 {"name": "MEMORY_VIOLATION", "value": 256} 560 ] 561 } 562} 563 564missing_enums_gfx8plus = { 565 **missing_enums_all, 566 'CB_COLOR_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE': { 567 "entries": [ 568 {"name": "MAX_BLOCK_SIZE_64B", "value": 0}, 569 {"name": "MAX_BLOCK_SIZE_128B", "value": 1}, 570 {"name": "MAX_BLOCK_SIZE_256B", "value": 2} 571 ] 572 }, 573 'CB_COLOR_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE': { 574 "entries": [ 575 {"name": "MIN_BLOCK_SIZE_32B", "value": 0}, 576 {"name": "MIN_BLOCK_SIZE_64B", "value": 1} 577 ] 578 }, 579} 580 581missing_enums_gfx81plus = { 582 **missing_enums_gfx8plus, 583 "SX_BLEND_OPT_EPSILON__MRT0_EPSILON": { 584 "entries": [ 585 {"name": "EXACT", "value": 0}, 586 # This determines whether epsilon is 0.5 or 0.75 in the unnormalized format 587 # that is used to determine whether a channel is equal to 0 for blending. 588 # 0.5 is exactly between 0 and the next representable value. 0.75 can be 589 # used for less precise blending. 590 {"name": "10BIT_FORMAT_0_5", "value": 2}, # (1.0 * 2^−11) * 1024 = 0.5 591 {"name": "10BIT_FORMAT_0_75", "value": 3}, # (1.5 * 2^−11) * 1024 = 0.75 592 {"name": "8BIT_FORMAT_0_5", "value": 6}, # (1.0 * 2^−9) * 256 = 0.5 593 {"name": "8BIT_FORMAT_0_75", "value": 7}, # (1.5 * 2^−9) * 256 = 0.75 594 {"name": "6BIT_FORMAT_0_5", "value": 10}, # (1.0 * 2^-7) * 64 = 0.5 595 {"name": "6BIT_FORMAT_0_75", "value": 11}, # (1.5 * 2^-7) * 64 = 0.75 596 {"name": "5BIT_FORMAT_0_5", "value": 12}, # (1.0 * 2^-6) * 32 = 0.5 597 {"name": "5BIT_FORMAT_0_75", "value": 13}, # (1.5 * 2^-6) * 32 = 0.75 598 {"name": "4BIT_FORMAT_0_5", "value": 14}, # (1.0 * 2^-5) * 16 = 0.5 599 {"name": "4BIT_FORMAT_0_75", "value": 15}, # (1.5 * 2^-5) * 16 = 0.75 600 ] 601 }, 602} 603 604missing_enums_gfx9 = { 605 **missing_enums_gfx81plus, 606 "DB_DFSM_CONTROL__PUNCHOUT_MODE": DB_DFSM_CONTROL__PUNCHOUT_MODE, 607 "IMG_DATA_FORMAT_STENCIL": IMG_DATA_FORMAT_STENCIL, 608 "SQ_IMG_RSRC_WORD4__BC_SWIZZLE": SQ_IMG_RSRC_WORD4__BC_SWIZZLE, 609 "BinSizeExtend": { 610 "entries": [ 611 {"name": "BIN_SIZE_32_PIXELS", "value": 0}, 612 {"name": "BIN_SIZE_64_PIXELS", "value": 1}, 613 {"name": "BIN_SIZE_128_PIXELS", "value": 2}, 614 {"name": "BIN_SIZE_256_PIXELS", "value": 3}, 615 {"name": "BIN_SIZE_512_PIXELS", "value": 4} 616 ] 617 }, 618 "ScUncertaintyRegionMode": { 619 "entries": [ 620 {"name": "SC_HALF_LSB", "value": 0}, 621 {"name": "SC_LSB_ONE_SIDED", "value": 1}, 622 {"name": "SC_LSB_TWO_SIDED", "value": 2} 623 ] 624 }, 625} 626 627missing_enums_gfx103plus = { 628 **missing_enums_gfx81plus, 629 "ColorFormat": ColorFormat, 630 "ThreadTraceRegInclude": ThreadTraceRegInclude, 631 "ThreadTraceTokenExclude": ThreadTraceTokenExclude, 632} 633 634missing_enums_gfx11plus = { 635 **missing_enums_gfx103plus, 636 "ZFormat": { 637 "entries": [ 638 {"name": "Z_INVALID", "value": 0}, 639 {"name": "Z_16", "value": 1}, 640 {"name": "Z_24", "value": 2}, 641 {"name": "Z_32_FLOAT", "value": 3} 642 ] 643 }, 644 "StencilFormat": { 645 "entries": [ 646 {"name": "STENCIL_INVALID", "value": 0}, 647 {"name": "STENCIL_8", "value": 1} 648 ] 649 }, 650 "SurfaceNumber": { 651 "entries": [ 652 {"name": "NUMBER_UNORM", "value": 0}, 653 {"name": "NUMBER_SNORM", "value": 1}, 654 {"name": "NUMBER_USCALED", "value": 2}, 655 {"name": "NUMBER_SSCALED", "value": 3}, 656 {"name": "NUMBER_UINT", "value": 4}, 657 {"name": "NUMBER_SINT", "value": 5}, 658 {"name": "NUMBER_SRGB", "value": 6}, 659 {"name": "NUMBER_FLOAT", "value": 7} 660 ] 661 }, 662 "SurfaceSwap": { 663 "entries": [ 664 {"name": "SWAP_STD", "value": 0}, 665 {"name": "SWAP_ALT", "value": 1}, 666 {"name": "SWAP_STD_REV", "value": 2}, 667 {"name": "SWAP_ALT_REV", "value": 3} 668 ] 669 }, 670} 671 672enums_missing = { 673 'gfx6': { 674 **missing_enums_all, 675 "GB_TILE_MODE0__MICRO_TILE_MODE": GB_TILE_MODE0__MICRO_TILE_MODE, 676 }, 677 'gfx7': { 678 **missing_enums_all, 679 }, 680 'gfx8': { 681 **missing_enums_gfx8plus, 682 }, 683 'gfx81': { 684 **missing_enums_gfx81plus, 685 }, 686 'gfx9': { 687 **missing_enums_gfx9, 688 }, 689 'gfx940': { 690 **missing_enums_gfx9, 691 }, 692 'gfx10': { 693 **missing_enums_gfx81plus, 694 "DB_DFSM_CONTROL__PUNCHOUT_MODE": DB_DFSM_CONTROL__PUNCHOUT_MODE, 695 "ThreadTraceRegInclude": ThreadTraceRegInclude, 696 "ThreadTraceTokenExclude": ThreadTraceTokenExclude, 697 }, 698 'gfx103': { 699 **missing_enums_gfx103plus, 700 "SX_DOWNCONVERT_FORMAT": SX_DOWNCONVERT_FORMAT, 701 "DB_DFSM_CONTROL__PUNCHOUT_MODE": DB_DFSM_CONTROL__PUNCHOUT_MODE, 702 "VRSHtileEncoding": VRSHtileEncoding, 703 "VRSCombinerModeSC": VRSCombinerModeSC, 704 }, 705 'gfx11': { 706 **missing_enums_gfx11plus, 707 }, 708 'gfx115': { 709 **missing_enums_gfx11plus, 710 }, 711} 712 713# Register field definitions that are missing in kernel headers 714fields_missing = { 715 # Format: 716 # Register: [[Field, StartBit, EndBit, EnumType(optional), ReplaceField=True/False(optional)], ...] 717 'gfx6': { 718 "COMPUTE_RESOURCE_LIMITS": [["WAVES_PER_SH_GFX6", 0, 5]], 719 "GB_TILE_MODE0": [["MICRO_TILE_MODE", 0, 1, "GB_TILE_MODE0__MICRO_TILE_MODE"]], 720 "SQ_IMG_SAMP_WORD3": [["UPGRADED_DEPTH", 29, 29]], 721 "SQ_THREAD_TRACE_MASK": [["RANDOM_SEED", 16, 31]], 722 }, 723 'gfx7': { 724 "SQ_IMG_SAMP_WORD3": [["UPGRADED_DEPTH", 29, 29]], 725 "SQ_THREAD_TRACE_MASK": [["RANDOM_SEED", 16, 31]], 726 }, 727 'gfx8': { 728 "SQ_IMG_SAMP_WORD3": [["UPGRADED_DEPTH", 29, 29]], 729 "SQ_THREAD_TRACE_MASK": [["RANDOM_SEED", 16, 31]], 730 }, 731 'gfx81': { 732 "SQ_IMG_SAMP_WORD3": [["UPGRADED_DEPTH", 29, 29]], 733 "SQ_THREAD_TRACE_MASK": [["RANDOM_SEED", 16, 31]], 734 }, 735 'gfx9': { 736 "SQ_IMG_RSRC_WORD1": [ 737 ["DATA_FORMAT_STENCIL", 20, 25, "IMG_DATA_FORMAT_STENCIL"], 738 ["NUM_FORMAT_FMASK", 26, 29, "IMG_NUM_FORMAT_FMASK"] 739 ], 740 }, 741 'gfx10': { 742 "DB_RESERVED_REG_2": [["RESOURCE_LEVEL", 28, 31, None, True]], 743 }, 744 'gfx103': { 745 "DB_RESERVED_REG_2": [["RESOURCE_LEVEL", 28, 31, None, True]], 746 "VGT_DRAW_PAYLOAD_CNTL": [["EN_VRS_RATE", 6, 6]], 747 "VGT_SHADER_STAGES_EN": [["PRIMGEN_PASSTHRU_NO_MSG", 26, 26]], 748 }, 749 'gfx11': { 750 "VGT_DRAW_PAYLOAD_CNTL": [["EN_VRS_RATE", 6, 6]], 751 # Only GFX1103_R2: 752 "CB_COLOR0_FDCC_CONTROL": [["DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25], 753 ["ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26], 754 ["MAX_COMP_FRAGS", 27, 29]], 755 "CB_COLOR1_FDCC_CONTROL": [["DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25], 756 ["ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26], 757 ["MAX_COMP_FRAGS", 27, 29]], 758 "CB_COLOR2_FDCC_CONTROL": [["DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25], 759 ["ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26], 760 ["MAX_COMP_FRAGS", 27, 29]], 761 "CB_COLOR3_FDCC_CONTROL": [["DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25], 762 ["ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26], 763 ["MAX_COMP_FRAGS", 27, 29]], 764 "CB_COLOR4_FDCC_CONTROL": [["DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25], 765 ["ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26], 766 ["MAX_COMP_FRAGS", 27, 29]], 767 "CB_COLOR5_FDCC_CONTROL": [["DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25], 768 ["ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26], 769 ["MAX_COMP_FRAGS", 27, 29]], 770 "CB_COLOR6_FDCC_CONTROL": [["DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25], 771 ["ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26], 772 ["MAX_COMP_FRAGS", 27, 29]], 773 "CB_COLOR7_FDCC_CONTROL": [["DISABLE_OVERRIDE_INCONSISTENT_KEYS", 25, 25], 774 ["ENABLE_MAX_COMP_FRAG_OVERRIDE", 26, 26], 775 ["MAX_COMP_FRAGS", 27, 29]], 776 }, 777} 778 779######### END HARDCODED CONFIGURATION 780 781def bitcount(n): 782 return bin(n).count('1') 783 784def generate_json(gfx_level, amd_headers_path): 785 gc_base_offsets = gfx_levels[gfx_level][0] 786 787 # Add the path to the filenames 788 filenames = [amd_headers_path + '/' + a for a in gfx_levels[gfx_level][1:]] 789 790 # Open the files 791 files = [open(a, 'r').readlines() if a is not None else None for a in filenames] 792 793 # Parse the offset.h file 794 name = None 795 offset = None 796 added_offsets = set() 797 regs = {} 798 for line in files[0]: 799 r = re_offset.match(line) 800 if r is None: 801 continue 802 803 if '_BASE_IDX' not in r.group('name'): 804 name = r.group('name') 805 offset = int(r.group('value'), 0) * 4 806 if len(gc_base_offsets) > 0 and r.group('mm') == 'mm': 807 continue 808 else: 809 if name != r.group('name')[:-9]: 810 print('Warning: "{0}" not preceded by {1} but by {2}'.format(r.group('name'), r.group('name')[:-9], name)) 811 continue 812 idx = int(r.group('value')) 813 assert idx < len(gc_base_offsets) 814 offset += gc_base_offsets[idx] * 4 815 816 # Remove the _UMD suffix because it was mistakenly added to indicate it's for a User-Mode Driver 817 if name[-4:] == '_UMD': 818 name = name[:-4] 819 820 # Only accept writeable registers and debug registers 821 if register_filter(gfx_level, name, offset, offset in added_offsets): 822 regs[name] = { 823 'chips': [gfx_level], 824 'map': {'at': offset, 'to': 'mm'}, 825 'name': name, 826 } 827 added_offsets.add(offset) 828 829 830 # Parse the sh_mask.h file 831 shifts = {} 832 masks = {} 833 for line in files[1]: 834 r = re_shift.match(line) 835 is_shift = r is not None 836 r = re_mask.match(line) if r is None else r 837 if r is None: 838 continue 839 840 name = r.group('name') 841 if name not in regs.keys(): 842 continue 843 844 field = r.group('field') 845 value = int(r.group('value'), 0) 846 assert not is_shift or value < 32 847 848 d = shifts if is_shift else masks 849 if name not in d: 850 d[name] = {} 851 d[name][field] = value 852 853 854 # Parse the enum.h file 855 re_enum_begin = re.compile(r'^typedef enum (?P<name>\w+) {\n') 856 re_enum_entry = re.compile(r'\s*(?P<name>\w+)\s*=\s*(?P<value>\w+),?\n') 857 re_enum_end = re.compile(r'^} \w+;\n') 858 inside_enum = False 859 name = None 860 enums = enums_missing[gfx_level] if gfx_level in enums_missing else {} 861 862 for line in files[2]: 863 r = re_enum_begin.match(line) 864 if r is not None: 865 name = r.group('name') 866 if name in enums: 867 continue 868 enums[name] = {'entries': []} 869 inside_enum = True 870 continue 871 872 r = re_enum_end.match(line) 873 if r is not None: 874 inside_enum = False 875 name = None 876 continue 877 878 if inside_enum: 879 r = re_enum_entry.match(line) 880 assert r 881 enums[name]['entries'].append({ 882 'name': r.group('name'), 883 'value': int(r.group('value'), 0), 884 }) 885 886 887 # Assemble everything 888 reg_types = {} 889 reg_mappings = [] 890 missing_fields = fields_missing[gfx_level] if gfx_level in fields_missing else {} 891 892 for (name, reg) in regs.items(): 893 type = {'fields': []} 894 895 if name in shifts and name in masks: 896 for (field, shift) in shifts[name].items(): 897 if field not in masks[name]: 898 continue 899 900 new = { 901 'bits': [shift, shift + bitcount(masks[name][field]) - 1], 902 'name': field, 903 } 904 if field in enum_map: 905 type_map = enum_map[field] 906 type_name = None 907 908 if len(type_map) == 1: 909 type_name = type_map[0]; 910 else: 911 reg_index = type_map.index(name) if name in type_map else -1 912 if reg_index >= 1 and reg_index % 2 == 1: 913 type_name = type_map[reg_index - 1] 914 915 if type_name is not None: 916 if type_name not in enums: 917 print('{0}: {1} type not found for {2}.{3}' 918 .format(gfx_level, type_name, name, field), file=sys.stderr) 919 else: 920 new['enum_ref'] = type_name 921 922 type['fields'].append(new) 923 924 if name in missing_fields: 925 fields = missing_fields[name] 926 for f in fields: 927 field = { 928 'bits': [f[1], f[2]], 929 'name': f[0], 930 } 931 if len(f) >= 4 and f[3] is not None and f[3] in enums: 932 field['enum_ref'] = f[3] 933 # missing_fields should replace overlapping fields if requested 934 if len(f) >= 5 and f[4]: 935 for f2 in type['fields']: 936 if f2['bits'] == field['bits']: 937 type['fields'].remove(f2) 938 939 type['fields'].append(field) 940 941 if len(type['fields']) > 0: 942 reg_types[name] = type 943 944 # Don't define types that have only one field covering all bits 945 field0_bits = type['fields'][0]['bits']; 946 if len(type['fields']) > 1 or field0_bits[0] != 0 or field0_bits[1] != 31: 947 reg['type_ref'] = name 948 949 reg_mappings.append(reg) 950 951 952 # Generate and canonicalize json 953 all = { 954 'enums': enums, 955 'register_mappings': reg_mappings, 956 'register_types': reg_types, 957 } 958 959 return json_canonicalize(io.StringIO(json.dumps(all, indent=1))) 960 961 962if __name__ == '__main__': 963 if len(sys.argv) <= 1 or (sys.argv[1] not in gfx_levels and sys.argv[1] != 'all'): 964 print('First parameter should be one of: all, ' + ', '.join(gfx_levels.keys()), file=sys.stderr) 965 sys.exit(1) 966 967 if len(sys.argv) <= 2: 968 print('Second parameter should be the path to the amd/include directory.', file=sys.stderr) 969 sys.exit(1) 970 971 if sys.argv[1] == 'all': 972 for gfx_level in gfx_levels.keys(): 973 print(generate_json(gfx_level, sys.argv[2]), file=open(gfx_level + '.json', 'w')) 974 sys.exit(0) 975 976 print(generate_json(sys.argv[1], sys.argv[2])) 977