1 /*
2 * Copyright © 2021 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #define AC_SURFACE_INCLUDE_NIR
25 #include "ac_surface.h"
26
27 #include "radv_meta.h"
28 #include "radv_private.h"
29 #include "vk_common_entrypoints.h"
30 #include "vk_format.h"
31
32 void
radv_device_finish_meta_copy_vrs_htile_state(struct radv_device * device)33 radv_device_finish_meta_copy_vrs_htile_state(struct radv_device *device)
34 {
35 struct radv_meta_state *state = &device->meta_state;
36
37 radv_DestroyPipeline(radv_device_to_handle(device), state->copy_vrs_htile_pipeline, &state->alloc);
38 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->copy_vrs_htile_p_layout, &state->alloc);
39 device->vk.dispatch_table.DestroyDescriptorSetLayout(radv_device_to_handle(device), state->copy_vrs_htile_ds_layout,
40 &state->alloc);
41 }
42
43 static nir_shader *
build_copy_vrs_htile_shader(struct radv_device * device,struct radeon_surf * surf)44 build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf)
45 {
46 nir_builder b = radv_meta_init_shader(device, MESA_SHADER_COMPUTE, "meta_copy_vrs_htile");
47 b.shader->info.workgroup_size[0] = 8;
48 b.shader->info.workgroup_size[1] = 8;
49
50 /* Get coordinates. */
51 nir_def *global_id = get_global_ids(&b, 2);
52
53 nir_def *offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8);
54
55 /* Multiply the coordinates by the HTILE block size. */
56 nir_def *coord = nir_iadd(&b, nir_imul_imm(&b, global_id, 8), offset);
57
58 /* Load constants. */
59 nir_def *constants = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 8), .range = 20);
60 nir_def *htile_pitch = nir_channel(&b, constants, 0);
61 nir_def *htile_slice_size = nir_channel(&b, constants, 1);
62 nir_def *read_htile_value = nir_channel(&b, constants, 2);
63
64 /* Get the HTILE addr from coordinates. */
65 nir_def *zero = nir_imm_int(&b, 0);
66 nir_def *htile_addr =
67 ac_nir_htile_addr_from_coord(&b, &device->physical_device->rad_info, &surf->u.gfx9.zs.htile_equation, htile_pitch,
68 htile_slice_size, nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), zero, zero);
69
70 /* Set up the input VRS image descriptor. */
71 const struct glsl_type *vrs_sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_FLOAT);
72 nir_variable *input_vrs_img = nir_variable_create(b.shader, nir_var_uniform, vrs_sampler_type, "input_vrs_image");
73 input_vrs_img->data.descriptor_set = 0;
74 input_vrs_img->data.binding = 0;
75
76 /* Load the VRS rates from the 2D image. */
77 nir_def *value = nir_txf_deref(&b, nir_build_deref_var(&b, input_vrs_img), global_id, NULL);
78
79 /* Extract the X/Y rates and clamp them because the maximum supported VRS rate is 2x2 (1x1 in
80 * hardware).
81 *
82 * VRS rate X = min(value >> 2, 1)
83 * VRS rate Y = min(value & 3, 1)
84 */
85 nir_def *x_rate = nir_ushr_imm(&b, nir_channel(&b, value, 0), 2);
86 x_rate = nir_umin(&b, x_rate, nir_imm_int(&b, 1));
87
88 nir_def *y_rate = nir_iand_imm(&b, nir_channel(&b, value, 0), 3);
89 y_rate = nir_umin(&b, y_rate, nir_imm_int(&b, 1));
90
91 /* Compute the final VRS rate. */
92 nir_def *vrs_rates = nir_ior(&b, nir_ishl_imm(&b, y_rate, 10), nir_ishl_imm(&b, x_rate, 6));
93
94 /* Load the HTILE buffer descriptor. */
95 nir_def *htile_buf = radv_meta_load_descriptor(&b, 0, 1);
96
97 /* Load the HTILE value if requested, otherwise use the default value. */
98 nir_variable *htile_value = nir_local_variable_create(b.impl, glsl_int_type(), "htile_value");
99
100 nir_push_if(&b, nir_ieq_imm(&b, read_htile_value, 1));
101 {
102 /* Load the existing HTILE 32-bit value for this 8x8 pixels area. */
103 nir_def *input_value = nir_load_ssbo(&b, 1, 32, htile_buf, htile_addr);
104
105 /* Clear the 4-bit VRS rates. */
106 nir_store_var(&b, htile_value, nir_iand_imm(&b, input_value, 0xfffff33f), 0x1);
107 }
108 nir_push_else(&b, NULL);
109 {
110 nir_store_var(&b, htile_value, nir_imm_int(&b, 0xfffff33f), 0x1);
111 }
112 nir_pop_if(&b, NULL);
113
114 /* Set the VRS rates loaded from the image. */
115 nir_def *output_value = nir_ior(&b, nir_load_var(&b, htile_value), vrs_rates);
116
117 /* Store the updated HTILE 32-bit which contains the VRS rates. */
118 nir_store_ssbo(&b, output_value, htile_buf, htile_addr, .access = ACCESS_NON_READABLE);
119
120 return b.shader;
121 }
122
123 static VkResult
radv_device_init_meta_copy_vrs_htile_state(struct radv_device * device,struct radeon_surf * surf)124 radv_device_init_meta_copy_vrs_htile_state(struct radv_device *device, struct radeon_surf *surf)
125 {
126 struct radv_meta_state *state = &device->meta_state;
127 nir_shader *cs = build_copy_vrs_htile_shader(device, surf);
128 VkResult result;
129
130 VkDescriptorSetLayoutCreateInfo ds_layout_info = {.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
131 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
132 .bindingCount = 2,
133 .pBindings = (VkDescriptorSetLayoutBinding[]){
134 {.binding = 0,
135 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
136 .descriptorCount = 1,
137 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
138 .pImmutableSamplers = NULL},
139 {.binding = 1,
140 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
141 .descriptorCount = 1,
142 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
143 .pImmutableSamplers = NULL},
144 }};
145
146 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_layout_info, &state->alloc,
147 &state->copy_vrs_htile_ds_layout);
148 if (result != VK_SUCCESS)
149 goto fail;
150
151 VkPipelineLayoutCreateInfo p_layout_info = {
152 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
153 .setLayoutCount = 1,
154 .pSetLayouts = &state->copy_vrs_htile_ds_layout,
155 .pushConstantRangeCount = 1,
156 .pPushConstantRanges =
157 &(VkPushConstantRange){
158 VK_SHADER_STAGE_COMPUTE_BIT,
159 0,
160 20,
161 },
162 };
163
164 result = radv_CreatePipelineLayout(radv_device_to_handle(device), &p_layout_info, &state->alloc,
165 &state->copy_vrs_htile_p_layout);
166 if (result != VK_SUCCESS)
167 goto fail;
168
169 VkPipelineShaderStageCreateInfo shader_stage = {
170 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
171 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
172 .module = vk_shader_module_handle_from_nir(cs),
173 .pName = "main",
174 .pSpecializationInfo = NULL,
175 };
176
177 VkComputePipelineCreateInfo pipeline_info = {
178 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
179 .stage = shader_stage,
180 .flags = 0,
181 .layout = state->copy_vrs_htile_p_layout,
182 };
183
184 result = radv_compute_pipeline_create(radv_device_to_handle(device), state->cache, &pipeline_info, NULL,
185 &state->copy_vrs_htile_pipeline);
186 fail:
187 ralloc_free(cs);
188 return result;
189 }
190
191 void
radv_copy_vrs_htile(struct radv_cmd_buffer * cmd_buffer,struct radv_image * vrs_image,const VkRect2D * rect,struct radv_image * dst_image,struct radv_buffer * htile_buffer,bool read_htile_value)192 radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_image, const VkRect2D *rect,
193 struct radv_image *dst_image, struct radv_buffer *htile_buffer, bool read_htile_value)
194 {
195 struct radv_device *device = cmd_buffer->device;
196 struct radv_meta_state *state = &device->meta_state;
197 struct radv_meta_saved_state saved_state;
198 struct radv_image_view vrs_iview;
199
200 assert(radv_image_has_htile(dst_image));
201
202 if (!cmd_buffer->device->meta_state.copy_vrs_htile_pipeline) {
203 VkResult ret = radv_device_init_meta_copy_vrs_htile_state(cmd_buffer->device, &dst_image->planes[0].surface);
204 if (ret != VK_SUCCESS) {
205 vk_command_buffer_set_error(&cmd_buffer->vk, ret);
206 return;
207 }
208 }
209
210 cmd_buffer->state.flush_bits |=
211 radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, NULL) |
212 radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, NULL);
213
214 radv_meta_save(&saved_state, cmd_buffer,
215 RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
216
217 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
218 state->copy_vrs_htile_pipeline);
219
220 radv_image_view_init(&vrs_iview, cmd_buffer->device,
221 &(VkImageViewCreateInfo){
222 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
223 .image = radv_image_to_handle(vrs_image),
224 .viewType = VK_IMAGE_VIEW_TYPE_2D,
225 .format = vrs_image->vk.format,
226 .subresourceRange = {.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
227 .baseMipLevel = 0,
228 .levelCount = 1,
229 .baseArrayLayer = 0,
230 .layerCount = 1},
231 },
232 0, NULL);
233
234 radv_meta_push_descriptor_set(
235 cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, state->copy_vrs_htile_p_layout, 0, /* set */
236 2, /* descriptorWriteCount */
237 (VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
238 .dstBinding = 0,
239 .dstArrayElement = 0,
240 .descriptorCount = 1,
241 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
242 .pImageInfo =
243 (VkDescriptorImageInfo[]){
244 {
245 .sampler = VK_NULL_HANDLE,
246 .imageView = radv_image_view_to_handle(&vrs_iview),
247 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
248 },
249 }},
250 {.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
251 .dstBinding = 1,
252 .dstArrayElement = 0,
253 .descriptorCount = 1,
254 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
255 .pBufferInfo = &(VkDescriptorBufferInfo){.buffer = radv_buffer_to_handle(htile_buffer),
256 .offset = 0,
257 .range = htile_buffer->vk.size}}});
258
259 const unsigned constants[5] = {
260 rect->offset.x,
261 rect->offset.y,
262 dst_image->planes[0].surface.meta_pitch,
263 dst_image->planes[0].surface.meta_slice_size,
264 read_htile_value,
265 };
266
267 vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->copy_vrs_htile_p_layout,
268 VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, constants);
269
270 uint32_t width = DIV_ROUND_UP(rect->extent.width, 8);
271 uint32_t height = DIV_ROUND_UP(rect->extent.height, 8);
272
273 radv_unaligned_dispatch(cmd_buffer, width, height, 1);
274
275 radv_image_view_finish(&vrs_iview);
276
277 radv_meta_restore(&saved_state, cmd_buffer);
278
279 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
280 radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL);
281 }
282