1 /*
2 * Copyright © 2021 Valve Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23 #include "nir/nir_builder.h"
24 #include "radv_meta.h"
25
26 static nir_shader *
build_fmask_copy_compute_shader(struct radv_device * dev,int samples)27 build_fmask_copy_compute_shader(struct radv_device *dev, int samples)
28 {
29 const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, GLSL_TYPE_FLOAT);
30 const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_MS, false, GLSL_TYPE_FLOAT);
31
32 nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_fmask_copy_cs_-%d", samples);
33
34 b.shader->info.workgroup_size[0] = 8;
35 b.shader->info.workgroup_size[1] = 8;
36
37 nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
38 input_img->data.descriptor_set = 0;
39 input_img->data.binding = 0;
40
41 nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform, img_type, "out_img");
42 output_img->data.descriptor_set = 0;
43 output_img->data.binding = 1;
44
45 nir_def *invoc_id = nir_load_local_invocation_id(&b);
46 nir_def *wg_id = nir_load_workgroup_id(&b);
47 nir_def *block_size = nir_imm_ivec3(&b, b.shader->info.workgroup_size[0], b.shader->info.workgroup_size[1],
48 b.shader->info.workgroup_size[2]);
49
50 nir_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
51
52 /* Get coordinates. */
53 nir_def *src_coord = nir_trim_vector(&b, global_id, 2);
54 nir_def *dst_coord = nir_vec4(&b, nir_channel(&b, src_coord, 0), nir_channel(&b, src_coord, 1), nir_undef(&b, 1, 32),
55 nir_undef(&b, 1, 32));
56
57 nir_tex_src frag_mask_srcs[] = {{
58 .src_type = nir_tex_src_coord,
59 .src = nir_src_for_ssa(src_coord),
60 }};
61 nir_def *frag_mask =
62 nir_build_tex_deref_instr(&b, nir_texop_fragment_mask_fetch_amd, nir_build_deref_var(&b, input_img), NULL,
63 ARRAY_SIZE(frag_mask_srcs), frag_mask_srcs);
64
65 /* Get the maximum sample used in this fragment. */
66 nir_def *max_sample_index = nir_imm_int(&b, 0);
67 for (uint32_t s = 0; s < samples; s++) {
68 /* max_sample_index = MAX2(max_sample_index, (frag_mask >> (s * 4)) & 0xf) */
69 max_sample_index = nir_umax(&b, max_sample_index,
70 nir_ubitfield_extract(&b, frag_mask, nir_imm_int(&b, 4 * s), nir_imm_int(&b, 4)));
71 }
72
73 nir_variable *counter = nir_local_variable_create(b.impl, glsl_int_type(), "counter");
74 nir_store_var(&b, counter, nir_imm_int(&b, 0), 0x1);
75
76 nir_loop *loop = nir_push_loop(&b);
77 {
78 nir_def *sample_id = nir_load_var(&b, counter);
79
80 nir_tex_src frag_fetch_srcs[] = {{
81 .src_type = nir_tex_src_coord,
82 .src = nir_src_for_ssa(src_coord),
83 },
84 {
85 .src_type = nir_tex_src_ms_index,
86 .src = nir_src_for_ssa(sample_id),
87 }};
88 nir_def *outval = nir_build_tex_deref_instr(&b, nir_texop_fragment_fetch_amd, nir_build_deref_var(&b, input_img),
89 NULL, ARRAY_SIZE(frag_fetch_srcs), frag_fetch_srcs);
90
91 nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->def, dst_coord, sample_id, outval,
92 nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_MS);
93
94 radv_break_on_count(&b, counter, max_sample_index);
95 }
96 nir_pop_loop(&b, loop);
97
98 return b.shader;
99 }
100
101 void
radv_device_finish_meta_fmask_copy_state(struct radv_device * device)102 radv_device_finish_meta_fmask_copy_state(struct radv_device *device)
103 {
104 struct radv_meta_state *state = &device->meta_state;
105
106 radv_DestroyPipelineLayout(radv_device_to_handle(device), state->fmask_copy.p_layout, &state->alloc);
107 device->vk.dispatch_table.DestroyDescriptorSetLayout(radv_device_to_handle(device), state->fmask_copy.ds_layout,
108 &state->alloc);
109
110 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
111 radv_DestroyPipeline(radv_device_to_handle(device), state->fmask_copy.pipeline[i], &state->alloc);
112 }
113 }
114
115 static VkResult
create_fmask_copy_pipeline(struct radv_device * device,int samples,VkPipeline * pipeline)116 create_fmask_copy_pipeline(struct radv_device *device, int samples, VkPipeline *pipeline)
117 {
118 struct radv_meta_state *state = &device->meta_state;
119 nir_shader *cs = build_fmask_copy_compute_shader(device, samples);
120 VkResult result;
121
122 VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
123 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
124 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
125 .module = vk_shader_module_handle_from_nir(cs),
126 .pName = "main",
127 .pSpecializationInfo = NULL,
128 };
129
130 VkComputePipelineCreateInfo vk_pipeline_info = {
131 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
132 .stage = pipeline_shader_stage,
133 .flags = 0,
134 .layout = state->fmask_copy.p_layout,
135 };
136
137 result =
138 radv_compute_pipeline_create(radv_device_to_handle(device), state->cache, &vk_pipeline_info, NULL, pipeline);
139 ralloc_free(cs);
140 return result;
141 }
142
143 static VkResult
radv_device_init_meta_fmask_copy_state_internal(struct radv_device * device,uint32_t samples_log2)144 radv_device_init_meta_fmask_copy_state_internal(struct radv_device *device, uint32_t samples_log2)
145 {
146 VkResult result;
147
148 if (device->meta_state.fmask_copy.pipeline[samples_log2])
149 return VK_SUCCESS;
150
151 if (!device->meta_state.fmask_copy.ds_layout) {
152 VkDescriptorSetLayoutCreateInfo ds_create_info = {
153 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
154 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
155 .bindingCount = 2,
156 .pBindings = (VkDescriptorSetLayoutBinding[]){
157 {.binding = 0,
158 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
159 .descriptorCount = 1,
160 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
161 .pImmutableSamplers = NULL},
162 {.binding = 1,
163 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
164 .descriptorCount = 1,
165 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
166 .pImmutableSamplers = NULL},
167 }};
168
169 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_create_info, &device->meta_state.alloc,
170 &device->meta_state.fmask_copy.ds_layout);
171 if (result != VK_SUCCESS)
172 return result;
173 }
174
175 if (!device->meta_state.fmask_copy.p_layout) {
176 VkPipelineLayoutCreateInfo pl_create_info = {.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
177 .setLayoutCount = 1,
178 .pSetLayouts = &device->meta_state.fmask_copy.ds_layout,
179 .pushConstantRangeCount = 0,
180 .pPushConstantRanges = NULL};
181
182 result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info, &device->meta_state.alloc,
183 &device->meta_state.fmask_copy.p_layout);
184 if (result != VK_SUCCESS)
185 return result;
186 }
187
188 return create_fmask_copy_pipeline(device, 1u << samples_log2, &device->meta_state.fmask_copy.pipeline[samples_log2]);
189 }
190
191 VkResult
radv_device_init_meta_fmask_copy_state(struct radv_device * device,bool on_demand)192 radv_device_init_meta_fmask_copy_state(struct radv_device *device, bool on_demand)
193 {
194 VkResult result;
195
196 if (on_demand)
197 return VK_SUCCESS;
198
199 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; i++) {
200 result = radv_device_init_meta_fmask_copy_state_internal(device, i);
201 if (result != VK_SUCCESS)
202 return result;
203 }
204
205 return VK_SUCCESS;
206 }
207
208 static void
radv_fixup_copy_dst_metadata(struct radv_cmd_buffer * cmd_buffer,const struct radv_image * src_image,const struct radv_image * dst_image)209 radv_fixup_copy_dst_metadata(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *src_image,
210 const struct radv_image *dst_image)
211 {
212 uint64_t src_offset, dst_offset, size;
213
214 assert(src_image->planes[0].surface.cmask_size == dst_image->planes[0].surface.cmask_size &&
215 src_image->planes[0].surface.fmask_size == dst_image->planes[0].surface.fmask_size);
216 assert(src_image->planes[0].surface.fmask_offset + src_image->planes[0].surface.fmask_size ==
217 src_image->planes[0].surface.cmask_offset &&
218 dst_image->planes[0].surface.fmask_offset + dst_image->planes[0].surface.fmask_size ==
219 dst_image->planes[0].surface.cmask_offset);
220
221 /* Copy CMASK+FMASK. */
222 size = src_image->planes[0].surface.cmask_size + src_image->planes[0].surface.fmask_size;
223 src_offset = src_image->bindings[0].offset + src_image->planes[0].surface.fmask_offset;
224 dst_offset = dst_image->bindings[0].offset + dst_image->planes[0].surface.fmask_offset;
225
226 radv_copy_buffer(cmd_buffer, src_image->bindings[0].bo, dst_image->bindings[0].bo, src_offset, dst_offset, size);
227 }
228
229 bool
radv_can_use_fmask_copy(struct radv_cmd_buffer * cmd_buffer,const struct radv_image * src_image,const struct radv_image * dst_image,unsigned num_rects,const struct radv_meta_blit2d_rect * rects)230 radv_can_use_fmask_copy(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *src_image,
231 const struct radv_image *dst_image, unsigned num_rects,
232 const struct radv_meta_blit2d_rect *rects)
233 {
234 /* TODO: Test on pre GFX10 chips. */
235 if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX10)
236 return false;
237
238 /* TODO: Add support for layers. */
239 if (src_image->vk.array_layers != 1 || dst_image->vk.array_layers != 1)
240 return false;
241
242 /* Source/destination images must have FMASK. */
243 if (!radv_image_has_fmask(src_image) || !radv_image_has_fmask(dst_image))
244 return false;
245
246 /* Source/destination images must have identical TC-compat mode. */
247 if (radv_image_is_tc_compat_cmask(src_image) != radv_image_is_tc_compat_cmask(dst_image))
248 return false;
249
250 /* The region must be a whole image copy. */
251 if (num_rects != 1 ||
252 (rects[0].src_x || rects[0].src_y || rects[0].dst_x || rects[0].dst_y ||
253 rects[0].width != src_image->vk.extent.width || rects[0].height != src_image->vk.extent.height))
254 return false;
255
256 /* Source/destination images must have identical size. */
257 if (src_image->vk.extent.width != dst_image->vk.extent.width ||
258 src_image->vk.extent.height != dst_image->vk.extent.height)
259 return false;
260
261 /* Source/destination images must have identical swizzle. */
262 if (src_image->planes[0].surface.fmask_tile_swizzle != dst_image->planes[0].surface.fmask_tile_swizzle ||
263 src_image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode !=
264 dst_image->planes[0].surface.u.gfx9.color.fmask_swizzle_mode)
265 return false;
266
267 return true;
268 }
269
270 void
radv_fmask_copy(struct radv_cmd_buffer * cmd_buffer,struct radv_meta_blit2d_surf * src,struct radv_meta_blit2d_surf * dst)271 radv_fmask_copy(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src,
272 struct radv_meta_blit2d_surf *dst)
273 {
274 struct radv_device *device = cmd_buffer->device;
275 struct radv_image_view src_iview, dst_iview;
276 uint32_t samples = src->image->vk.samples;
277 uint32_t samples_log2 = ffs(samples) - 1;
278
279 VkResult result = radv_device_init_meta_fmask_copy_state_internal(device, samples_log2);
280 if (result != VK_SUCCESS) {
281 vk_command_buffer_set_error(&cmd_buffer->vk, result);
282 return;
283 }
284
285 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
286 cmd_buffer->device->meta_state.fmask_copy.pipeline[samples_log2]);
287
288 radv_image_view_init(&src_iview, device,
289 &(VkImageViewCreateInfo){
290 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
291 .image = radv_image_to_handle(src->image),
292 .viewType = radv_meta_get_view_type(src->image),
293 .format = vk_format_no_srgb(src->image->vk.format),
294 .subresourceRange =
295 {
296 .aspectMask = src->aspect_mask,
297 .baseMipLevel = 0,
298 .levelCount = 1,
299 .baseArrayLayer = 0,
300 .layerCount = 1,
301 },
302 },
303 0, NULL);
304
305 radv_image_view_init(&dst_iview, device,
306 &(VkImageViewCreateInfo){
307 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
308 .image = radv_image_to_handle(dst->image),
309 .viewType = radv_meta_get_view_type(dst->image),
310 .format = vk_format_no_srgb(dst->image->vk.format),
311 .subresourceRange =
312 {
313 .aspectMask = dst->aspect_mask,
314 .baseMipLevel = 0,
315 .levelCount = 1,
316 .baseArrayLayer = 0,
317 .layerCount = 1,
318 },
319 },
320 0, NULL);
321
322 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
323 cmd_buffer->device->meta_state.fmask_copy.p_layout, 0, /* set */
324 2, /* descriptorWriteCount */
325 (VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
326 .dstBinding = 0,
327 .dstArrayElement = 0,
328 .descriptorCount = 1,
329 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
330 .pImageInfo =
331 (VkDescriptorImageInfo[]){
332 {.sampler = VK_NULL_HANDLE,
333 .imageView = radv_image_view_to_handle(&src_iview),
334 .imageLayout = VK_IMAGE_LAYOUT_GENERAL},
335 }},
336 {.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
337 .dstBinding = 1,
338 .dstArrayElement = 0,
339 .descriptorCount = 1,
340 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
341 .pImageInfo = (VkDescriptorImageInfo[]){
342 {.sampler = VK_NULL_HANDLE,
343 .imageView = radv_image_view_to_handle(&dst_iview),
344 .imageLayout = VK_IMAGE_LAYOUT_GENERAL},
345 }}});
346
347 radv_unaligned_dispatch(cmd_buffer, src->image->vk.extent.width, src->image->vk.extent.height, 1);
348
349 /* Fixup destination image metadata by copying CMASK/FMASK from the source image. */
350 radv_fixup_copy_dst_metadata(cmd_buffer, src->image, dst->image);
351 }
352