1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27 #ifndef RADV_ACO_SHADER_INFO_H
28 #define RADV_ACO_SHADER_INFO_H
29
30 /* this will convert from radv shader info to the ACO one. */
31
32 #include "ac_hw_stage.h"
33 #include "aco_shader_info.h"
34
35 #define ASSIGN_FIELD(x) aco_info->x = radv->x
36 #define ASSIGN_FIELD_CP(x) memcpy(&aco_info->x, &radv->x, sizeof(radv->x))
37
38 static inline void radv_aco_convert_ps_epilog_key(struct aco_ps_epilog_info *aco_info,
39 const struct radv_ps_epilog_key *radv,
40 const struct radv_shader_args *radv_args);
41
42 static inline void
radv_aco_convert_shader_info(struct aco_shader_info * aco_info,const struct radv_shader_info * radv,const struct radv_shader_args * radv_args,const struct radv_device_cache_key * radv_key,const enum amd_gfx_level gfx_level)43 radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv_shader_info *radv,
44 const struct radv_shader_args *radv_args, const struct radv_device_cache_key *radv_key,
45 const enum amd_gfx_level gfx_level)
46 {
47 ASSIGN_FIELD(wave_size);
48 ASSIGN_FIELD(has_ngg_culling);
49 ASSIGN_FIELD(has_ngg_early_prim_export);
50 ASSIGN_FIELD(workgroup_size);
51 ASSIGN_FIELD(has_epilog);
52 ASSIGN_FIELD(merged_shader_compiled_separately);
53 ASSIGN_FIELD(vs.tcs_in_out_eq);
54 ASSIGN_FIELD(vs.tcs_temp_only_input_mask);
55 ASSIGN_FIELD(vs.has_prolog);
56 ASSIGN_FIELD(tcs.num_lds_blocks);
57 ASSIGN_FIELD(tcs.num_linked_outputs);
58 ASSIGN_FIELD(tcs.num_linked_patch_outputs);
59 ASSIGN_FIELD(tcs.tcs_vertices_out);
60 ASSIGN_FIELD(ps.num_interp);
61 ASSIGN_FIELD(cs.uses_full_subgroups);
62 aco_info->ps.spi_ps_input_ena = radv->ps.spi_ps_input;
63 aco_info->ps.spi_ps_input_addr = radv->ps.spi_ps_input;
64 aco_info->gfx9_gs_ring_lds_size = radv->gs_ring_info.lds_size;
65 aco_info->is_trap_handler_shader = radv->type == RADV_SHADER_TYPE_TRAP_HANDLER;
66 aco_info->image_2d_view_of_3d = radv_key->image_2d_view_of_3d;
67 aco_info->ps.epilog_pc = radv_args->ps_epilog_pc;
68 aco_info->hw_stage = radv_select_hw_stage(radv, gfx_level);
69 aco_info->tcs.epilog_pc = radv_args->tcs_epilog_pc;
70 aco_info->tcs.tcs_offchip_layout = radv_args->tcs_offchip_layout;
71 aco_info->next_stage_pc = radv_args->next_stage_pc;
72 }
73
74 static inline void
radv_aco_convert_vs_prolog_key(struct aco_vs_prolog_info * aco_info,const struct radv_vs_prolog_key * radv,const struct radv_shader_args * radv_args)75 radv_aco_convert_vs_prolog_key(struct aco_vs_prolog_info *aco_info, const struct radv_vs_prolog_key *radv,
76 const struct radv_shader_args *radv_args)
77 {
78 ASSIGN_FIELD(instance_rate_inputs);
79 ASSIGN_FIELD(nontrivial_divisors);
80 ASSIGN_FIELD(zero_divisors);
81 ASSIGN_FIELD(post_shuffle);
82 ASSIGN_FIELD(alpha_adjust_lo);
83 ASSIGN_FIELD(alpha_adjust_hi);
84 ASSIGN_FIELD_CP(formats);
85 ASSIGN_FIELD(num_attributes);
86 ASSIGN_FIELD(misaligned_mask);
87 ASSIGN_FIELD(is_ngg);
88 ASSIGN_FIELD(next_stage);
89
90 aco_info->inputs = radv_args->prolog_inputs;
91 }
92
93 static inline void
radv_aco_convert_tcs_epilog_key(struct aco_tcs_epilog_info * aco_info,const struct radv_tcs_epilog_key * radv,const struct radv_shader_args * radv_args)94 radv_aco_convert_tcs_epilog_key(struct aco_tcs_epilog_info *aco_info, const struct radv_tcs_epilog_key *radv,
95 const struct radv_shader_args *radv_args)
96 {
97 aco_info->pass_tessfactors_by_reg = false;
98 ASSIGN_FIELD(tcs_out_patch_fits_subgroup);
99 ASSIGN_FIELD(primitive_mode);
100 ASSIGN_FIELD(tes_reads_tessfactors);
101
102 aco_info->tcs_offchip_layout = radv_args->tcs_offchip_layout;
103 aco_info->invocation_id = radv_args->invocation_id;
104 aco_info->rel_patch_id = radv_args->rel_patch_id;
105 aco_info->tcs_out_current_patch_data_offset = radv_args->tcs_out_current_patch_data_offset;
106 aco_info->patch_base = radv_args->patch_base;
107 }
108
109 static inline void
radv_aco_convert_ps_epilog_key(struct aco_ps_epilog_info * aco_info,const struct radv_ps_epilog_key * radv,const struct radv_shader_args * radv_args)110 radv_aco_convert_ps_epilog_key(struct aco_ps_epilog_info *aco_info, const struct radv_ps_epilog_key *radv,
111 const struct radv_shader_args *radv_args)
112 {
113 ASSIGN_FIELD(spi_shader_col_format);
114 ASSIGN_FIELD(color_is_int8);
115 ASSIGN_FIELD(color_is_int10);
116 ASSIGN_FIELD(mrt0_is_dual_src);
117 ASSIGN_FIELD(alpha_to_coverage_via_mrtz);
118
119 memcpy(aco_info->colors, radv_args->colors, sizeof(aco_info->colors));
120 aco_info->depth = radv_args->depth;
121 aco_info->stencil = radv_args->stencil;
122 aco_info->samplemask = radv_args->sample_mask;
123
124 aco_info->alpha_func = COMPARE_FUNC_ALWAYS;
125 }
126
127 static inline void
radv_aco_convert_opts(struct aco_compiler_options * aco_info,const struct radv_nir_compiler_options * radv,const struct radv_shader_args * radv_args,const struct radv_shader_stage_key * stage_key)128 radv_aco_convert_opts(struct aco_compiler_options *aco_info, const struct radv_nir_compiler_options *radv,
129 const struct radv_shader_args *radv_args, const struct radv_shader_stage_key *stage_key)
130 {
131 ASSIGN_FIELD(dump_shader);
132 ASSIGN_FIELD(dump_preoptir);
133 ASSIGN_FIELD(record_ir);
134 ASSIGN_FIELD(record_stats);
135 ASSIGN_FIELD(enable_mrt_output_nan_fixup);
136 ASSIGN_FIELD(wgp_mode);
137 ASSIGN_FIELD(debug.func);
138 ASSIGN_FIELD(debug.private_data);
139 ASSIGN_FIELD(debug.private_data);
140 aco_info->is_opengl = false;
141 aco_info->load_grid_size_from_user_sgpr = radv_args->load_grid_size_from_user_sgpr;
142 aco_info->optimisations_disabled = stage_key->optimisations_disabled;
143 aco_info->gfx_level = radv->info->gfx_level;
144 aco_info->family = radv->info->family;
145 aco_info->address32_hi = radv->info->address32_hi;
146 aco_info->has_ls_vgpr_init_bug = radv->info->has_ls_vgpr_init_bug;
147 }
148 #undef ASSIGN_VS_STATE_FIELD
149 #undef ASSIGN_VS_STATE_FIELD_CP
150 #undef ASSIGN_FIELD
151 #undef ASSIGN_FIELD_CP
152
153 #endif
154