1 /* 2 * Copyright © 2016 Red Hat. 3 * Copyright © 2016 Bas Nieuwenhuizen 4 * 5 * based in part on anv driver which is: 6 * Copyright © 2015 Intel Corporation 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 25 * IN THE SOFTWARE. 26 */ 27 28 #ifndef RADV_CONSTANTS_H 29 #define RADV_CONSTANTS_H 30 31 #define ATI_VENDOR_ID 0x1002 32 33 #define MAX_VBS 32 34 #define MAX_VERTEX_ATTRIBS 32 35 #define MAX_RTS 8 36 #define MAX_VIEWPORTS 16 37 #define MAX_SCISSORS 16 38 #define MAX_DISCARD_RECTANGLES 4 39 #define MAX_SAMPLE_LOCATIONS 32 40 #define MAX_PUSH_CONSTANTS_SIZE 256 41 #define MAX_PUSH_DESCRIPTORS 32 42 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16 43 #define MAX_DYNAMIC_STORAGE_BUFFERS 8 44 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS) 45 #define MAX_SAMPLES_LOG2 4 46 #define NUM_META_FS_KEYS 12 47 #define RADV_MAX_DRM_DEVICES 8 48 #define MAX_VIEWS 8 49 #define MAX_SO_STREAMS 4 50 #define MAX_SO_BUFFERS 4 51 #define MAX_SO_OUTPUTS 128 52 #define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024) 53 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64 54 #define MAX_BIND_POINTS 3 /* compute + graphics + raytracing */ 55 56 #define NUM_DEPTH_CLEAR_PIPELINES 2 57 #define NUM_DEPTH_DECOMPRESS_PIPELINES 3 58 #define MAX_FRAMEBUFFER_WIDTH (1u << 14) 59 #define MAX_FRAMEBUFFER_HEIGHT (1u << 14) 60 61 /* 62 * This is the point we switch from using CP to compute shader 63 * for certain buffer operations. 64 */ 65 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096 66 67 #define RADV_BUFFER_UPDATE_THRESHOLD 1024 68 69 /* descriptor index into scratch ring offsets */ 70 #define RING_SCRATCH 0 71 #define RING_ESGS_VS 1 72 #define RING_ESGS_GS 2 73 #define RING_GSVS_VS 3 74 #define RING_GSVS_GS 4 75 #define RING_HS_TESS_FACTOR 5 76 #define RING_HS_TESS_OFFCHIP 6 77 #define RING_TS_DRAW 7 78 #define RING_TS_PAYLOAD 8 79 #define RING_MS_SCRATCH 9 80 #define RING_PS_ATTR 10 81 #define RING_PS_SAMPLE_POSITIONS 11 82 83 #define SI_GS_PER_ES 128 84 85 /* max number of descriptor sets */ 86 #define MAX_SETS 32 87 88 /* Make sure everything is addressable by a signed 32-bit int, and 89 * our largest descriptors are 96 bytes. 90 */ 91 #define RADV_MAX_PER_SET_DESCRIPTORS ((1ull << 31) / 96) 92 93 /* Our buffer size fields allow only 2**32 - 1. We round that down to a multiple 94 * of 4 bytes so we can align buffer sizes up. 95 */ 96 #define RADV_MAX_MEMORY_ALLOCATION_SIZE 0xFFFFFFFCull 97 98 /* Number of entries in the mesh shader scratch ring. 99 * This depends on VGT_GS_MAX_WAVE_ID which is set by the kernel 100 * and is impossible to query. We leave it on its maximum value 101 * because real applications are unlikely to use it. 102 * 103 * The maximum ID on GFX10.3 is 2047 (0x7ff), so we need 2048 entries. 104 */ 105 #define RADV_MESH_SCRATCH_NUM_ENTRIES 2048 106 107 /* Size of each entry in the mesh shader scratch ring. 108 * We must ensure that the absolute maximum mesh shader output fits here. 109 * 110 * Mesh shaders can create up to 256 vertices/primitives per workgroup, 111 * and up to the following amount of outputs: 112 * - 32 parameters 113 * - 4 positions (clip/cull distance, etc.) 114 * - 4 per-primitive built-in outputs (layer, view index, prim id, VRS rate) 115 * - primitive indices which are always kept in LDS 116 * That is a total of 32+4+4=40 output slots x 16 bytes per slot x 256 = 160K bytes. 117 */ 118 #define RADV_MESH_SCRATCH_ENTRY_BYTES (160 * 1024) 119 120 /* Number of invocations in each subgroup. */ 121 #define RADV_SUBGROUP_SIZE 64 122 123 /* The spec requires this to be 32. */ 124 #define RADV_RT_HANDLE_SIZE 32 125 126 #define RADV_MAX_HIT_ATTRIB_SIZE 32 127 #define RADV_MAX_HIT_ATTRIB_DWORDS (RADV_MAX_HIT_ATTRIB_SIZE / 4) 128 129 #define RADV_SHADER_ALLOC_ALIGNMENT 256 130 #define RADV_SHADER_ALLOC_MIN_ARENA_SIZE (256 * 1024) 131 /* 256 KiB << 5 = 8 MiB */ 132 #define RADV_SHADER_ALLOC_MAX_ARENA_SIZE_SHIFT 5u 133 #define RADV_SHADER_ALLOC_MIN_SIZE_CLASS 8 134 #define RADV_SHADER_ALLOC_MAX_SIZE_CLASS 15 135 #define RADV_SHADER_ALLOC_NUM_FREE_LISTS (RADV_SHADER_ALLOC_MAX_SIZE_CLASS - RADV_SHADER_ALLOC_MIN_SIZE_CLASS + 1) 136 137 #define PERF_CTR_MAX_PASSES 512 138 #define PERF_CTR_BO_PASS_OFFSET 16 139 #define PERF_CTR_BO_LOCK_OFFSET 0 140 #define PERF_CTR_BO_FENCE_OFFSET 8 141 142 /* The maximum number of in-flight uploads (radv_shader_dma_submission) when asynchronous shader 143 * upload is used. 144 */ 145 #define RADV_SHADER_UPLOAD_CS_COUNT 32 146 147 /* Shader GDS counters: 148 * offset 0| 4| 8|12 - reserved for NGG streamout counters 149 * offset 16 - number of primitives generated by geometry shader invocations 150 * offset 20 - number of geometry shader invocations 151 * offset 24|28|32|36 - generated primitive counter for stream 0|1|2|3 152 * offset 40|44|48|52 - written primitive counter for stream 0|1|2|3 153 * 154 * Mesh shader GDS counters: 155 * offset 56 - number of mesh shader invocations 156 * offset 60 - number of mesh shader generated primitives 157 * 158 * Task shader GDS counter: 159 * offset 64 - number of task shader invocations 160 */ 161 #define RADV_SHADER_QUERY_GS_PRIM_EMIT_OFFSET 16 162 #define RADV_SHADER_QUERY_GS_INVOCATION_OFFSET 20 163 #define RADV_SHADER_QUERY_PRIM_GEN_OFFSET(stream) (24 + stream * 4) 164 #define RADV_SHADER_QUERY_PRIM_XFB_OFFSET(stream) (40 + stream * 4) 165 #define RADV_SHADER_QUERY_MS_INVOCATION_OFFSET 56 166 #define RADV_SHADER_QUERY_MS_PRIM_GEN_OFFSET 60 167 #define RADV_SHADER_QUERY_TS_INVOCATION_OFFSET 64 168 169 /* Number of samples for line smooth lowering (hw requirement). */ 170 #define RADV_NUM_SMOOTH_AA_SAMPLES 4 171 172 /* Size of the temporary buffer allocated for transfer queue copy command workarounds. 173 * The size is chosen so that it can fit two lines of (1 << 14) blocks at 16 bpp. 174 */ 175 #define RADV_SDMA_TRANSFER_TEMP_BYTES (2 * (1 << 14) * 16) 176 177 #endif /* RADV_CONSTANTS_H */ 178