1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * IN THE SOFTWARE.
27 */
28
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
31
32 #include <stdbool.h>
33 #include <stdint.h>
34 #include <stdio.h>
35 #include <stdlib.h>
36 #include <string.h>
37 #include "util/u_math.h"
38 #include "util/u_memory.h"
39 #include <vulkan/vulkan.h>
40 #include "amd_family.h"
41
42 struct radeon_info;
43 struct ac_surf_info;
44 struct radeon_surf;
45 struct vk_sync_type;
46 struct vk_sync_wait;
47 struct vk_sync_signal;
48
49 enum radeon_bo_domain { /* bitfield */
50 RADEON_DOMAIN_GTT = 2,
51 RADEON_DOMAIN_VRAM = 4,
52 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
53 RADEON_DOMAIN_GDS = 8,
54 RADEON_DOMAIN_OA = 16,
55 };
56
57 enum radeon_bo_flag { /* bitfield */
58 RADEON_FLAG_GTT_WC = (1 << 0),
59 RADEON_FLAG_CPU_ACCESS = (1 << 1),
60 RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
61 RADEON_FLAG_VIRTUAL = (1 << 3),
62 RADEON_FLAG_VA_UNCACHED = (1 << 4),
63 RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
64 RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
65 RADEON_FLAG_READ_ONLY = (1 << 7),
66 RADEON_FLAG_32BIT = (1 << 8),
67 RADEON_FLAG_PREFER_LOCAL_BO = (1 << 9),
68 RADEON_FLAG_ZERO_VRAM = (1 << 10),
69 RADEON_FLAG_REPLAYABLE = (1 << 11),
70 RADEON_FLAG_DISCARDABLE = (1 << 12),
71 };
72
73 enum radeon_ctx_priority {
74 RADEON_CTX_PRIORITY_INVALID = -1,
75 RADEON_CTX_PRIORITY_LOW = 0,
76 RADEON_CTX_PRIORITY_MEDIUM,
77 RADEON_CTX_PRIORITY_HIGH,
78 RADEON_CTX_PRIORITY_REALTIME,
79 };
80
81 enum radeon_ctx_pstate {
82 RADEON_CTX_PSTATE_NONE = 0,
83 RADEON_CTX_PSTATE_STANDARD,
84 RADEON_CTX_PSTATE_MIN_SCLK,
85 RADEON_CTX_PSTATE_MIN_MCLK,
86 RADEON_CTX_PSTATE_PEAK,
87 };
88
89 enum radeon_value_id {
90 RADEON_ALLOCATED_VRAM,
91 RADEON_ALLOCATED_VRAM_VIS,
92 RADEON_ALLOCATED_GTT,
93 RADEON_TIMESTAMP,
94 RADEON_NUM_BYTES_MOVED,
95 RADEON_NUM_EVICTIONS,
96 RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
97 RADEON_VRAM_USAGE,
98 RADEON_VRAM_VIS_USAGE,
99 RADEON_GTT_USAGE,
100 RADEON_GPU_TEMPERATURE,
101 RADEON_CURRENT_SCLK,
102 RADEON_CURRENT_MCLK,
103 };
104
105 struct radeon_cmdbuf {
106 /* These are uint64_t to tell the compiler that buf can't alias them.
107 * If they're uint32_t the generated code needs to redundantly
108 * store and reload them between buf writes. */
109 uint64_t cdw; /* Number of used dwords. */
110 uint64_t max_dw; /* Maximum number of dwords. */
111 uint64_t reserved_dw; /* Number of dwords reserved through radeon_check_space() */
112 uint32_t *buf; /* The base pointer of the chunk. */
113 };
114
115 #define RADEON_SURF_TYPE_MASK 0xFF
116 #define RADEON_SURF_TYPE_SHIFT 0
117 #define RADEON_SURF_TYPE_1D 0
118 #define RADEON_SURF_TYPE_2D 1
119 #define RADEON_SURF_TYPE_3D 2
120 #define RADEON_SURF_TYPE_CUBEMAP 3
121 #define RADEON_SURF_TYPE_1D_ARRAY 4
122 #define RADEON_SURF_TYPE_2D_ARRAY 5
123 #define RADEON_SURF_MODE_MASK 0xFF
124 #define RADEON_SURF_MODE_SHIFT 8
125
126 #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_##field##_SHIFT) & RADEON_SURF_##field##_MASK)
127 #define RADEON_SURF_SET(v, field) (((v)&RADEON_SURF_##field##_MASK) << RADEON_SURF_##field##_SHIFT)
128 #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_##field##_MASK << RADEON_SURF_##field##_SHIFT))
129
130 enum radeon_bo_layout {
131 RADEON_LAYOUT_LINEAR = 0,
132 RADEON_LAYOUT_TILED,
133 RADEON_LAYOUT_SQUARETILED,
134
135 RADEON_LAYOUT_UNKNOWN
136 };
137
138 /* Tiling info for display code, DRI sharing, and other data. */
139 struct radeon_bo_metadata {
140 /* Tiling flags describing the texture layout for display code
141 * and DRI sharing.
142 */
143 union {
144 struct {
145 enum radeon_bo_layout microtile;
146 enum radeon_bo_layout macrotile;
147 unsigned pipe_config;
148 unsigned bankw;
149 unsigned bankh;
150 unsigned tile_split;
151 unsigned mtilea;
152 unsigned num_banks;
153 unsigned stride;
154 bool scanout;
155 } legacy;
156
157 struct {
158 /* surface flags */
159 unsigned swizzle_mode : 5;
160 bool scanout;
161 uint32_t dcc_offset_256b;
162 uint32_t dcc_pitch_max;
163 bool dcc_independent_64b_blocks;
164 bool dcc_independent_128b_blocks;
165 unsigned dcc_max_compressed_block_size;
166 } gfx9;
167 } u;
168
169 /* Additional metadata associated with the buffer, in bytes.
170 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
171 * Supported by amdgpu only.
172 */
173 uint32_t size_metadata;
174 uint32_t metadata[64];
175 };
176
177 struct radeon_winsys_ctx;
178
179 struct radeon_winsys_bo {
180 uint64_t va;
181 /* buffer is created with AMDGPU_GEM_CREATE_VM_ALWAYS_VALID */
182 bool is_local;
183 bool vram_no_cpu_access;
184 /* buffer is added to the BO list of all submissions */
185 bool use_global_list;
186 enum radeon_bo_domain initial_domain;
187 };
188
189 struct radv_winsys_submit_info {
190 enum amd_ip_type ip_type;
191 int queue_index;
192 unsigned cs_count;
193 unsigned initial_preamble_count;
194 unsigned continue_preamble_count;
195 unsigned postamble_count;
196 struct radeon_cmdbuf **cs_array;
197 struct radeon_cmdbuf **initial_preamble_cs;
198 struct radeon_cmdbuf **continue_preamble_cs;
199 struct radeon_cmdbuf **postamble_cs;
200 bool uses_shadow_regs;
201 };
202
203 /* Kernel effectively allows 0-31. This sets some priorities for fixed
204 * functionality buffers */
205 enum {
206 RADV_BO_PRIORITY_APPLICATION_MAX = 28,
207
208 /* virtual buffers have 0 priority since the priority is not used. */
209 RADV_BO_PRIORITY_VIRTUAL = 0,
210
211 RADV_BO_PRIORITY_METADATA = 10,
212 /* This should be considerably lower than most of the stuff below,
213 * but how much lower is hard to say since we don't know application
214 * assignments. Put it pretty high since it is GTT anyway. */
215 RADV_BO_PRIORITY_QUERY_POOL = 29,
216
217 RADV_BO_PRIORITY_DESCRIPTOR = 30,
218 RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
219 RADV_BO_PRIORITY_FENCE = 30,
220 RADV_BO_PRIORITY_SHADER = 31,
221 RADV_BO_PRIORITY_SCRATCH = 31,
222 RADV_BO_PRIORITY_CS = 31,
223 };
224
225 struct radv_winsys_gpuvm_fault_info {
226 uint64_t addr;
227 uint32_t status;
228 uint32_t vmhub;
229 };
230
231 enum radv_cs_dump_type {
232 RADV_CS_DUMP_TYPE_IBS,
233 RADV_CS_DUMP_TYPE_CTX_ROLLS,
234 };
235
236 struct radeon_winsys {
237 void (*destroy)(struct radeon_winsys *ws);
238
239 void (*query_info)(struct radeon_winsys *ws, struct radeon_info *info);
240
241 uint64_t (*query_value)(struct radeon_winsys *ws, enum radeon_value_id value);
242
243 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers, uint32_t *out);
244
245 const char *(*get_chip_name)(struct radeon_winsys *ws);
246
247 bool (*query_gpuvm_fault)(struct radeon_winsys *ws, struct radv_winsys_gpuvm_fault_info *fault_info);
248
249 VkResult (*buffer_create)(struct radeon_winsys *ws, uint64_t size, unsigned alignment, enum radeon_bo_domain domain,
250 enum radeon_bo_flag flags, unsigned priority, uint64_t address,
251 struct radeon_winsys_bo **out_bo);
252
253 void (*buffer_destroy)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo);
254 void *(*buffer_map)(struct radeon_winsys_bo *bo);
255
256 VkResult (*buffer_from_ptr)(struct radeon_winsys *ws, void *pointer, uint64_t size, unsigned priority,
257 struct radeon_winsys_bo **out_bo);
258
259 VkResult (*buffer_from_fd)(struct radeon_winsys *ws, int fd, unsigned priority, struct radeon_winsys_bo **out_bo,
260 uint64_t *alloc_size);
261
262 bool (*buffer_get_fd)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, int *fd);
263
264 bool (*buffer_get_flags_from_fd)(struct radeon_winsys *ws, int fd, enum radeon_bo_domain *domains,
265 enum radeon_bo_flag *flags);
266
267 void (*buffer_unmap)(struct radeon_winsys_bo *bo);
268
269 void (*buffer_set_metadata)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, struct radeon_bo_metadata *md);
270 void (*buffer_get_metadata)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, struct radeon_bo_metadata *md);
271
272 VkResult (*buffer_virtual_bind)(struct radeon_winsys *ws, struct radeon_winsys_bo *parent, uint64_t offset,
273 uint64_t size, struct radeon_winsys_bo *bo, uint64_t bo_offset);
274
275 VkResult (*buffer_make_resident)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, bool resident);
276
277 VkResult (*ctx_create)(struct radeon_winsys *ws, enum radeon_ctx_priority priority, struct radeon_winsys_ctx **ctx);
278 void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
279
280 bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, enum amd_ip_type amd_ip_type, int ring_index);
281
282 int (*ctx_set_pstate)(struct radeon_winsys_ctx *ctx, uint32_t pstate);
283
284 enum radeon_bo_domain (*cs_domain)(const struct radeon_winsys *ws);
285
286 struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum amd_ip_type amd_ip_type, bool is_secondary);
287
288 void (*cs_destroy)(struct radeon_cmdbuf *cs);
289
290 void (*cs_reset)(struct radeon_cmdbuf *cs);
291
292 bool (*cs_chain)(struct radeon_cmdbuf *cs, struct radeon_cmdbuf *next_cs, bool pre_en);
293
294 void (*cs_unchain)(struct radeon_cmdbuf *cs);
295
296 VkResult (*cs_finalize)(struct radeon_cmdbuf *cs);
297
298 void (*cs_grow)(struct radeon_cmdbuf *cs, size_t min_size);
299
300 VkResult (*cs_submit)(struct radeon_winsys_ctx *ctx, const struct radv_winsys_submit_info *submit,
301 uint32_t wait_count, const struct vk_sync_wait *waits, uint32_t signal_count,
302 const struct vk_sync_signal *signals);
303
304 void (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo);
305
306 void (*cs_execute_secondary)(struct radeon_cmdbuf *parent, struct radeon_cmdbuf *child, bool allow_ib2);
307
308 void (*cs_execute_ib)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo, const uint64_t offset,
309 const uint32_t cdw, const bool predicate);
310
311 void (*cs_dump)(struct radeon_cmdbuf *cs, FILE *file, const int *trace_ids, int trace_id_count,
312 enum radv_cs_dump_type type);
313
314 void (*dump_bo_ranges)(struct radeon_winsys *ws, FILE *file);
315
316 void (*dump_bo_log)(struct radeon_winsys *ws, FILE *file);
317
318 int (*surface_init)(struct radeon_winsys *ws, const struct ac_surf_info *surf_info, struct radeon_surf *surf);
319
320 int (*get_fd)(struct radeon_winsys *ws);
321
322 struct ac_addrlib *(*get_addrlib)(struct radeon_winsys *ws);
323
324 const struct vk_sync_type *const *(*get_sync_types)(struct radeon_winsys *ws);
325 };
326
327 static inline void
radeon_emit(struct radeon_cmdbuf * cs,uint32_t value)328 radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
329 {
330 assert(cs->cdw < cs->reserved_dw);
331 cs->buf[cs->cdw++] = value;
332 }
333
334 static inline void
radeon_emit_array(struct radeon_cmdbuf * cs,const uint32_t * values,unsigned count)335 radeon_emit_array(struct radeon_cmdbuf *cs, const uint32_t *values, unsigned count)
336 {
337 assert(cs->cdw + count <= cs->reserved_dw);
338 memcpy(cs->buf + cs->cdw, values, count * 4);
339 cs->cdw += count;
340 }
341
342 static inline uint64_t
radv_buffer_get_va(const struct radeon_winsys_bo * bo)343 radv_buffer_get_va(const struct radeon_winsys_bo *bo)
344 {
345 return bo->va;
346 }
347
348 static inline bool
radv_buffer_is_resident(const struct radeon_winsys_bo * bo)349 radv_buffer_is_resident(const struct radeon_winsys_bo *bo)
350 {
351 return bo->use_global_list || bo->is_local;
352 }
353
354 static inline void
radv_cs_add_buffer(struct radeon_winsys * ws,struct radeon_cmdbuf * cs,struct radeon_winsys_bo * bo)355 radv_cs_add_buffer(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo)
356 {
357 if (radv_buffer_is_resident(bo))
358 return;
359
360 ws->cs_add_buffer(cs, bo);
361 }
362
363 #endif /* RADV_RADEON_WINSYS_H */
364