1 /*
2 * Copyright 2023 Alyssa Rosenzweig
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "compiler/shader_enums.h"
7 #include "agx_tilebuffer.h"
8 #include "nir.h"
9 #include "nir_builder.h"
10 #include "nir_builder_opcodes.h"
11 #include "nir_intrinsics_indices.h"
12
13 /*
14 * If a fragment shader reads the layer ID but the vertex shader does not write
15 * the layer ID, the fragment shader is supposed to read zero. However, in our
16 * hardware, if the vertex shader does not write the layer ID, the value read by
17 * the fragment shader is UNDEFINED. To reconcile, the driver passes in whether
18 * the layer ID value is written, and this pass predicates layer ID on that
19 * system value. This handles both cases without shader variants, at the cost of
20 * a single instruction.
21 */
22 static bool
lower(nir_builder * b,nir_intrinsic_instr * intr,void * _)23 lower(nir_builder *b, nir_intrinsic_instr *intr, void *_)
24 {
25 if (intr->intrinsic != nir_intrinsic_load_input)
26 return false;
27
28 if (nir_intrinsic_io_semantics(intr).location != VARYING_SLOT_LAYER)
29 return false;
30
31 b->cursor = nir_after_instr(&intr->instr);
32 nir_def *written = nir_load_layer_id_written_agx(b);
33
34 /* Zero extend the mask since layer IDs are 16-bits, so upper bits of the
35 * layer ID are necessarily zero.
36 */
37 nir_def *mask = nir_u2uN(b, written, intr->def.bit_size);
38 nir_def *repl = nir_iand(b, &intr->def, mask);
39 nir_def_rewrite_uses_after(&intr->def, repl, repl->parent_instr);
40 return true;
41 }
42
43 bool
agx_nir_predicate_layer_id(nir_shader * shader)44 agx_nir_predicate_layer_id(nir_shader *shader)
45 {
46 assert(shader->info.stage == MESA_SHADER_FRAGMENT);
47 assert(shader->info.inputs_read & VARYING_BIT_LAYER);
48
49 return nir_shader_intrinsics_pass(
50 shader, lower, nir_metadata_block_index | nir_metadata_dominance, NULL);
51 }
52