1 /*
2 * Copyright (C) 2014-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Christian Gmeiner <christian.gmeiner@gmail.com>
25 */
26
27 #ifndef ETNAVIV_DRMIF_H_
28 #define ETNAVIV_DRMIF_H_
29
30 #include <xf86drm.h>
31 #include <stdbool.h>
32 #include <stdint.h>
33
34 struct etna_bo;
35 struct etna_pipe;
36 struct etna_gpu;
37 struct etna_device;
38 struct etna_cmd_stream;
39 struct etna_perfmon;
40 struct etna_perfmon_domain;
41 struct etna_perfmon_signal;
42
43 enum etna_pipe_id {
44 ETNA_PIPE_3D = 0,
45 ETNA_PIPE_2D = 1,
46 ETNA_PIPE_VG = 2,
47 ETNA_PIPE_MAX
48 };
49
50 enum etna_param_id {
51 ETNA_GPU_MODEL = 0x1,
52 ETNA_GPU_REVISION = 0x2,
53 ETNA_GPU_FEATURES_0 = 0x3,
54 ETNA_GPU_FEATURES_1 = 0x4,
55 ETNA_GPU_FEATURES_2 = 0x5,
56 ETNA_GPU_FEATURES_3 = 0x6,
57 ETNA_GPU_FEATURES_4 = 0x7,
58 ETNA_GPU_FEATURES_5 = 0x8,
59 ETNA_GPU_FEATURES_6 = 0x9,
60 ETNA_GPU_FEATURES_7 = 0xa,
61 ETNA_GPU_FEATURES_8 = 0xb,
62 ETNA_GPU_FEATURES_9 = 0xc,
63 ETNA_GPU_FEATURES_10 = 0xd,
64 ETNA_GPU_FEATURES_11 = 0xe,
65 ETNA_GPU_FEATURES_12 = 0xf,
66
67 ETNA_GPU_STREAM_COUNT = 0x10,
68 ETNA_GPU_REGISTER_MAX = 0x11,
69 ETNA_GPU_THREAD_COUNT = 0x12,
70 ETNA_GPU_VERTEX_CACHE_SIZE = 0x13,
71 ETNA_GPU_SHADER_CORE_COUNT = 0x14,
72 ETNA_GPU_PIXEL_PIPES = 0x15,
73 ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE = 0x16,
74 ETNA_GPU_BUFFER_SIZE = 0x17,
75 ETNA_GPU_INSTRUCTION_COUNT = 0x18,
76 ETNA_GPU_NUM_CONSTANTS = 0x19,
77 ETNA_GPU_NUM_VARYINGS = 0x1a,
78 ETNA_SOFTPIN_START_ADDR = 0x1b,
79 ETNA_GPU_PRODUCT_ID = 0x1c,
80 ETNA_GPU_CUSTOMER_ID = 0x1d,
81 ETNA_GPU_ECO_ID = 0x1e,
82 ETNA_GPU_NN_CORE_COUNT = 0x1f,
83 ETNA_GPU_NN_MAD_PER_CORE = 0x20,
84 ETNA_GPU_TP_CORE_COUNT = 0x21,
85 ETNA_GPU_ON_CHIP_SRAM_SIZE = 0x22,
86 ETNA_GPU_AXI_SRAM_SIZE = 0x23,
87 };
88
89 /* bo flags: */
90 #define DRM_ETNA_GEM_CACHE_CACHED 0x00010000
91 #define DRM_ETNA_GEM_CACHE_WC 0x00020000
92 #define DRM_ETNA_GEM_CACHE_UNCACHED 0x00040000
93 #define DRM_ETNA_GEM_CACHE_MASK 0x000f0000
94 /* map flags */
95 #define DRM_ETNA_GEM_FORCE_MMU 0x00100000
96
97 /* bo access flags: (keep aligned to ETNA_PREP_x) */
98 #define DRM_ETNA_PREP_READ 0x01
99 #define DRM_ETNA_PREP_WRITE 0x02
100 #define DRM_ETNA_PREP_NOSYNC 0x04
101
102 /* device functions:
103 */
104
105 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
106
107 struct etna_device *etna_device_new(int fd);
108 struct etna_device *etna_device_new_dup(int fd);
109 struct etna_device *etna_device_ref(struct etna_device *dev);
110 void etna_device_del(struct etna_device *dev);
111 int etna_device_fd(struct etna_device *dev);
112 bool etnaviv_device_softpin_capable(struct etna_device *dev);
113 uint32_t etnaviv_device_version(struct etna_device *dev);
114
115 /* gpu functions:
116 */
117
118 struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core);
119 void etna_gpu_del(struct etna_gpu *gpu);
120 int etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param,
121 uint64_t *value);
122
123
124 /* pipe functions:
125 */
126
127 struct etna_pipe *etna_pipe_new(struct etna_gpu *gpu, enum etna_pipe_id id);
128 void etna_pipe_del(struct etna_pipe *pipe);
129 int etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns);
130
131
132 /* buffer-object functions:
133 */
134
135 struct etna_bo *etna_bo_new(struct etna_device *dev,
136 uint32_t size, uint32_t flags);
137 struct etna_bo *etna_bo_from_name(struct etna_device *dev, uint32_t name);
138 struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd);
139 struct etna_bo *etna_bo_ref(struct etna_bo *bo);
140 void etna_bo_del(struct etna_bo *bo);
141 int etna_bo_get_name(struct etna_bo *bo, uint32_t *name);
142 uint32_t etna_bo_handle(struct etna_bo *bo);
143 int etna_bo_dmabuf(struct etna_bo *bo);
144 uint32_t etna_bo_size(struct etna_bo *bo);
145 uint32_t etna_bo_gpu_va(struct etna_bo *bo);
146 void * etna_bo_map(struct etna_bo *bo);
147 int etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op);
148 void etna_bo_cpu_fini(struct etna_bo *bo);
149 int etna_bo_is_idle(struct etna_bo *bo);
150
151
152 /* cmd stream functions:
153 */
154
155 struct etna_cmd_stream {
156 uint32_t *buffer;
157 uint32_t offset; /* in 32-bit words */
158 uint32_t size; /* in 32-bit words */
159 };
160
161 struct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe, uint32_t size,
162 void (*reset_notify)(struct etna_cmd_stream *stream, void *priv),
163 void *priv);
164 void etna_cmd_stream_del(struct etna_cmd_stream *stream);
165 uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream);
166 void etna_cmd_stream_flush(struct etna_cmd_stream *stream, int in_fence_fd,
167 int *out_fence_fd, bool is_noop);
168 void etna_cmd_stream_force_flush(struct etna_cmd_stream *stream);
169
etna_cmd_stream_avail(struct etna_cmd_stream * stream)170 static inline uint32_t etna_cmd_stream_avail(struct etna_cmd_stream *stream)
171 {
172 static const uint32_t END_CLEARANCE = 2; /* LINK op code */
173
174 return stream->size - stream->offset - END_CLEARANCE;
175 }
176
177 void etna_cmd_stream_realloc(struct etna_cmd_stream *stream, size_t n);
178
etna_cmd_stream_reserve(struct etna_cmd_stream * stream,size_t n)179 static inline void etna_cmd_stream_reserve(struct etna_cmd_stream *stream, size_t n)
180 {
181 if (etna_cmd_stream_avail(stream) < n)
182 etna_cmd_stream_realloc(stream, n);
183 }
184
etna_cmd_stream_emit(struct etna_cmd_stream * stream,uint32_t data)185 static inline void etna_cmd_stream_emit(struct etna_cmd_stream *stream, uint32_t data)
186 {
187 stream->buffer[stream->offset++] = data;
188 }
189
etna_cmd_stream_get(struct etna_cmd_stream * stream,uint32_t offset)190 static inline uint32_t etna_cmd_stream_get(struct etna_cmd_stream *stream, uint32_t offset)
191 {
192 return stream->buffer[offset];
193 }
194
etna_cmd_stream_set(struct etna_cmd_stream * stream,uint32_t offset,uint32_t data)195 static inline void etna_cmd_stream_set(struct etna_cmd_stream *stream, uint32_t offset,
196 uint32_t data)
197 {
198 stream->buffer[offset] = data;
199 }
200
etna_cmd_stream_offset(struct etna_cmd_stream * stream)201 static inline uint32_t etna_cmd_stream_offset(struct etna_cmd_stream *stream)
202 {
203 return stream->offset;
204 }
205
206 struct etna_reloc {
207 struct etna_bo *bo;
208 #define ETNA_RELOC_READ 0x0001
209 #define ETNA_RELOC_WRITE 0x0002
210 uint32_t flags;
211 uint32_t offset;
212 };
213
214 void etna_cmd_stream_reloc(struct etna_cmd_stream *stream, const struct etna_reloc *r);
215 void etna_cmd_stream_ref_bo(struct etna_cmd_stream *stream,
216 struct etna_bo *bo, uint32_t flags);
217
218 void etna_cmd_stream_mark_end_of_context_init(struct etna_cmd_stream *stream);
219
220 /* performance monitoring functions:
221 */
222
223 struct etna_perfmon *etna_perfmon_create(struct etna_pipe *pipe);
224 void etna_perfmon_del(struct etna_perfmon *perfmon);
225 struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name);
226 struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name);
227
228 struct etna_perf {
229 #define ETNA_PM_PROCESS_PRE 0x0001
230 #define ETNA_PM_PROCESS_POST 0x0002
231 uint32_t flags;
232 uint32_t sequence;
233 struct etna_perfmon_signal *signal;
234 struct etna_bo *bo;
235 uint32_t offset;
236 };
237
238 void etna_cmd_stream_perf(struct etna_cmd_stream *stream, const struct etna_perf *p);
239
240 #endif /* ETNAVIV_DRMIF_H_ */
241