1<?xml version="1.0" encoding="UTF-8"?> 2<!-- 3Copyright © 2023 Igalia S.L. 4SPDX-License-Identifier: MIT 5 --> 6 7<isa> 8 9<template name="INSTR_ALU"> 10 {NAME}{SAT}{COND}{TYPE}{PMODE}{THREAD}{RMODE} 11</template> 12 13<template name="INSTR_TEX"> 14 {NAME}{TEX_SWIZ} 15</template> 16 17<template name="INSTR_CF"> 18 {NAME}{COND}{TYPE} 19</template> 20 21<template name="INSTR_LOAD_STORE"> 22 {NAME}{COND}{SKPHP}{DENORM}{LOCAL}{TYPE}{PMODE} 23</template> 24 25<template name="INSTR_LOAD_STORE_WITH_LEFT_SHIFT"> 26 {NAME}{COND}{SKPHP}{DENORM}{LOCAL}.ls{LEFT_SHIFT}{TYPE}{PMODE} 27</template> 28 29<enum name="#cond"> 30 <value val="0" name=".true" display=""/> 31 <value val="1" display=".gt"/> 32 <value val="2" display=".lt"/> 33 <value val="3" display=".ge"/> 34 <value val="4" display=".le"/> 35 <value val="5" display=".eq"/> 36 <value val="6" display=".ne"/> 37 <value val="7" display=".and"/> 38 <value val="8" display=".or"/> 39 <value val="9" display=".xor"/> 40 <value val="10" display=".not"/> 41 <value val="11" display=".nz"/> 42 <value val="12" display=".gez"/> 43 <value val="13" display=".gz"/> 44 <value val="14" display=".lez"/> 45 <value val="15" display=".lz"/> 46 <value val="22" display=".0x16"/> 47</enum> 48 49<enum name="#swiz"> 50 <value val="0" display="x"/> 51 <value val="1" display="y"/> 52 <value val="2" display="z"/> 53 <value val="3" display="w"/> 54</enum> 55 56<enum name="#type"> 57 <value val="0" name=".f32" display=""/> 58 <value val="1" display=".s32"/> 59 <value val="2" display=".s8"/> 60 <value val="3" display=".u16"/> 61 <value val="4" display=".f16"/> 62 <value val="5" display=".s16"/> 63 <value val="6" display=".u32"/> 64 <value val="7" display=".u8"/> 65</enum> 66 67<enum name="#reg_group"> 68 <value val="0" display="t"/> 69 <value val="2" display="u"/> 70 <value val="3" display="u2"/> 71 <value val="4" display="th"/> 72 <value val="7" name="immed" display=""/> 73</enum> 74 75<enum name="#reg_addressing_mode"> 76 <value val="0" display=""/> 77 <value val="1" display="[a.x]"/> 78 <value val="2" display="[a.y]"/> 79 <value val="3" display="[a.z]"/> 80 <value val="4" display="[a.w]"/> 81</enum> 82 83<enum name="#rounding"> 84 <value val="0" display=""/> 85 <value val="1" display=".rtz"/> 86 <value val="2" display=".rtne"/> 87 <value val="3" display=".unkown"/> 88 <value val="4" display=".unkown2"/> 89</enum> 90 91<enum name="#wrmask"> 92 <value val="0" display=".____"/> 93 <value val="1" display=".x___"/> 94 <value val="2" display="._y__"/> 95 <value val="3" display=".xy__"/> 96 <value val="4" display=".__z_"/> 97 <value val="5" display=".zx"/> 98 <value val="6" display=".zy"/> 99 <value val="7" display=".xyz_"/> 100 <value val="8" display=".___w"/> 101 <value val="9" display=".x__w"/> 102 <value val="10" display="._y_w"/> 103 <value val="11" display=".xy_w"/> 104 <value val="12" display=".__zw"/> 105 <value val="13" display=".x_zw"/> 106 <value val="14" display="._yzw"/> 107 <value val="15" display=""/> <!-- xyzw --> 108</enum> 109 110<bitset name="#instruction-dst" size="14"> 111 <override> 112 <expr> 113 {DST_USE} == 0 114 </expr> 115 <display> 116 void 117 </display> 118 </override> 119 120 <display> 121 t{REG}{AMODE}{COMPS} 122 </display> 123 124 <field name="AMODE" low="0" high="2" type="#reg_addressing_mode"/> 125 <field name="REG" low="3" high="9" type="uint"/> 126 <field name="COMPS" low="10" high="13" type="#wrmask"/> 127</bitset> 128 129<bitset name="#instruction" size="128"> 130 <field name="COND" low="6" high="10" type="#cond"/> 131 <field name="SAT" pos="11" type="bool" display=".sat"/> 132 133 <field name="TYPE_BIT2" pos="53" type="uint"/> 134 <pattern low="65" high="66">00</pattern> 135 <field name="TYPE_BIT01" low="94" high="95" type="int"/> 136 137 <derived name="TYPE" type="#type"> 138 <expr>{TYPE_BIT2} << 2 | {TYPE_BIT01}</expr> 139 </derived> 140</bitset> 141 142<bitset name="#src-swizzle" size="8"> 143 <display> 144 .{SWIZ_X}{SWIZ_Y}{SWIZ_Z}{SWIZ_W} 145 </display> 146 147 <field name="SWIZ_X" low="0" high="1" type="#swiz"/> 148 <field name="SWIZ_Y" low="2" high="3" type="#swiz"/> 149 <field name="SWIZ_Z" low="4" high="5" type="#swiz"/> 150 <field name="SWIZ_W" low="6" high="7" type="#swiz"/> 151</bitset> 152 153<enum name="#thread"> 154 <value val="0" display=""/> 155 <value val="1" display=".t0"/> 156 <value val="2" display=".t1"/> 157</enum> 158 159<bitset name="#instruction-alu-base" extends="#instruction"> 160 <field name="DST_USE" pos="12" type="bool"/> 161 <field name="DST" low="13" high="26" type="#instruction-dst"> 162 <param name="DST_USE"/> 163 <param name="COMPS"/> 164 </field> 165 <pattern low="27" high="31">00000</pattern> <!-- TEX_ID --> 166 <field name="RMODE" low="32" high="33" type="#rounding"/> 167 <field name="PMODE" pos="34" type="bool_inv" display=".pack"/> 168 169 <field name="LOW_HALF" pos="109" type="bool"/> 170 <field name="HIGH_HALF" pos="120" type="bool"/> 171 172 <derived name="THREAD" type="#thread"> 173 <expr>{HIGH_HALF} << 1 | {LOW_HALF}</expr> 174 </derived> 175 176 <field name="DST_FULL" pos="127" type="bool" display=".hp"/> 177</bitset> 178 179<bitset name="#instruction-alu" extends="#instruction-alu-base"> 180 <pattern low="35" high="42">00000000</pattern><!-- TEX_SWIZ --> 181</bitset> 182 183<bitset name="#instruction-src" size="10"> 184 <display> 185 {SRC_NEG}{SRC_ABS}{SRC_RGROUP}{SRC_REG}{SRC_AMODE}{SRC_SWIZ}{SRC_ABS} 186 </display> 187 188 <field name="SRC_SWIZ" low="0" high="7" type="#src-swizzle"/> 189 <field name="SRC_NEG" pos="8" type="bool" display="-"/> 190 <field name="SRC_ABS" pos="9" type="bool" display="|"/> 191 192 <derived name="IMMED_TYPE" type="uint"> 193 <expr>({SRC_AMODE} >> 1)</expr> <!-- lowest bit is the sign bit --> 194 </derived> 195 196 <override> 197 <expr> 198 (({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 0)) 199 </expr> 200 201 <display> 202 {IMMED} 203 </display> 204 205 <derived name="IMMED" type="float" width="32"> 206 <expr> 207 (((({SRC_AMODE} & 0x1) << 19) | 208 ({SRC_ABS} << 18) | 209 ({SRC_NEG} << 17) | 210 ({SRC_SWIZ} << 9) | 211 {SRC_REG}) << 12) 212 </expr> 213 </derived> 214 </override> 215 216 <override> 217 <expr> 218 (({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 1)) 219 </expr> 220 221 <display> 222 {IMMED} 223 </display> 224 225 <derived name="IMMED" type="int" width="20"> 226 <expr> 227 ((({SRC_AMODE} & 0x1) << 19) | 228 ({SRC_ABS} << 18) | 229 ({SRC_NEG} << 17) | 230 ({SRC_SWIZ} << 9) | 231 {SRC_REG}) 232 </expr> 233 </derived> 234 </override> 235 236 <override> 237 <expr> 238 (({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 2)) 239 </expr> 240 241 <display> 242 {IMMED} 243 </display> 244 245 <derived name="IMMED" type="uint" width="20"> 246 <expr> 247 ((({SRC_AMODE} & 0x1) << 19) | 248 ({SRC_ABS} << 18) | 249 ({SRC_NEG} << 17) | 250 ({SRC_SWIZ} << 9) | 251 {SRC_REG}) 252 </expr> 253 </derived> 254 </override> 255 256 <override> 257 <expr> 258 (({SRC_RGROUP} == 7) & ({IMMED_TYPE} == 3)) 259 </expr> 260 261 <display> 262 {IMMED} 263 </display> 264 265 <derived name="IMMED" type="float" width="16"> 266 <expr> 267 ((({SRC_AMODE} & 0x1) << 19) | 268 ({SRC_ABS} << 18) | 269 ({SRC_NEG} << 17) | 270 ({SRC_SWIZ} << 9) | 271 {SRC_REG}) 272 </expr> 273 </derived> 274 </override> 275</bitset> 276 277<bitset name="#instruction-alu-atomic" extends="#instruction-alu-base"> 278 <display> 279 {INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, {SRC2} 280 </display> 281 282 <pattern low="35" high="42">xxxxxxxx</pattern><!-- TEX_SWIZ --> 283 284 <!-- SRC0 --> 285 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 286 <field name="SRC0_REG" low="44" high="52" type="uint"/> 287 <field name="SRC0" low="54" high="63" type="#instruction-src"> 288 <param name="SRC0_REG" as="SRC_REG"/> 289 <param name="SRC0_AMODE" as="SRC_AMODE"/> 290 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 291 </field> 292 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 293 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 294 295 <!-- SRC1 --> 296 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 297 <field name="SRC1_REG" low="71" high="79" type="uint"/> 298 <field name="SRC1" low="81" high="90" type="#instruction-src"> 299 <param name="SRC1_REG" as="SRC_REG"/> 300 <param name="SRC1_AMODE" as="SRC_AMODE"/> 301 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 302 </field> 303 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 304 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 305 306 <!-- SRC2 --> 307 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 308 <field name="SRC2_REG" low="100" high="108" type="uint"/> 309 <field name="SRC2" low="110" high="119" type="#instruction-src"> 310 <param name="SRC2_REG" as="SRC_REG"/> 311 <param name="SRC2_AMODE" as="SRC_AMODE"/> 312 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 313 </field> 314 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 315 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 316</bitset> 317 318<bitset name="#instruction-alu-atomic" extends="#instruction-alu-base"> 319 <display> 320 {INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, {SRC2} 321 </display> 322 323 <pattern low="35" high="42">xxxxxxxx</pattern> 324 325 <!-- SRC0 --> 326 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 327 <field name="SRC0_REG" low="44" high="52" type="uint"/> 328 <field name="SRC0" low="54" high="63" type="#instruction-src"> 329 <param name="SRC0_REG" as="SRC_REG"/> 330 <param name="SRC0_AMODE" as="SRC_AMODE"/> 331 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 332 </field> 333 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 334 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 335 336 <!-- SRC1 --> 337 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 338 <field name="SRC1_REG" low="71" high="79" type="uint"/> 339 <field name="SRC1" low="81" high="90" type="#instruction-src"> 340 <param name="SRC1_REG" as="SRC_REG"/> 341 <param name="SRC1_AMODE" as="SRC_AMODE"/> 342 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 343 </field> 344 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 345 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 346 347 <!-- SRC2 --> 348 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 349 <field name="SRC2_REG" low="100" high="108" type="uint"/> 350 <field name="SRC2" low="110" high="119" type="#instruction-src"> 351 <param name="SRC2_REG" as="SRC_REG"/> 352 <param name="SRC2_AMODE" as="SRC_AMODE"/> 353 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 354 </field> 355 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 356 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 357</bitset> 358 359<bitset name="#instruction-alu-no-src" extends="#instruction-alu"> 360 <display> 361 {NAME} {DST:align=18}{DST_FULL}, void, void, void 362 </display> 363 364 <!-- SRC0 --> 365 <pattern pos="43">0</pattern> <!-- SRC0_USE --> 366 <pattern low="44" high="52">000000000</pattern> <!-- SRC0_REG --> 367 <pattern low="54" high="61">00000000</pattern> <!-- SRC0_SWIZ --> 368 <pattern pos="62">0</pattern> <!-- SRC0_NEG --> 369 <pattern pos="63">0</pattern> <!-- SRC0_ABS --> 370 <pattern pos="64">0</pattern> <!-- SRC0_AMODE --> 371 <pattern low="67" high="69">000</pattern> <!-- SRC0_RGROUP --> 372 373 <!-- SRC1 --> 374 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 375 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 376 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 377 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 378 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 379 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 380 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 381 382 <!-- SRC2 --> 383 <pattern pos="99">0</pattern> <!-- SRC2_USE --> 384 <pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG --> 385 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 386 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 387 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 388 <pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE --> 389 <pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP --> 390</bitset> 391 392<expr name="#instruction-alu-no-dst-has-src0-src1"> 393 ({SRC0_USE} != 0) && ({SRC1_USE} != 0) 394</expr> 395 396<bitset name="#instruction-alu-no-dst-maybe-src1-src2" extends="#instruction-alu"> 397 <doc>Needed for texkill</doc> 398 <display> 399 {NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}{DST_FULL}, void, void, void 400 </display> 401 402 <override expr="#instruction-alu-no-dst-has-src0-src1"> 403 <display> 404 {NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}, {SRC0}, {SRC1}, void 405 </display> 406 </override> 407 408 <!-- SRC0 --> 409 <field name="SRC0_USE" pos="43" type="bool"/> 410 <field name="SRC0_REG" low="44" high="52" type="uint"/> 411 <field name="SRC0" low="54" high="63" type="#instruction-src"> 412 <param name="SRC0_REG" as="SRC_REG"/> 413 <param name="SRC0_AMODE" as="SRC_AMODE"/> 414 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 415 </field> 416 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 417 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 418 419 <!-- SRC1 --> 420 <field name="SRC1_USE" pos="70" type="bool"/> 421 <field name="SRC1_REG" low="71" high="79" type="uint"/> 422 <field name="SRC1" low="81" high="90" type="#instruction-src"> 423 <param name="SRC1_REG" as="SRC_REG"/> 424 <param name="SRC1_AMODE" as="SRC_AMODE"/> 425 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 426 </field> 427 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 428 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 429 430 <!-- SRC2 --> 431 <pattern pos="99">0</pattern> <!-- SRC2_USE --> 432 <pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG --> 433 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 434 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 435 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 436 <pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE --> 437 <pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP --> 438</bitset> 439 440<bitset name="#instruction-alu-src0" extends="#instruction-alu"> 441 <display> 442 {INSTR_ALU} {DST:align=18}, {SRC0}, void, void 443 </display> 444 445 <!-- SRC0 --> 446 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 447 <field name="SRC0_REG" low="44" high="52" type="uint"/> 448 <field name="SRC0" low="54" high="63" type="#instruction-src"> 449 <param name="SRC0_REG" as="SRC_REG"/> 450 <param name="SRC0_AMODE" as="SRC_AMODE"/> 451 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 452 </field> 453 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 454 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 455 456 <!-- SRC1 --> 457 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 458 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 459 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 460 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 461 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 462 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 463 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 464 465 <!-- SRC2 --> 466 <pattern pos="99">0</pattern> <!-- SRC2_USE --> 467 <pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG --> 468 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 469 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 470 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 471 <pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE --> 472 <pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP --> 473</bitset> 474 475<bitset name="#instruction-alu-src2" extends="#instruction-alu"> 476 <display> 477 {INSTR_ALU} {DST:align=18}, void, void, {SRC2} 478 </display> 479 480 <!-- SRC0 --> 481 <pattern pos="43">0</pattern> <!-- SRC0_USE --> 482 <pattern low="44" high="52">000000000</pattern> <!-- SRC0_REG --> 483 <pattern low="54" high="61">00000000</pattern> <!-- SRC0_SWIZ --> 484 <pattern pos="62">0</pattern> <!-- SRC0_NEG --> 485 <pattern pos="63">0</pattern> <!-- SRC0_ABS --> 486 <pattern pos="64">0</pattern> <!-- SRC0_AMODE --> 487 <pattern low="67" high="69">000</pattern> <!-- SRC0_RGROUP --> 488 489 <!-- SRC1 --> 490 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 491 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 492 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 493 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 494 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 495 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 496 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 497 498 <!-- SRC2 --> 499 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 500 <field name="SRC2_REG" low="100" high="108" type="uint"/> 501 <field name="SRC2" low="110" high="119" type="#instruction-src"> 502 <param name="SRC2_REG" as="SRC_REG"/> 503 <param name="SRC2_AMODE" as="SRC_AMODE"/> 504 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 505 </field> 506 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 507 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 508</bitset> 509 510<bitset name="#instruction-alu-src0-src1" extends="#instruction-alu"> 511 <display> 512 {INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, void 513 </display> 514 515 <!-- SRC0 --> 516 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 517 <field name="SRC0_REG" low="44" high="52" type="uint"/> 518 <field name="SRC0" low="54" high="63" type="#instruction-src"> 519 <param name="SRC0_REG" as="SRC_REG"/> 520 <param name="SRC0_AMODE" as="SRC_AMODE"/> 521 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 522 </field> 523 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 524 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 525 526 <!-- SRC1 --> 527 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 528 <field name="SRC1_REG" low="71" high="79" type="uint"/> 529 <field name="SRC1" low="81" high="90" type="#instruction-src"> 530 <param name="SRC1_REG" as="SRC_REG"/> 531 <param name="SRC1_AMODE" as="SRC_AMODE"/> 532 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 533 </field> 534 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 535 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 536 537 <!-- SRC2 --> 538 <pattern pos="99">0</pattern> <!-- SRC2_USE --> 539 <pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG --> 540 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 541 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 542 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 543 <pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE --> 544 <pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP --> 545</bitset> 546 547<bitset name="#instruction-alu-src0-src2" extends="#instruction-alu"> 548 <display> 549 {INSTR_ALU} {DST:align=18}, {SRC0}, void, {SRC2} 550 </display> 551 552 <!-- SRC0 --> 553 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 554 <field name="SRC0_REG" low="44" high="52" type="uint"/> 555 <field name="SRC0" low="54" high="63" type="#instruction-src"> 556 <param name="SRC0_REG" as="SRC_REG"/> 557 <param name="SRC0_AMODE" as="SRC_AMODE"/> 558 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 559 </field> 560 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 561 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 562 563 <!-- SRC1 --> 564 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 565 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 566 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 567 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 568 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 569 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 570 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 571 572 <!-- SRC2 --> 573 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 574 <field name="SRC2_REG" low="100" high="108" type="uint"/> 575 <field name="SRC2" low="110" high="119" type="#instruction-src"> 576 <param name="SRC2_REG" as="SRC_REG"/> 577 <param name="SRC2_AMODE" as="SRC_AMODE"/> 578 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 579 </field> 580 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 581 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 582</bitset> 583 584<bitset name="#instruction-alu-src0-src1-src2" extends="#instruction-alu"> 585 <display> 586 {INSTR_ALU} {DST:align=18}, {SRC0}, {SRC1}, {SRC2} 587 </display> 588 589 <!-- SRC0 --> 590 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 591 <field name="SRC0_REG" low="44" high="52" type="uint"/> 592 <field name="SRC0" low="54" high="63" type="#instruction-src"> 593 <param name="SRC0_REG" as="SRC_REG"/> 594 <param name="SRC0_AMODE" as="SRC_AMODE"/> 595 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 596 </field> 597 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 598 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 599 600 <!-- SRC1 --> 601 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 602 <field name="SRC1_REG" low="71" high="79" type="uint"/> 603 <field name="SRC1" low="81" high="90" type="#instruction-src"> 604 <param name="SRC1_REG" as="SRC_REG"/> 605 <param name="SRC1_AMODE" as="SRC_AMODE"/> 606 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 607 </field> 608 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 609 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 610 611 <!-- SRC2 --> 612 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 613 <field name="SRC2_REG" low="100" high="108" type="uint"/> 614 <field name="SRC2" low="110" high="119" type="#instruction-src"> 615 <param name="SRC2_REG" as="SRC_REG"/> 616 <param name="SRC2_AMODE" as="SRC_AMODE"/> 617 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 618 </field> 619 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 620 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 621</bitset> 622 623<bitset name="#instruction-tex" extends="#instruction"> 624 <field name="DST_USE" pos="12" type="bool"/> 625 <field name="DST" low="13" high="26" type="#instruction-dst"> 626 <param name="DST_USE"/> 627 <param name="COMPS"/> 628 </field> 629 <field name="TEX_ID" low="27" high="31" type="uint"/> 630 <field name="RMODE" low="32" high="34" type="#reg_addressing_mode"/> 631 <field name="TEX_SWIZ" low="35" high="42" type="#src-swizzle"/> 632 633 <pattern pos="109">0</pattern> 634 <pattern pos="120">0</pattern> 635 <pattern pos="127">0</pattern> 636</bitset> 637 638<bitset name="#instruction-tex-src0" extends="#instruction-tex"> 639 <display> 640 {INSTR_TEX} {DST:align=18}, tex{TEX_ID}, {SRC0}, void, void 641 </display> 642 643 <!-- SRC0 --> 644 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 645 <field name="SRC0_REG" low="44" high="52" type="uint"/> 646 <field name="SRC0" low="54" high="63" type="#instruction-src"> 647 <param name="SRC0_REG" as="SRC_REG"/> 648 <param name="SRC0_AMODE" as="SRC_AMODE"/> 649 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 650 </field> 651 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 652 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 653 654 <!-- SRC1 --> 655 <pattern pos="70">0</pattern> <!-- SRC1_USE --> 656 <pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG --> 657 <pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ --> 658 <pattern pos="89">0</pattern> <!-- SRC1_NEG --> 659 <pattern pos="90">0</pattern> <!-- SRC1_ABS --> 660 <pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE --> 661 <pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP --> 662 663 <!-- SRC2 --> 664 <pattern pos="99">0</pattern> <!-- SRC2_USE --> 665 <pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG --> 666 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 667 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 668 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 669 <pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE --> 670 <pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP --> 671</bitset> 672 673<bitset name="#instruction-tex-src0-src1-src2" extends="#instruction-tex"> 674 <display> 675 {INSTR_TEX} {DST:align=18}, tex{TEX_ID}, {SRC0}, {SRC1}, {SRC2} 676 </display> 677 678 <!-- SRC0 --> 679 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 680 <field name="SRC0_REG" low="44" high="52" type="uint"/> 681 <field name="SRC0" low="54" high="63" type="#instruction-src"> 682 <param name="SRC0_REG" as="SRC_REG"/> 683 <param name="SRC0_AMODE" as="SRC_AMODE"/> 684 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 685 </field> 686 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 687 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 688 689 <!-- SRC1 --> 690 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 691 <field name="SRC1_REG" low="71" high="79" type="uint"/> 692 <field name="SRC1" low="81" high="90" type="#instruction-src"> 693 <param name="SRC2_REG" as="SRC_REG"/> 694 <param name="SRC2_AMODE" as="SRC_AMODE"/> 695 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 696 </field> 697 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 698 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 699 700 <!-- SRC2 --> 701 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 702 <field name="SRC2_REG" low="100" high="108" type="uint"/> 703 <field name="SRC2" low="110" high="119" type="#instruction-src"> 704 <param name="SRC2_REG" as="SRC_REG"/> 705 <param name="SRC2_AMODE" as="SRC_AMODE"/> 706 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 707 </field> 708 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 709 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 710</bitset> 711 712<bitset name="#instruction-cf" extends="#instruction"> 713 <pattern low="12" high="31">00000000000000000000</pattern> 714 715 <pattern low="32" high="33">00</pattern> <!-- RMODE --> 716 <pattern pos="34">x</pattern><!-- PMODE --> 717 <pattern low="35" high="42">00000000</pattern><!-- TEX_SWIZ --> 718 719 <pattern low="99" high="102">0000</pattern> 720 <field name="TARGET" low="103" high="117" type="absbranch"/> 721 <pattern low="118" high="127">0000000000</pattern> 722</bitset> 723 724<bitset name="#instruction-cf-no-src" extends="#instruction-cf"> 725 <display> 726 {INSTR_CF} {:align=18}void, void, void, {TARGET} 727 </display> 728 729 <pattern low="43" high="52">0000000000</pattern> 730 <pattern low="54" high="63">0000000000</pattern> 731 732 <pattern pos="64">0</pattern> 733 <pattern low="67" high="79">0000000000000</pattern> 734 <pattern low="81" high="93">0000000000000</pattern> 735 <pattern low="96" high="98">000</pattern> 736</bitset> 737 738<bitset name="#instruction-cf-src1-src2" extends="#instruction-cf"> 739 <display> 740 {INSTR_CF} {:align=18}void, {SRC0}, {SRC1}, {TARGET} 741 </display> 742 743 <!-- SRC0 --> 744 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 745 <field name="SRC0_REG" low="44" high="52" type="uint"/> 746 <field name="SRC0" low="54" high="63" type="#instruction-src"> 747 <param name="SRC0_REG" as="SRC_REG"/> 748 <param name="SRC0_AMODE" as="SRC_AMODE"/> 749 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 750 </field> 751 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 752 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 753 754 <!-- SRC1 --> 755 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 756 <field name="SRC1_REG" low="71" high="79" type="uint"/> 757 <field name="SRC1" low="81" high="90" type="#instruction-src"> 758 <param name="SRC1_REG" as="SRC_REG"/> 759 <param name="SRC1_AMODE" as="SRC_AMODE"/> 760 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 761 </field> 762 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 763 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 764</bitset> 765 766<expr name="#instruction-has-left-shift"> 767 ({LEFT_SHIFT} != 0) 768</expr> 769 770<bitset name="#instruction-load" extends="#instruction"> 771 <field name="DST_USE" pos="12" type="bool"/> 772 <field name="DST" low="13" high="26" type="#instruction-dst"> 773 <param name="DST_USE"/> 774 <param name="COMPS"/> 775 </field> 776 777 <pattern low="27" high="31">00000</pattern> <!-- TEX_ID --> 778 <pattern low="32" high="33">00</pattern> <!-- RMODE --> 779 <field name="PMODE" pos="34" type="bool_inv" display=".pack"/> 780 <field name="LEFT_SHIFT" low="35" high="36" type="uint"/> 781 <pattern low="37" high="38">00</pattern> 782 <field name="SKPHP" pos="39" type="bool" display=".skpHp"/> 783 <field name="LOCAL" pos="40" type="bool" display=".local"/> 784 <pattern pos="41">0</pattern> 785 <field name="DENORM" pos="42" type="bool" display=".denorm"/> 786 787 <field name="LOW_HALF" pos="109" type="bool"/> 788 <field name="HIGH_HALF" pos="120" type="bool"/> 789 790 <derived name="THREAD" type="#thread"> 791 <expr>{HIGH_HALF} << 1 | {LOW_HALF}</expr> 792 </derived> 793 794 <field name="DST_FULL" pos="127" type="bool" display=".hp"/> 795 796 <display> 797 {INSTR_LOAD_STORE} {DST:align=18}, {SRC0}, {SRC1}, void 798 </display> 799 800 <override expr="#instruction-has-left-shift"> 801 <display> 802 {INSTR_LOAD_STORE_WITH_LEFT_SHIFT} {DST:align=18}, {SRC0}, {SRC1}, void 803 </display> 804 </override> 805 806 <!-- SRC0 --> 807 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 808 <field name="SRC0_REG" low="44" high="52" type="uint"/> 809 <field name="SRC0" low="54" high="63" type="#instruction-src"> 810 <param name="SRC0_REG" as="SRC_REG"/> 811 <param name="SRC0_AMODE" as="SRC_AMODE"/> 812 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 813 </field> 814 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 815 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 816 817 <!-- SRC1 --> 818 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 819 <field name="SRC1_REG" low="71" high="79" type="uint"/> 820 <field name="SRC1" low="81" high="90" type="#instruction-src"> 821 <param name="SRC1_REG" as="SRC_REG"/> 822 <param name="SRC1_AMODE" as="SRC_AMODE"/> 823 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 824 </field> 825 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 826 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 827 828 <!-- SRC2 --> 829 <pattern pos="99">0</pattern> <!-- SRC2_USE --> 830 <pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG --> 831 <pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ --> 832 <pattern pos="118">0</pattern> <!-- SRC2_NEG --> 833 <pattern pos="119">0</pattern> <!-- SRC2_ABS --> 834 <pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE --> 835 <pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP --> 836</bitset> 837 838<bitset name="#instruction-store" extends="#instruction"> 839 <pattern low="12" high="16">xxxxx</pattern> 840 <pattern pos="17">x</pattern> 841 <pattern low="18" high="22">xxxxx</pattern> 842 <field name="COMPS" low="23" high="26" type="#wrmask"/> 843 <pattern low="27" high="31">xxxxx</pattern> 844 <pattern low="32" high="33">xx</pattern> 845 <field name="PMODE" pos="34" type="bool_inv" display=".pack"/> 846 <field name="LEFT_SHIFT" low="35" high="36" type="uint"/> 847 <pattern low="37" high="38">00</pattern> 848 <field name="SKPHP" pos="39" type="bool" display=".skpHp"/> 849 <field name="LOCAL" pos="40" type="bool" display=".local"/> 850 <pattern low="41" high="41">x</pattern> 851 <field name="DENORM" pos="42" type="bool" display=".denorm"/> 852 853 <field name="LOW_HALF" pos="109" type="bool"/> 854 <field name="HIGH_HALF" pos="120" type="bool"/> 855 856 <derived name="THREAD" type="#thread"> 857 <expr>{HIGH_HALF} << 1 | {LOW_HALF}</expr> 858 </derived> 859 860 <field name="DST_FULL" pos="127" type="bool" display=".hp"/> 861 862 <display> 863 {INSTR_LOAD_STORE} {:align=18}mem{COMPS}, {SRC0}, {SRC1}, {SRC2} 864 </display> 865 866 <override expr="#instruction-has-left-shift"> 867 <display> 868 {INSTR_LOAD_STORE_WITH_LEFT_SHIFT} {:align=18}mem{COMPS}, {SRC0}, {SRC1}, {SRC2} 869 </display> 870 </override> 871 872 <!-- SRC0 --> 873 <pattern pos="43">1</pattern> <!-- SRC0_USE --> 874 <field name="SRC0_REG" low="44" high="52" type="uint"/> 875 <field name="SRC0" low="54" high="63" type="#instruction-src"> 876 <param name="SRC0_REG" as="SRC_REG"/> 877 <param name="SRC0_AMODE" as="SRC_AMODE"/> 878 <param name="SRC0_RGROUP" as="SRC_RGROUP"/> 879 </field> 880 <field name="SRC0_AMODE" pos="64" type="#reg_addressing_mode"/> 881 <field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/> 882 883 <!-- SRC1 --> 884 <pattern pos="70">1</pattern> <!-- SRC1_USE --> 885 <field name="SRC1_REG" low="71" high="79" type="uint"/> 886 <field name="SRC1" low="81" high="90" type="#instruction-src"> 887 <param name="SRC1_REG" as="SRC_REG"/> 888 <param name="SRC1_AMODE" as="SRC_AMODE"/> 889 <param name="SRC1_RGROUP" as="SRC_RGROUP"/> 890 </field> 891 <field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/> 892 <field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/> 893 894 <!-- SRC2 --> 895 <pattern pos="99">1</pattern> <!-- SRC2_USE --> 896 <field name="SRC2_REG" low="100" high="108" type="uint"/> 897 <field name="SRC2" low="110" high="119" type="#instruction-src"> 898 <param name="SRC2_REG" as="SRC_REG"/> 899 <param name="SRC2_AMODE" as="SRC_AMODE"/> 900 <param name="SRC2_RGROUP" as="SRC_RGROUP"/> 901 </field> 902 <field name="SRC2_AMODE" low="121" high="123" type="#reg_addressing_mode"/> 903 <field name="SRC2_RGROUP" low="124" high="126" type="#reg_group"/> 904</bitset> 905 906<!-- opcocdes sorted by opc number --> 907 908<bitset name="nop" extends="#instruction-alu-no-src"> 909 <pattern low="0" high="5">000000</pattern> <!-- OPC --> 910 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 911</bitset> 912 913<bitset name="add" extends="#instruction-alu-src0-src2"> 914 <pattern low="0" high="5">000001</pattern> <!-- OPC --> 915 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 916</bitset> 917 918<bitset name="mad" extends="#instruction-alu-src0-src1-src2"> 919 <pattern low="0" high="5">000010</pattern> <!-- OPC --> 920 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 921</bitset> 922 923<bitset name="mul" extends="#instruction-alu-src0-src1"> 924 <pattern low="0" high="5">000011</pattern> <!-- OPC --> 925 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 926</bitset> 927 928<!-- dst --> 929 930<bitset name="dp2" extends="#instruction-alu-src0-src1"> 931 <pattern low="0" high="5">000100</pattern> <!-- OPC --> 932 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 933</bitset> 934 935<bitset name="dp3" extends="#instruction-alu-src0-src1"> 936 <pattern low="0" high="5">000101</pattern> <!-- OPC --> 937 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 938</bitset> 939 940<bitset name="dp4" extends="#instruction-alu-src0-src1"> 941 <pattern low="0" high="5">000110</pattern> <!-- OPC --> 942 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 943</bitset> 944 945<!-- dsx --> 946<!-- dsy --> 947 948<bitset name="mov" extends="#instruction-alu-src2"> 949 <pattern low="0" high="5">001001</pattern> <!-- OPC --> 950 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 951</bitset> 952 953<!-- movar --> 954<!-- movaf --> 955 956<bitset name="rcp" extends="#instruction-alu-src2"> 957 <pattern low="0" high="5">001100</pattern> <!-- OPC --> 958 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 959</bitset> 960 961<bitset name="rsq" extends="#instruction-alu-src2"> 962 <pattern low="0" high="5">001101</pattern> <!-- OPC --> 963 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 964</bitset> 965 966<!-- litp --> 967 968<bitset name="select" extends="#instruction-alu-src0-src1-src2"> 969 <pattern low="0" high="5">001111</pattern> <!-- OPC --> 970 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 971</bitset> 972 973<bitset name="set" extends="#instruction-alu-src0-src1"> 974 <pattern low="0" high="5">010000</pattern> <!-- OPC --> 975 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 976</bitset> 977 978<bitset name="exp" extends="#instruction-alu-src2"> 979 <pattern low="0" high="5">010001</pattern> <!-- OPC --> 980 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 981</bitset> 982 983<bitset name="log" extends="#instruction-alu-src2"> 984 <pattern low="0" high="5">010010</pattern> <!-- OPC --> 985 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 986</bitset> 987 988<!-- frc --> 989 990<bitset name="call" extends="#instruction-cf-no-src"> 991 <pattern low="0" high="5">010100</pattern> <!-- OPC --> 992 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 993</bitset> 994 995<bitset name="ret" extends="#instruction-alu-no-src"> 996 <pattern low="0" high="5">010101</pattern> <!-- OPC --> 997 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 998</bitset> 999 1000<bitset name="branch" extends="#instruction-cf-no-src"> 1001 <pattern low="0" high="5">010110</pattern> <!-- OPC --> 1002 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1003</bitset> 1004 1005<bitset name="branch_if" extends="#instruction-cf-src1-src2" displayname="branch"> 1006 <pattern low="0" high="5">010110</pattern> <!-- OPC --> 1007 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1008</bitset> 1009 1010<bitset name="texkill" extends="#instruction-alu-no-dst-maybe-src1-src2"> 1011 <pattern low="0" high="5">010111</pattern> <!-- OPC --> 1012 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1013</bitset> 1014 1015<bitset name="texld" extends="#instruction-tex-src0"> 1016 <pattern low="0" high="5">011000</pattern> <!-- OPC --> 1017 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1018</bitset> 1019 1020 1021<!-- 0x7800000f 0x9011007c 0x00200804 0x0100100c --> 1022 1023<!-- texldd --> 1024<!-- texldl --> 1025<!-- texldpcf --> 1026<!-- rep --> 1027<!-- endrep --> 1028<!-- loop --> 1029<!-- endloop --> 1030 1031<bitset name="sqrt" extends="#instruction-alu-src2"> 1032 <pattern low="0" high="5">100001</pattern> <!-- OPC --> 1033 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1034</bitset> 1035 1036<bitset name="sin" extends="#instruction-alu-src2"> 1037 <pattern low="0" high="5">100010</pattern> <!-- OPC --> 1038 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1039</bitset> 1040 1041<bitset name="cos" extends="#instruction-alu-src2"> 1042 <pattern low="0" high="5">100011</pattern> <!-- OPC --> 1043 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1044</bitset> 1045 1046<!-- branch2 --> 1047 1048<bitset name="floor" extends="#instruction-alu-src2"> 1049 <pattern low="0" high="5">100101</pattern> <!-- OPC --> 1050 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1051</bitset> 1052 1053<bitset name="ceil" extends="#instruction-alu-src2"> 1054 <pattern low="0" high="5">100110</pattern> <!-- OPC --> 1055 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1056</bitset> 1057 1058<bitset name="sign" extends="#instruction-alu-src2"> 1059 <pattern low="0" high="5">100111</pattern> <!-- OPC --> 1060 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1061</bitset> 1062 1063<!-- addlo --> 1064<!-- mullo --> 1065 1066<bitset name="barrier" extends="#instruction-alu-no-src"> 1067 <pattern low="0" high="5">101010</pattern> <!-- OPC --> 1068 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1069</bitset> 1070 1071<!-- swizzle --> 1072 1073<bitset name="i2i" extends="#instruction-alu-src0-src1"> 1074 <pattern low="0" high="5">101100</pattern> <!-- OPC --> 1075 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1076</bitset> 1077 1078<bitset name="i2f" extends="#instruction-alu-src0"> 1079 <pattern low="0" high="5">101101</pattern> <!-- OPC --> 1080 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1081</bitset> 1082 1083<bitset name="f2i" extends="#instruction-alu-src0"> 1084 <pattern low="0" high="5">101110</pattern> <!-- OPC --> 1085 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1086</bitset> 1087 1088<bitset name="f2irnd" extends="#instruction-alu-src0"> 1089 <pattern low="0" high="5">101111</pattern> <!-- OPC --> 1090 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1091</bitset> 1092 1093<!-- f2i7 --> 1094 1095<bitset name="cmp" extends="#instruction-alu-src0-src1-src2"> 1096 <pattern low="0" high="5">110001</pattern> <!-- OPC --> 1097 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1098</bitset> 1099 1100<bitset name="load" extends="#instruction-load"> 1101 <pattern low="0" high="5">110010</pattern> <!-- OPC --> 1102 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1103</bitset> 1104 1105<bitset name="store" extends="#instruction-store"> 1106 <pattern low="0" high="5">110011</pattern> <!-- OPC --> 1107 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1108</bitset> 1109 1110<bitset name="iaddsat" extends="#instruction-alu-src0-src2"> 1111 <pattern low="0" high="5">111011</pattern> <!-- OPC --> 1112 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1113</bitset> 1114 1115<bitset name="imullo0" extends="#instruction-alu-src0-src1"> 1116 <pattern low="0" high="5">111100</pattern> <!-- OPC --> 1117 <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> 1118</bitset> 1119 1120<!-- imullo1 --> 1121<!-- imullosat0 --> 1122<!-- imullosat1 --> 1123 1124<bitset name="imulhi0" extends="#instruction-alu-src0-src1"> 1125 <pattern low="0" high="5">000000</pattern> <!-- OPC --> 1126 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1127</bitset> 1128 1129<!-- imulhi1 --> 1130 1131<bitset name="idiv0" extends="#instruction-alu-src0-src1"> 1132 <pattern low="0" high="5">000100</pattern> <!-- OPC --> 1133 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1134</bitset> 1135 1136<bitset name="imod" extends="#instruction-alu-src0-src1"> 1137 <pattern low="0" high="5">001000</pattern> <!-- OPC --> 1138 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1139</bitset> 1140 1141<bitset name="imadlo0" extends="#instruction-alu-src0-src1-src2"> 1142 <pattern low="0" high="5">001100</pattern> <!-- OPC --> 1143 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1144</bitset> 1145 1146<bitset name="imadlosat0" extends="#instruction-alu-src0-src1-src2"> 1147 <pattern low="0" high="5">001110</pattern> <!-- OPC --> 1148 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1149</bitset> 1150 1151<bitset name="or" extends="#instruction-alu-src0-src2"> 1152 <pattern low="0" high="5">011100</pattern> <!-- OPC --> 1153 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1154</bitset> 1155 1156<bitset name="and" extends="#instruction-alu-src0-src2"> 1157 <pattern low="0" high="5">011101</pattern> <!-- OPC --> 1158 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1159</bitset> 1160 1161<bitset name="xor" extends="#instruction-alu-src0-src2"> 1162 <pattern low="0" high="5">011110</pattern> <!-- OPC --> 1163 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1164</bitset> 1165 1166<bitset name="not" extends="#instruction-alu-src2"> 1167 <pattern low="0" high="5">011111</pattern> <!-- OPC --> 1168 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1169</bitset> 1170 1171<bitset name="popcount" extends="#instruction-alu-src2"> 1172 <pattern low="0" high="5">100001</pattern> <!-- OPC --> 1173 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1174</bitset> 1175 1176<bitset name="iabs" extends="#instruction-alu-src2"> 1177 <pattern low="0" high="5">010111</pattern> <!-- OPC --> 1178 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1179</bitset> 1180 1181<bitset name="leadzero" extends="#instruction-alu-src2"> 1182 <pattern low="0" high="5">011000</pattern> <!-- OPC --> 1183 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1184</bitset> 1185 1186<bitset name="lshift" extends="#instruction-alu-src0-src2"> 1187 <pattern low="0" high="5">011001</pattern> <!-- OPC --> 1188 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1189</bitset> 1190 1191<bitset name="rshift" extends="#instruction-alu-src0-src2"> 1192 <pattern low="0" high="5">011010</pattern> <!-- OPC --> 1193 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1194</bitset> 1195 1196<bitset name="rotate" extends="#instruction-alu-src0-src2"> 1197 <pattern low="0" high="5">011011</pattern> <!-- OPC --> 1198 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1199</bitset> 1200 1201<bitset name="atomic_add" extends="#instruction-alu-atomic"> 1202 <pattern low="0" high="5">100101</pattern> <!-- OPC --> 1203 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1204</bitset> 1205 1206<bitset name="atomic_xchg" extends="#instruction-alu-atomic"> 1207 <pattern low="0" high="5">100110</pattern> <!-- OPC --> 1208 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1209</bitset> 1210 1211<bitset name="atomic_cmp_xchg" extends="#instruction-alu-atomic"> 1212 <pattern low="0" high="5">100111</pattern> <!-- OPC --> 1213 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1214</bitset> 1215 1216<bitset name="atomic_min" extends="#instruction-alu-atomic"> 1217 <pattern low="0" high="5">101000</pattern> <!-- OPC --> 1218 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1219</bitset> 1220 1221<bitset name="atomic_max" extends="#instruction-alu-atomic"> 1222 <pattern low="0" high="5">101001</pattern> <!-- OPC --> 1223 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1224</bitset> 1225 1226<bitset name="atomic_or" extends="#instruction-alu-atomic"> 1227 <pattern low="0" high="5">101010</pattern> <!-- OPC --> 1228 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1229</bitset> 1230 1231<bitset name="atomic_and" extends="#instruction-alu-atomic"> 1232 <pattern low="0" high="5">101011</pattern> <!-- OPC --> 1233 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1234</bitset> 1235 1236<bitset name="atomic_xor" extends="#instruction-alu-atomic"> 1237 <pattern low="0" high="5">101100</pattern> <!-- OPC --> 1238 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1239</bitset> 1240 1241<bitset name="texldlpcf" extends="#instruction-tex-src0-src1-src2"> 1242 <pattern low="0" high="5">101111</pattern> <!-- OPC --> 1243 <pattern pos="80">1</pattern> <!-- OPCODE_BIT6 --> 1244</bitset> 1245 1246</isa> 1247