1; a6xx microcode 2; Version: 01000001 3 4[01000001] 5[01000081] 6mov $01, 0x830 ; CP_SQE_INSTR_BASE 7mov $02, 0x2 8cwrite $01, [$00 + @REG_READ_ADDR] 9cwrite $02, [$00 + @REG_READ_DWORDS] 10mov $01, $regdata 11mov $02, $regdata 12add $01, $01, 0x4 13addhi $02, $02, 0x0 14mov $03, 0x1 15cwrite $01, [$00 + @MEM_READ_ADDR] 16cwrite $02, [$00 + @MEM_READ_ADDR+0x1] 17cwrite $03, [$00 + @MEM_READ_DWORDS] 18rot $04, $memdata, 0x8 19ushr $04, $04, 0x6 20sub $04, $04, 0x4 21add $01, $01, $04 22addhi $02, $02, 0x0 23mov $rem, 0x80 24cwrite $01, [$00 + @MEM_READ_ADDR] 25cwrite $02, [$00 + @MEM_READ_ADDR+0x1] 26cwrite $02, [$00 + @LOAD_STORE_HI] 27cwrite $rem, [$00 + @MEM_READ_DWORDS] 28cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR] 29(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE] 30mov $02, 0x883 ; CP_SCRATCH[0].REG 31mov $03, 0xbeef 32mov $04, 0xdead << 16 33or $03, $03, $04 34cwrite $02, [$00 + @REG_WRITE_ADDR] 35cwrite $03, [$00 + @REG_WRITE] 36waitin 37mov $01, $data 38 39CP_ME_INIT: 40mov $02, 0x2 41waitin 42mov $01, $data 43 44CP_MEM_WRITE: 45mov $addr, 0xa0 << 24 ; |NRT_ADDR 46mov $02, 0x4 47(xmov1)add $data, $02, $data 48mov $addr, 0xa204 << 16 ; |NRT_DATA 49(rep)(xmov3)mov $data, $data 50waitin 51mov $01, $data 52 53CP_SCRATCH_WRITE: 54mov $02, 0xff 55(rep)cwrite $data, [$02 + 0x1]! 56waitin 57mov $01, $data 58 59CP_SET_DRAW_STATE: 60(rep)(sds2)cwrite $data, [$00 + @DRAW_STATE_SET_HDR] 61waitin 62mov $01, $data 63 64CP_SET_BIN_DATA5: 65sread $02, [$00 + %SP] 66swrite $02, [$00 + %SP] 67mov $02, 0x7 68(rep)swrite $data, [$02 + 0x1]! 69waitin 70mov $01, $data 71 72CP_SET_SECURE_MODE: 73mov $02, $data 74setsecure $02, #l61 75l59: 76jump #l59 77nop 78l61: 79waitin 80mov $01, $data 81 82fxn63: 83l63: 84cmp $04, $02, $03 85breq $04, b0, #l70 86brne $04, b1, #l68 87breq $04, b2, #l63 88sub $03, $03, $02 89l68: 90jump #l63 91sub $02, $02, $03 92l70: 93ret 94nop 95 96CP_REG_RMW: 97cwrite $data, [$00 + @REG_READ_ADDR] 98add $02, $regdata, 0x42 99addhi $03, $00, $regdata 100sub $02, $02, $regdata 101call #fxn63 102subhi $03, $03, $regdata 103and $02, $02, $regdata 104or $02, $02, 0x1 105xor $02, $02, 0x1 106not $02, $02 107shl $02, $02, $regdata 108ushr $02, $02, $regdata 109ishr $02, $02, $regdata 110rot $02, $02, $regdata 111min $02, $02, $regdata 112max $02, $02, $regdata 113mul8 $02, $02, $regdata 114msb $02, $02 115mov $usraddr, $data 116mov $data, $02 117waitin 118mov $01, $data 119 120CP_MEMCPY: 121mov $02, $data 122mov $03, $data 123mov $04, $data 124mov $05, $data 125mov $06, $data 126l99: 127breq $06, 0x0, #l105 128cwrite $03, [$00 + @LOAD_STORE_HI] 129load $07, [$02 + 0x4]! 130cwrite $05, [$00 + @LOAD_STORE_HI] 131jump #l99 132store $07, [$04 + 0x4]! 133l105: 134waitin 135mov $01, $data 136 137CP_MEM_TO_MEM: 138cwrite $data, [$00 + @MEM_READ_ADDR] 139cwrite $data, [$00 + @MEM_READ_ADDR+0x1] 140mov $02, $data 141cwrite $data, [$00 + @LOAD_STORE_HI] 142mov $rem, $data 143cwrite $rem, [$00 + @MEM_READ_DWORDS] 144(rep)store $memdata, [$02 + 0x4]! 145waitin 146mov $01, $data 147 148IN_PREEMPT: 149cread $02, [$00 + 0x101] 150brne $02, 0x1, #l125 151nop 152preemptleave #l59 153nop 154nop 155nop 156waitin 157mov $01, $data 158l125: 159iret 160nop 161 162CP_BLIT: 163CP_BOOTSTRAP_UCODE: 164CP_COND_EXEC: 165CP_COND_INDIRECT_BUFFER_PFE: 166CP_COND_REG_EXEC: 167CP_COND_WRITE5: 168CP_CONTEXT_REG_BUNCH: 169CP_CONTEXT_SWITCH: 170CP_CONTEXT_SWITCH_YIELD: 171CP_CONTEXT_UPDATE: 172CP_DRAW_AUTO: 173CP_DRAW_INDIRECT: 174CP_DRAW_INDIRECT_MULTI: 175CP_DRAW_INDX: 176CP_DRAW_INDX_INDIRECT: 177CP_DRAW_INDX_OFFSET: 178CP_DRAW_PRED_ENABLE_GLOBAL: 179CP_DRAW_PRED_ENABLE_LOCAL: 180CP_DRAW_PRED_SET: 181CP_END_BIN: 182CP_EVENT_WRITE: 183CP_EVENT_WRITE_CFL: 184CP_EVENT_WRITE_SHD: 185CP_EVENT_WRITE_ZPD: 186CP_EXEC_CS: 187CP_EXEC_CS_INDIRECT: 188CP_IM_LOAD: 189CP_IM_LOAD_IMMEDIATE: 190CP_INDIRECT_BUFFER: 191CP_INDIRECT_BUFFER_CHAIN: 192CP_INDIRECT_BUFFER_PFD: 193CP_INTERRUPT: 194CP_INVALIDATE_STATE: 195CP_LOAD_STATE6: 196CP_LOAD_STATE6_FRAG: 197CP_LOAD_STATE6_GEOM: 198CP_MEM_TO_REG: 199CP_MEM_WRITE_CNTR: 200CP_NOP: 201CP_PREEMPT_DISABLE: 202CP_RECORD_PFP_TIMESTAMP: 203CP_REG_TEST: 204CP_REG_TO_MEM: 205CP_REG_TO_MEM_OFFSET_MEM: 206CP_REG_TO_MEM_OFFSET_REG: 207CP_REG_TO_SCRATCH: 208CP_REG_WRITE: 209CP_REG_WR_NO_CTXT: 210CP_RUN_OPENCL: 211CP_SCRATCH_TO_REG: 212CP_SET_BIN_DATA5_OFFSET: 213CP_SET_CTXSWITCH_IB: 214CP_SET_DRAW_INIT_FLAGS: 215CP_SET_MARKER: 216CP_SET_MODE: 217CP_SET_PROTECTED_MODE: 218CP_SET_PSEUDO_REG: 219CP_SET_STATE: 220CP_SET_SUBDRAW_SIZE: 221CP_SET_VISIBILITY_OVERRIDE: 222CP_SKIP_IB2_ENABLE_GLOBAL: 223CP_SKIP_IB2_ENABLE_LOCAL: 224CP_SMMU_TABLE_UPDATE: 225CP_START_BIN: 226CP_TEST_TWO_MEMS: 227CP_WAIT_FOR_IDLE: 228CP_WAIT_FOR_ME: 229CP_WAIT_MEM_GTE: 230CP_WAIT_MEM_WRITES: 231CP_WAIT_REG_EQ: 232CP_WAIT_REG_MEM: 233CP_WAIT_TWO_REGS: 234CP_WHERE_AM_I: 235IN_GMU_INTERRUPT: 236IN_IB_END: 237PKT4: 238UNKN0: 239UNKN1: 240UNKN103: 241UNKN104: 242UNKN105: 243UNKN106: 244UNKN110: 245UNKN118: 246UNKN119: 247UNKN12: 248UNKN121: 249UNKN122: 250UNKN123: 251UNKN124: 252UNKN125: 253UNKN126: 254UNKN127: 255UNKN13: 256UNKN14: 257UNKN2: 258UNKN21: 259UNKN22: 260UNKN23: 261UNKN24: 262UNKN27: 263UNKN28: 264UNKN3: 265UNKN30: 266UNKN31: 267UNKN32: 268UNKN45: 269UNKN48: 270UNKN5: 271UNKN6: 272UNKN7: 273UNKN73: 274UNKN8: 275UNKN9: 276UNKN90: 277UNKN93: 278UNKN96: 279UNKN97: 280waitin 281mov $01, $data 282[0000007f] 283[0000007f] 284[0000007f] 285[0000007f] 286[0000007f] 287[0000007f] 288[0000007f] 289[0000007f] 290[0000007f] 291[0000007f] 292[0000007f] 293[0000007f] 294[0000007f] 295[0000007f] 296[0000007f] 297[00000074] 298[0000007f] 299[0000007f] 300[0000007f] 301[0000007f] 302[0000007f] 303[0000007f] 304[0000007f] 305[0000007f] 306[0000007f] 307[0000007f] 308[0000007f] 309[0000007f] 310[0000007f] 311[0000007f] 312[0000007f] 313[0000007f] 314[0000007f] 315[00000048] 316[0000007f] 317[0000007f] 318[0000007f] 319[0000007f] 320[0000007f] 321[0000007f] 322[0000007f] 323[0000007f] 324[0000007f] 325[0000007f] 326[0000007f] 327[0000007f] 328[0000007f] 329[00000033] 330[0000007f] 331[0000007f] 332[0000007f] 333[0000007f] 334[0000007f] 335[0000007f] 336[0000007f] 337[0000007f] 338[0000007f] 339[0000007f] 340[0000007f] 341[0000007f] 342[0000007f] 343[00000025] 344[0000007f] 345[0000007f] 346[0000007f] 347[0000007f] 348[0000007f] 349[00000030] 350[0000007f] 351[0000007f] 352[0000007f] 353[0000007f] 354[00000022] 355[0000007f] 356[0000007f] 357[0000007f] 358[0000002c] 359[0000007f] 360[0000007f] 361[0000007f] 362[0000007f] 363[0000007f] 364[0000007f] 365[0000007f] 366[0000007f] 367[0000007f] 368[0000007f] 369[0000007f] 370[0000007f] 371[0000007f] 372[0000007f] 373[0000007f] 374[0000007f] 375[0000007f] 376[0000007f] 377[0000007f] 378[0000007f] 379[0000007f] 380[0000007f] 381[0000007f] 382[0000007f] 383[0000007f] 384[00000039] 385[0000007f] 386[0000007f] 387[0000007f] 388[0000007f] 389[0000007f] 390[0000007f] 391[0000007f] 392[0000007f] 393[0000007f] 394[0000007f] 395[0000007f] 396[0000007f] 397[0000006b] 398[0000007f] 399[0000005e] 400[0000007f] 401[0000007f] 402[0000007f] 403[0000007f] 404[0000007f] 405[0000007f] 406[0000007f] 407[0000007f] 408[0000007f] 409[0000007f] 410