1# 2# Copyright © 2021 Google, Inc. 3# 4# Permission is hereby granted, free of charge, to any person obtaining a 5# copy of this software and associated documentation files (the "Software"), 6# to deal in the Software without restriction, including without limitation 7# the rights to use, copy, modify, merge, publish, distribute, sublicense, 8# and/or sell copies of the Software, and to permit persons to whom the 9# Software is furnished to do so, subject to the following conditions: 10# 11# The above copyright notice and this permission notice (including the next 12# paragraph) shall be included in all copies or substantial portions of the 13# Software. 14# 15# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21# IN THE SOFTWARE. 22 23from mako.template import Template 24import sys 25import argparse 26from enum import Enum 27 28def max_bitfield_val(high, low, shift): 29 return ((1 << (high - low)) - 1) << shift 30 31 32parser = argparse.ArgumentParser() 33parser.add_argument('-p', '--import-path', required=True) 34args = parser.parse_args() 35sys.path.insert(0, args.import_path) 36 37from a6xx import * 38 39 40class CHIP(Enum): 41 A2XX = 2 42 A3XX = 3 43 A4XX = 4 44 A5XX = 5 45 A6XX = 6 46 A7XX = 7 47 48class CCUColorCacheFraction(Enum): 49 FULL = 0 50 HALF = 1 51 QUARTER = 2 52 EIGHTH = 3 53 54 55class State(object): 56 def __init__(self): 57 # List of unique device-info structs, multiple different GPU ids 58 # can map to a single info struct in cases where the differences 59 # are not sw visible, or the only differences are parameters 60 # queried from the kernel (like GMEM size) 61 self.gpu_infos = [] 62 63 # Table mapping GPU id to device-info struct 64 self.gpus = {} 65 66 def info_index(self, gpu_info): 67 i = 0 68 for info in self.gpu_infos: 69 if gpu_info == info: 70 return i 71 i += 1 72 raise Error("invalid info") 73 74s = State() 75 76def add_gpus(ids, info): 77 for id in ids: 78 s.gpus[id] = info 79 80class GPUId(object): 81 def __init__(self, gpu_id = None, chip_id = None, name=None): 82 if chip_id == None: 83 assert(gpu_id != None) 84 val = gpu_id 85 core = int(val / 100) 86 val -= (core * 100); 87 major = int(val / 10); 88 val -= (major * 10) 89 minor = val 90 chip_id = (core << 24) | (major << 16) | (minor << 8) | 0xff 91 self.chip_id = chip_id 92 if gpu_id == None: 93 gpu_id = 0 94 self.gpu_id = gpu_id 95 if name == None: 96 assert(gpu_id != 0) 97 name = "FD%d" % gpu_id 98 self.name = name 99 100class Struct(object): 101 """A helper class that stringifies itself to a 'C' struct initializer 102 """ 103 def __str__(self): 104 s = "{" 105 for name, value in vars(self).items(): 106 s += "." + name + "=" + str(value) + "," 107 return s + "}" 108 109class GPUInfo(Struct): 110 """Base class for any generation of adreno, consists of GMEM layout 111 related parameters 112 113 Note that tile_max_h is normally only constrained by corresponding 114 bitfield size/shift (ie. VSC_BIN_SIZE, or similar), but tile_max_h 115 tends to have lower limits, in which case a comment will describe 116 the bitfield size/shift 117 """ 118 def __init__(self, chip, gmem_align_w, gmem_align_h, 119 tile_align_w, tile_align_h, 120 tile_max_w, tile_max_h, num_vsc_pipes, 121 cs_shared_mem_size, num_sp_cores, wave_granularity, fibers_per_sp): 122 self.chip = chip.value 123 self.gmem_align_w = gmem_align_w 124 self.gmem_align_h = gmem_align_h 125 self.tile_align_w = tile_align_w 126 self.tile_align_h = tile_align_h 127 self.tile_max_w = tile_max_w 128 self.tile_max_h = tile_max_h 129 self.num_vsc_pipes = num_vsc_pipes 130 self.cs_shared_mem_size = cs_shared_mem_size 131 self.num_sp_cores = num_sp_cores 132 self.wave_granularity = wave_granularity 133 self.fibers_per_sp = fibers_per_sp 134 135 s.gpu_infos.append(self) 136 137 138class A6xxGPUInfo(GPUInfo): 139 """The a6xx generation has a lot more parameters, and is broken down 140 into distinct sub-generations. The template parameter avoids 141 duplication of parameters that are unique to the sub-generation. 142 """ 143 def __init__(self, chip, template, num_ccu, 144 tile_align_w, tile_align_h, num_vsc_pipes, 145 cs_shared_mem_size, wave_granularity, fibers_per_sp, 146 magic_regs, raw_magic_regs = None): 147 super().__init__(chip, gmem_align_w = 16, gmem_align_h = 4, 148 tile_align_w = tile_align_w, 149 tile_align_h = tile_align_h, 150 tile_max_w = 1024, # max_bitfield_val(5, 0, 5) 151 tile_max_h = max_bitfield_val(14, 8, 4), 152 num_vsc_pipes = num_vsc_pipes, 153 cs_shared_mem_size = cs_shared_mem_size, 154 num_sp_cores = num_ccu, # The # of SP cores seems to always match # of CCU 155 wave_granularity = wave_granularity, 156 fibers_per_sp = fibers_per_sp) 157 158 self.num_ccu = num_ccu 159 160 self.a6xx = Struct() 161 self.a7xx = Struct() 162 163 self.a6xx.magic = Struct() 164 165 for name, val in magic_regs.items(): 166 setattr(self.a6xx.magic, name, val) 167 168 if raw_magic_regs: 169 self.a6xx.magic_raw = [[int(r[0]), r[1]] for r in raw_magic_regs] 170 171 templates = template if type(template) is list else [template] 172 for template in templates: 173 template.apply_props(self) 174 175 176 def __str__(self): 177 return super(A6xxGPUInfo, self).__str__().replace('[', '{').replace("]", "}") 178 179 180# a2xx is really two sub-generations, a20x and a22x, but we don't currently 181# capture that in the device-info tables 182add_gpus([ 183 GPUId(200), 184 GPUId(201), 185 GPUId(205), 186 GPUId(220), 187 ], GPUInfo( 188 CHIP.A2XX, 189 gmem_align_w = 32, gmem_align_h = 32, 190 tile_align_w = 32, tile_align_h = 32, 191 tile_max_w = 512, 192 tile_max_h = ~0, # TODO 193 num_vsc_pipes = 8, 194 cs_shared_mem_size = 0, 195 num_sp_cores = 0, # TODO 196 wave_granularity = 2, 197 fibers_per_sp = 0, # TODO 198 )) 199 200add_gpus([ 201 GPUId(305), 202 GPUId(307), 203 GPUId(320), 204 GPUId(330), 205 GPUId(chip_id=0x03000512, name="FD305B"), 206 ], GPUInfo( 207 CHIP.A3XX, 208 gmem_align_w = 32, gmem_align_h = 32, 209 tile_align_w = 32, tile_align_h = 32, 210 tile_max_w = 992, # max_bitfield_val(4, 0, 5) 211 tile_max_h = max_bitfield_val(9, 5, 5), 212 num_vsc_pipes = 8, 213 cs_shared_mem_size = 32 * 1024, 214 num_sp_cores = 0, # TODO 215 wave_granularity = 2, 216 fibers_per_sp = 0, # TODO 217 )) 218 219add_gpus([ 220 GPUId(405), 221 GPUId(420), 222 GPUId(430), 223 ], GPUInfo( 224 CHIP.A4XX, 225 gmem_align_w = 32, gmem_align_h = 32, 226 tile_align_w = 32, tile_align_h = 32, 227 tile_max_w = 1024, # max_bitfield_val(4, 0, 5) 228 tile_max_h = max_bitfield_val(9, 5, 5), 229 num_vsc_pipes = 8, 230 cs_shared_mem_size = 32 * 1024, 231 num_sp_cores = 0, # TODO 232 wave_granularity = 2, 233 fibers_per_sp = 0, # TODO 234 )) 235 236add_gpus([ 237 GPUId(506), 238 GPUId(508), 239 GPUId(509), 240 ], GPUInfo( 241 CHIP.A5XX, 242 gmem_align_w = 64, gmem_align_h = 32, 243 tile_align_w = 64, tile_align_h = 32, 244 tile_max_w = 1024, # max_bitfield_val(7, 0, 5) 245 tile_max_h = max_bitfield_val(16, 9, 5), 246 num_vsc_pipes = 16, 247 cs_shared_mem_size = 32 * 1024, 248 num_sp_cores = 1, 249 wave_granularity = 2, 250 fibers_per_sp = 64 * 16, # Lowest number that didn't fault on spillall fs-varying-array-mat4-col-row-rd. 251 )) 252 253add_gpus([ 254 GPUId(510), 255 GPUId(512), 256 ], GPUInfo( 257 CHIP.A5XX, 258 gmem_align_w = 64, gmem_align_h = 32, 259 tile_align_w = 64, tile_align_h = 32, 260 tile_max_w = 1024, # max_bitfield_val(7, 0, 5) 261 tile_max_h = max_bitfield_val(16, 9, 5), 262 num_vsc_pipes = 16, 263 cs_shared_mem_size = 32 * 1024, 264 num_sp_cores = 2, 265 wave_granularity = 2, 266 fibers_per_sp = 64 * 16, # Lowest number that didn't fault on spillall fs-varying-array-mat4-col-row-rd. 267 )) 268 269add_gpus([ 270 GPUId(530), 271 GPUId(540), 272 ], GPUInfo( 273 CHIP.A5XX, 274 gmem_align_w = 64, gmem_align_h = 32, 275 tile_align_w = 64, tile_align_h = 32, 276 tile_max_w = 1024, # max_bitfield_val(7, 0, 5) 277 tile_max_h = max_bitfield_val(16, 9, 5), 278 num_vsc_pipes = 16, 279 cs_shared_mem_size = 32 * 1024, 280 num_sp_cores = 4, 281 wave_granularity = 2, 282 fibers_per_sp = 64 * 16, # Lowest number that didn't fault on spillall fs-varying-array-mat4-col-row-rd. 283 )) 284 285 286class A6XXProps(dict): 287 unique_props = dict() 288 def apply_gen_props(self, gen, gpu_info): 289 for name, val in self.items(): 290 setattr(getattr(gpu_info, gen), name, val) 291 A6XXProps.unique_props[(name, gen)] = val 292 293 def apply_props(self, gpu_info): 294 self.apply_gen_props("a6xx", gpu_info) 295 296 297class A7XXProps(A6XXProps): 298 def apply_props(self, gpu_info): 299 self.apply_gen_props("a7xx", gpu_info) 300 301 302# Props could be modified with env var: 303# FD_DEV_FEATURES=%feature_name%=%value%:%feature_name%=%value%:... 304# e.g. 305# FD_DEV_FEATURES=has_fs_tex_prefetch=0:max_sets=4 306 307a6xx_base = A6XXProps( 308 has_cp_reg_write = True, 309 has_8bpp_ubwc = True, 310 has_gmem_fast_clear = True, 311 has_hw_multiview = True, 312 has_fs_tex_prefetch = True, 313 has_sampler_minmax = True, 314 315 supports_double_threadsize = True, 316 317 sysmem_per_ccu_depth_cache_size = 64 * 1024, 318 sysmem_per_ccu_color_cache_size = 64 * 1024, 319 gmem_ccu_color_cache_fraction = CCUColorCacheFraction.QUARTER.value, 320 321 prim_alloc_threshold = 0x7, 322 vs_max_inputs_count = 32, 323 max_sets = 5, 324 ) 325 326 327# a6xx can be divided into distinct sub-generations, where certain device- 328# info parameters are keyed to the sub-generation. These templates reduce 329# the copypaste 330 331a6xx_gen1_low = A6XXProps( 332 reg_size_vec4 = 48, 333 instr_cache_size = 64, 334 indirect_draw_wfm_quirk = True, 335 depth_bounds_require_depth_test_quirk = True, 336 337 has_gmem_fast_clear = False, 338 has_hw_multiview = False, 339 has_sampler_minmax = False, 340 has_fs_tex_prefetch = False, 341 sysmem_per_ccu_color_cache_size = 8 * 1024, 342 sysmem_per_ccu_depth_cache_size = 8 * 1024, 343 gmem_ccu_color_cache_fraction = CCUColorCacheFraction.HALF.value, 344 vs_max_inputs_count = 16, 345 supports_double_threadsize = False, 346 ) 347 348a6xx_gen1 = A6XXProps( 349 reg_size_vec4 = 96, 350 instr_cache_size = 64, 351 indirect_draw_wfm_quirk = True, 352 depth_bounds_require_depth_test_quirk = True, 353 ) 354 355a6xx_gen2 = A6XXProps( 356 reg_size_vec4 = 96, 357 instr_cache_size = 64, # TODO 358 supports_multiview_mask = True, 359 has_z24uint_s8uint = True, 360 indirect_draw_wfm_quirk = True, 361 depth_bounds_require_depth_test_quirk = True, # TODO: check if true 362 has_dp2acc = False, # TODO: check if true 363 has_8bpp_ubwc = False, 364 ) 365 366a6xx_gen3 = A6XXProps( 367 reg_size_vec4 = 64, 368 # Blob limits it to 128 but we hang with 128 369 instr_cache_size = 127, 370 supports_multiview_mask = True, 371 has_z24uint_s8uint = True, 372 tess_use_shared = True, 373 storage_16bit = True, 374 has_tex_filter_cubic = True, 375 has_separate_chroma_filter = True, 376 has_sample_locations = True, 377 has_8bpp_ubwc = False, 378 has_dp2acc = True, 379 has_lrz_dir_tracking = True, 380 enable_lrz_fast_clear = True, 381 lrz_track_quirk = True, 382 has_per_view_viewport = True, 383 ) 384 385a6xx_gen4 = A6XXProps( 386 reg_size_vec4 = 64, 387 # Blob limits it to 128 but we hang with 128 388 instr_cache_size = 127, 389 supports_multiview_mask = True, 390 has_z24uint_s8uint = True, 391 tess_use_shared = True, 392 storage_16bit = True, 393 has_tex_filter_cubic = True, 394 has_separate_chroma_filter = True, 395 has_sample_locations = True, 396 has_cp_reg_write = False, 397 has_8bpp_ubwc = False, 398 has_lpac = True, 399 has_shading_rate = True, 400 has_getfiberid = True, 401 has_dp2acc = True, 402 has_dp4acc = True, 403 enable_lrz_fast_clear = True, 404 has_lrz_dir_tracking = True, 405 has_per_view_viewport = True, 406 ) 407 408a6xx_a690_quirk = A6XXProps( 409 broken_ds_ubwc_quirk = True, 410 ) 411 412add_gpus([ 413 GPUId(605), # TODO: Test it, based only on libwrapfake dumps 414 GPUId(608), # TODO: Test it, based only on libwrapfake dumps 415 GPUId(610), 416 GPUId(612), # TODO: Test it, based only on libwrapfake dumps 417 ], A6xxGPUInfo( 418 CHIP.A6XX, 419 [a6xx_base, a6xx_gen1_low], 420 num_ccu = 1, 421 tile_align_w = 32, 422 tile_align_h = 16, 423 num_vsc_pipes = 16, 424 cs_shared_mem_size = 16 * 1024, 425 wave_granularity = 1, 426 fibers_per_sp = 128 * 16, 427 magic_regs = dict( 428 PC_POWER_CNTL = 0, 429 TPL1_DBG_ECO_CNTL = 0, 430 GRAS_DBG_ECO_CNTL = 0, 431 SP_CHICKEN_BITS = 0, 432 UCHE_CLIENT_PF = 0x00000004, 433 PC_MODE_CNTL = 0xf, 434 SP_DBG_ECO_CNTL = 0x0, 435 RB_DBG_ECO_CNTL = 0x04100000, 436 RB_DBG_ECO_CNTL_blit = 0x04100000, 437 HLSQ_DBG_ECO_CNTL = 0, 438 RB_UNKNOWN_8E01 = 0x00000001, 439 VPC_DBG_ECO_CNTL = 0x0, 440 UCHE_UNKNOWN_0E12 = 0x10000000, 441 ), 442 )) 443 444add_gpus([ 445 GPUId(615), 446 GPUId(616), 447 GPUId(618), 448 GPUId(619), 449 ], A6xxGPUInfo( 450 CHIP.A6XX, 451 [a6xx_base, a6xx_gen1], 452 num_ccu = 1, 453 tile_align_w = 32, 454 tile_align_h = 32, 455 num_vsc_pipes = 32, 456 cs_shared_mem_size = 32 * 1024, 457 wave_granularity = 2, 458 fibers_per_sp = 128 * 16, 459 magic_regs = dict( 460 PC_POWER_CNTL = 0, 461 TPL1_DBG_ECO_CNTL = 0x00108000, 462 GRAS_DBG_ECO_CNTL = 0x00000880, 463 SP_CHICKEN_BITS = 0x00000430, 464 UCHE_CLIENT_PF = 0x00000004, 465 PC_MODE_CNTL = 0x1f, 466 SP_DBG_ECO_CNTL = 0x0, 467 RB_DBG_ECO_CNTL = 0x04100000, 468 RB_DBG_ECO_CNTL_blit = 0x04100000, 469 HLSQ_DBG_ECO_CNTL = 0x00080000, 470 RB_UNKNOWN_8E01 = 0x00000001, 471 VPC_DBG_ECO_CNTL = 0x0, 472 UCHE_UNKNOWN_0E12 = 0x00000001 473 ) 474 )) 475 476add_gpus([ 477 GPUId(620), 478 ], A6xxGPUInfo( 479 CHIP.A6XX, 480 [a6xx_base, a6xx_gen1], 481 num_ccu = 1, 482 tile_align_w = 32, 483 tile_align_h = 16, 484 num_vsc_pipes = 32, 485 cs_shared_mem_size = 32 * 1024, 486 wave_granularity = 2, 487 fibers_per_sp = 128 * 16, 488 magic_regs = dict( 489 PC_POWER_CNTL = 0, 490 TPL1_DBG_ECO_CNTL = 0x01008000, 491 GRAS_DBG_ECO_CNTL = 0x0, 492 SP_CHICKEN_BITS = 0x00000400, 493 UCHE_CLIENT_PF = 0x00000004, 494 PC_MODE_CNTL = 0x1f, 495 SP_DBG_ECO_CNTL = 0x01000000, 496 RB_DBG_ECO_CNTL = 0x04100000, 497 RB_DBG_ECO_CNTL_blit = 0x04100000, 498 HLSQ_DBG_ECO_CNTL = 0x0, 499 RB_UNKNOWN_8E01 = 0x0, 500 VPC_DBG_ECO_CNTL = 0x02000000, 501 UCHE_UNKNOWN_0E12 = 0x00000001 502 ) 503 )) 504 505add_gpus([ 506 GPUId(630), 507 ], A6xxGPUInfo( 508 CHIP.A6XX, 509 [a6xx_base, a6xx_gen1], 510 num_ccu = 2, 511 tile_align_w = 32, 512 tile_align_h = 16, 513 num_vsc_pipes = 32, 514 cs_shared_mem_size = 32 * 1024, 515 wave_granularity = 2, 516 fibers_per_sp = 128 * 16, 517 magic_regs = dict( 518 PC_POWER_CNTL = 1, 519 TPL1_DBG_ECO_CNTL = 0x00108000, 520 GRAS_DBG_ECO_CNTL = 0x00000880, 521 SP_CHICKEN_BITS = 0x00001430, 522 UCHE_CLIENT_PF = 0x00000004, 523 PC_MODE_CNTL = 0x1f, 524 SP_DBG_ECO_CNTL = 0x0, 525 RB_DBG_ECO_CNTL = 0x04100000, 526 RB_DBG_ECO_CNTL_blit = 0x05100000, 527 HLSQ_DBG_ECO_CNTL = 0x00080000, 528 RB_UNKNOWN_8E01 = 0x00000001, 529 VPC_DBG_ECO_CNTL = 0x0, 530 UCHE_UNKNOWN_0E12 = 0x10000001 531 ) 532 )) 533 534add_gpus([ 535 GPUId(640), 536 ], A6xxGPUInfo( 537 CHIP.A6XX, 538 [a6xx_base, a6xx_gen2], 539 num_ccu = 2, 540 tile_align_w = 32, 541 tile_align_h = 16, 542 num_vsc_pipes = 32, 543 cs_shared_mem_size = 32 * 1024, 544 wave_granularity = 2, 545 fibers_per_sp = 128 * 4 * 16, 546 magic_regs = dict( 547 PC_POWER_CNTL = 1, 548 TPL1_DBG_ECO_CNTL = 0x00008000, 549 GRAS_DBG_ECO_CNTL = 0x0, 550 SP_CHICKEN_BITS = 0x00000420, 551 UCHE_CLIENT_PF = 0x00000004, 552 PC_MODE_CNTL = 0x1f, 553 SP_DBG_ECO_CNTL = 0x0, 554 RB_DBG_ECO_CNTL = 0x04100000, 555 RB_DBG_ECO_CNTL_blit = 0x04100000, 556 HLSQ_DBG_ECO_CNTL = 0x0, 557 RB_UNKNOWN_8E01 = 0x00000001, 558 VPC_DBG_ECO_CNTL = 0x02000000, 559 UCHE_UNKNOWN_0E12 = 0x00000001 560 ) 561 )) 562 563add_gpus([ 564 GPUId(680), 565 ], A6xxGPUInfo( 566 CHIP.A6XX, 567 [a6xx_base, a6xx_gen2], 568 num_ccu = 4, 569 tile_align_w = 64, 570 tile_align_h = 32, 571 num_vsc_pipes = 32, 572 cs_shared_mem_size = 32 * 1024, 573 wave_granularity = 2, 574 fibers_per_sp = 128 * 4 * 16, 575 magic_regs = dict( 576 PC_POWER_CNTL = 3, 577 TPL1_DBG_ECO_CNTL = 0x00108000, 578 GRAS_DBG_ECO_CNTL = 0x0, 579 SP_CHICKEN_BITS = 0x00001430, 580 UCHE_CLIENT_PF = 0x00000004, 581 PC_MODE_CNTL = 0x1f, 582 SP_DBG_ECO_CNTL = 0x0, 583 RB_DBG_ECO_CNTL = 0x04100000, 584 RB_DBG_ECO_CNTL_blit = 0x04100000, 585 HLSQ_DBG_ECO_CNTL = 0x0, 586 RB_UNKNOWN_8E01 = 0x00000001, 587 VPC_DBG_ECO_CNTL = 0x02000000, 588 UCHE_UNKNOWN_0E12 = 0x00000001 589 ) 590 )) 591 592add_gpus([ 593 GPUId(650), 594 ], A6xxGPUInfo( 595 CHIP.A6XX, 596 [a6xx_base, a6xx_gen3], 597 num_ccu = 3, 598 tile_align_w = 96, 599 tile_align_h = 16, 600 num_vsc_pipes = 32, 601 cs_shared_mem_size = 32 * 1024, 602 wave_granularity = 2, 603 fibers_per_sp = 128 * 2 * 16, 604 magic_regs = dict( 605 PC_POWER_CNTL = 2, 606 # this seems to be a chicken bit that fixes cubic filtering: 607 TPL1_DBG_ECO_CNTL = 0x01008000, 608 GRAS_DBG_ECO_CNTL = 0x0, 609 SP_CHICKEN_BITS = 0x00001400, 610 UCHE_CLIENT_PF = 0x00000004, 611 PC_MODE_CNTL = 0x1f, 612 SP_DBG_ECO_CNTL = 0x01000000, 613 RB_DBG_ECO_CNTL = 0x04100000, 614 RB_DBG_ECO_CNTL_blit = 0x04100000, 615 HLSQ_DBG_ECO_CNTL = 0x0, 616 RB_UNKNOWN_8E01 = 0x0, 617 VPC_DBG_ECO_CNTL = 0x02000000, 618 UCHE_UNKNOWN_0E12 = 0x00000001 619 ) 620 )) 621 622add_gpus([ 623 GPUId(chip_id=0x00be06030500, name="Adreno 8c Gen 3"), 624 GPUId(chip_id=0x007506030500, name="Adreno 7c+ Gen 3"), 625 GPUId(chip_id=0x006006030500, name="Adreno 7c+ Gen 3 Lite"), 626 GPUId(chip_id=0x00ac06030500, name="FD643"), # e.g. QCM6490, Fairphone 5 627 # fallback wildcard entry should be last: 628 GPUId(chip_id=0xffff06030500, name="Adreno 7c+ Gen 3"), 629 ], A6xxGPUInfo( 630 CHIP.A6XX, 631 [a6xx_base, a6xx_gen4], 632 num_ccu = 2, 633 tile_align_w = 32, 634 tile_align_h = 16, 635 num_vsc_pipes = 32, 636 cs_shared_mem_size = 32 * 1024, 637 wave_granularity = 2, 638 fibers_per_sp = 128 * 2 * 16, 639 magic_regs = dict( 640 PC_POWER_CNTL = 1, 641 TPL1_DBG_ECO_CNTL = 0x05008000, 642 GRAS_DBG_ECO_CNTL = 0x0, 643 SP_CHICKEN_BITS = 0x00001400, 644 UCHE_CLIENT_PF = 0x00000084, 645 PC_MODE_CNTL = 0x1f, 646 SP_DBG_ECO_CNTL = 0x00000006, 647 RB_DBG_ECO_CNTL = 0x04100000, 648 RB_DBG_ECO_CNTL_blit = 0x04100000, 649 HLSQ_DBG_ECO_CNTL = 0x0, 650 RB_UNKNOWN_8E01 = 0x0, 651 VPC_DBG_ECO_CNTL = 0x02000000, 652 UCHE_UNKNOWN_0E12 = 0x00000001 653 ) 654 )) 655 656add_gpus([ 657 GPUId(660), 658 ], A6xxGPUInfo( 659 CHIP.A6XX, 660 [a6xx_base, a6xx_gen4], 661 num_ccu = 3, 662 tile_align_w = 96, 663 tile_align_h = 16, 664 num_vsc_pipes = 32, 665 cs_shared_mem_size = 32 * 1024, 666 wave_granularity = 2, 667 fibers_per_sp = 128 * 2 * 16, 668 magic_regs = dict( 669 PC_POWER_CNTL = 2, 670 TPL1_DBG_ECO_CNTL = 0x05008000, 671 GRAS_DBG_ECO_CNTL = 0x0, 672 SP_CHICKEN_BITS = 0x00001400, 673 UCHE_CLIENT_PF = 0x00000084, 674 PC_MODE_CNTL = 0x1f, 675 SP_DBG_ECO_CNTL = 0x01000000, 676 RB_DBG_ECO_CNTL = 0x04100000, 677 RB_DBG_ECO_CNTL_blit = 0x04100000, 678 HLSQ_DBG_ECO_CNTL = 0x0, 679 RB_UNKNOWN_8E01 = 0x0, 680 VPC_DBG_ECO_CNTL = 0x02000000, 681 UCHE_UNKNOWN_0E12 = 0x00000001 682 ) 683 )) 684 685add_gpus([ 686 GPUId(chip_id=0x6060201, name="FD644"), 687 ], A6xxGPUInfo( 688 CHIP.A6XX, 689 [a6xx_base, a6xx_gen4], 690 num_ccu = 3, 691 tile_align_w = 96, 692 tile_align_h = 16, 693 num_vsc_pipes = 32, 694 cs_shared_mem_size = 32 * 1024, 695 wave_granularity = 2, 696 fibers_per_sp = 128 * 4 * 16, 697 magic_regs = dict( 698 PC_POWER_CNTL = 2, 699 TPL1_DBG_ECO_CNTL = 0x05008000, 700 GRAS_DBG_ECO_CNTL = 0x0, 701 SP_CHICKEN_BITS = 0x00001400, 702 UCHE_CLIENT_PF = 0x00000084, 703 PC_MODE_CNTL = 0x1f, 704 SP_DBG_ECO_CNTL = 0x6, 705 RB_DBG_ECO_CNTL = 0x04100000, 706 RB_DBG_ECO_CNTL_blit = 0x04100000, 707 HLSQ_DBG_ECO_CNTL = 0x0, 708 RB_UNKNOWN_8E01 = 0x0, 709 VPC_DBG_ECO_CNTL = 0x02000000, 710 UCHE_UNKNOWN_0E12 = 0x00000001 711 ) 712 )) 713 714add_gpus([ 715 GPUId(690), 716 GPUId(chip_id=0xffff06090000, name="FD690"), # Default no-speedbin fallback 717 ], A6xxGPUInfo( 718 CHIP.A6XX, 719 [a6xx_base, a6xx_gen4, a6xx_a690_quirk], 720 num_ccu = 8, 721 tile_align_w = 64, 722 tile_align_h = 32, 723 num_vsc_pipes = 32, 724 cs_shared_mem_size = 32 * 1024, 725 wave_granularity = 2, 726 fibers_per_sp = 128 * 2 * 16, 727 magic_regs = dict( 728 PC_POWER_CNTL = 7, 729 TPL1_DBG_ECO_CNTL = 0x04c00000, 730 GRAS_DBG_ECO_CNTL = 0x0, 731 SP_CHICKEN_BITS = 0x00001400, 732 UCHE_CLIENT_PF = 0x00000084, 733 PC_MODE_CNTL = 0x1f, 734 SP_DBG_ECO_CNTL = 0x1200000, 735 RB_DBG_ECO_CNTL = 0x100000, 736 RB_DBG_ECO_CNTL_blit = 0x00100000, # ??? 737 HLSQ_DBG_ECO_CNTL = 0x0, 738 RB_UNKNOWN_8E01 = 0x0, 739 VPC_DBG_ECO_CNTL = 0x2000400, 740 UCHE_UNKNOWN_0E12 = 0x00000001 741 ), 742 raw_magic_regs = [ 743 [A6XXRegs.REG_A6XX_SP_UNKNOWN_AAF2, 0x00c00000], 744 ], 745 )) 746 747# Based on a6xx_base + a6xx_gen4 748a7xx_base = A6XXProps( 749 has_gmem_fast_clear = True, 750 has_hw_multiview = True, 751 has_fs_tex_prefetch = True, 752 has_sampler_minmax = True, 753 754 supports_double_threadsize = True, 755 756 sysmem_per_ccu_depth_cache_size = 256 * 1024, 757 sysmem_per_ccu_color_cache_size = 64 * 1024, 758 gmem_ccu_color_cache_fraction = CCUColorCacheFraction.EIGHTH.value, 759 760 prim_alloc_threshold = 0x7, 761 vs_max_inputs_count = 32, 762 max_sets = 8, 763 764 reg_size_vec4 = 64, 765 # Blob limits it to 128 but we hang with 128 766 instr_cache_size = 127, 767 supports_multiview_mask = True, 768 has_z24uint_s8uint = True, 769 tess_use_shared = True, 770 storage_16bit = True, 771 has_tex_filter_cubic = True, 772 has_separate_chroma_filter = True, 773 has_sample_locations = True, 774 has_lpac = True, 775 has_shading_rate = True, 776 has_getfiberid = True, 777 has_dp2acc = True, 778 has_dp4acc = True, 779 enable_lrz_fast_clear = True, 780 has_lrz_dir_tracking = True, 781 has_per_view_viewport = True, 782 supports_ibo_ubwc = True, 783 ) 784 785a7xx_725 = A7XXProps( 786 cmdbuf_start_a725_quirk = True, 787 ) 788 789a7xx_730 = A7XXProps() 790 791a7xx_740 = A7XXProps( 792 stsc_duplication_quirk = True, 793 has_event_write_sample_count = True, 794 ubwc_unorm_snorm_int_compatible = True, 795 ) 796 797a7xx_750 = A7XXProps( 798 has_event_write_sample_count = True, 799 load_inline_uniforms_via_preamble_ldgk = True, 800 load_shader_consts_via_preamble = True, 801 has_gmem_vpc_attr_buf = True, 802 sysmem_vpc_attr_buf_size = 0x20000, 803 gmem_vpc_attr_buf_size = 0xc000, 804 ubwc_unorm_snorm_int_compatible = True, 805 ) 806 807a730_magic_regs = dict( 808 TPL1_DBG_ECO_CNTL = 0x1000000, 809 GRAS_DBG_ECO_CNTL = 0x800, 810 SP_CHICKEN_BITS = 0x1440, 811 UCHE_CLIENT_PF = 0x00000084, 812 PC_MODE_CNTL = 0x0000003f, # 0x00001f1f in some tests 813 SP_DBG_ECO_CNTL = 0x10000000, 814 RB_DBG_ECO_CNTL = 0x00000000, 815 RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed? 816 RB_UNKNOWN_8E01 = 0x0, 817 VPC_DBG_ECO_CNTL = 0x02000000, 818 UCHE_UNKNOWN_0E12 = 0x3200000, 819 820 RB_UNKNOWN_8E06 = 0x02080000, 821 ) 822 823a730_raw_magic_regs = [ 824 [A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00840004], 825 [A6XXRegs.REG_A6XX_TPL1_UNKNOWN_B602, 0x00000724], 826 827 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00002400], 828 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00000000], 829 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE0A, 0x00000000], 830 [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000], 831 [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000040], 832 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6C, 0x00008000], 833 [A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x20080000], 834 [A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x21fc7f00], 835 [A6XXRegs.REG_A7XX_VFD_UNKNOWN_A600, 0x00000000], 836 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000], 837 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000], 838 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080], 839 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE73, 0x00000000], 840 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000], 841 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000], 842 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000], 843 [A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000], 844 845 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840], 846 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62], 847 848 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2, 0x00000000], 849 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000], 850 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4, 0x00000000], 851 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4+1, 0x00000000], 852 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6, 0x00000000], 853 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6+1, 0x00000000], 854 855 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000], 856 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_810B, 0x3], 857 858 [A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000], 859 [A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000], 860 [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000], 861 [A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000], 862 863 # Shading rate group 864 [A6XXRegs.REG_A6XX_RB_UNKNOWN_88F4, 0x00000000], 865 [A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AD, 0x00000000], 866 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80F4, 0x00000000], 867 ] 868 869add_gpus([ 870 # These are named as Adreno730v3 or Adreno725v1. 871 GPUId(chip_id=0x07030002, name="FD725"), 872 GPUId(chip_id=0xffff07030002, name="FD725"), 873 ], A6xxGPUInfo( 874 CHIP.A7XX, 875 [a7xx_base, a7xx_725], 876 num_ccu = 4, 877 tile_align_w = 64, 878 tile_align_h = 32, 879 num_vsc_pipes = 32, 880 cs_shared_mem_size = 32 * 1024, 881 wave_granularity = 2, 882 fibers_per_sp = 128 * 2 * 16, 883 magic_regs = a730_magic_regs, 884 raw_magic_regs = a730_raw_magic_regs, 885 )) 886 887add_gpus([ 888 GPUId(chip_id=0x07030001, name="FD730"), # KGSL, no speedbin data 889 GPUId(chip_id=0xffff07030001, name="FD730"), # Default no-speedbin fallback 890 ], A6xxGPUInfo( 891 CHIP.A7XX, 892 [a7xx_base, a7xx_730], 893 num_ccu = 4, 894 tile_align_w = 64, 895 tile_align_h = 32, 896 num_vsc_pipes = 32, 897 cs_shared_mem_size = 32 * 1024, 898 wave_granularity = 2, 899 fibers_per_sp = 128 * 2 * 16, 900 magic_regs = a730_magic_regs, 901 raw_magic_regs = a730_raw_magic_regs, 902 )) 903 904add_gpus([ 905 GPUId(740), # Deprecated, used for dev kernels. 906 GPUId(chip_id=0x43050a01, name="FD740"), # KGSL, no speedbin data 907 GPUId(chip_id=0xffff43050a01, name="FD740"), # Default no-speedbin fallback 908 ], A6xxGPUInfo( 909 CHIP.A7XX, 910 [a7xx_base, a7xx_740], 911 num_ccu = 6, 912 tile_align_w = 64, 913 tile_align_h = 32, 914 num_vsc_pipes = 32, 915 cs_shared_mem_size = 32 * 1024, 916 wave_granularity = 2, 917 fibers_per_sp = 128 * 2 * 16, 918 magic_regs = dict( 919 # PC_POWER_CNTL = 7, 920 TPL1_DBG_ECO_CNTL = 0x11100000, 921 GRAS_DBG_ECO_CNTL = 0x00004800, 922 SP_CHICKEN_BITS = 0x10001400, 923 UCHE_CLIENT_PF = 0x00000084, 924 # Blob uses 0x1f or 0x1f1f, however these values cause vertices 925 # corruption in some tests. 926 PC_MODE_CNTL = 0x0000003f, 927 SP_DBG_ECO_CNTL = 0x10000000, 928 RB_DBG_ECO_CNTL = 0x00000000, 929 RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed? 930 # HLSQ_DBG_ECO_CNTL = 0x0, 931 RB_UNKNOWN_8E01 = 0x0, 932 VPC_DBG_ECO_CNTL = 0x02000000, 933 UCHE_UNKNOWN_0E12 = 0x00000000, 934 935 RB_UNKNOWN_8E06 = 0x02080000, 936 ), 937 raw_magic_regs = [ 938 [A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00040004], 939 [A6XXRegs.REG_A6XX_TPL1_UNKNOWN_B602, 0x00000724], 940 941 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00000400], 942 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00430800], 943 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE0A, 0x00000000], 944 [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000], 945 [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000000], 946 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6C, 0x00000000], 947 [A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000], 948 [A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x21585600], 949 [A6XXRegs.REG_A7XX_VFD_UNKNOWN_A600, 0x00008000], 950 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000], 951 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000], 952 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080], 953 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE73, 0x00000000], 954 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000], 955 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000], 956 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000], 957 [A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000], 958 959 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840], 960 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62], 961 962 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8009, 0x00000000], 963 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800A, 0x00000000], 964 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800B, 0x00000000], 965 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800C, 0x00000000], 966 967 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2, 0x00000000], 968 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000], 969 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4, 0x00000000], 970 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4+1, 0x00000000], 971 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6, 0x00000000], 972 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6+1, 0x00000000], 973 974 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000], 975 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_810B, 0x3], 976 977 [A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000], 978 [A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000], 979 [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000], 980 [A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000], 981 982 # Shading rate group 983 [A6XXRegs.REG_A6XX_RB_UNKNOWN_88F4, 0x00000000], 984 [A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AD, 0x00000000], 985 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80F4, 0x00000000], 986 ], 987 )) 988 989add_gpus([ 990 GPUId(chip_id=0x43051401, name="FD750"), # KGSL, no speedbin data 991 GPUId(chip_id=0xffff43051401, name="FD750"), # Default no-speedbin fallback 992 ], A6xxGPUInfo( 993 CHIP.A7XX, 994 [a7xx_base, a7xx_750], 995 num_ccu = 6, 996 tile_align_w = 96, 997 tile_align_h = 32, 998 num_vsc_pipes = 32, 999 cs_shared_mem_size = 32 * 1024, 1000 wave_granularity = 2, 1001 fibers_per_sp = 128 * 2 * 16, 1002 magic_regs = dict( 1003 TPL1_DBG_ECO_CNTL = 0x11100000, 1004 GRAS_DBG_ECO_CNTL = 0x00004800, 1005 SP_CHICKEN_BITS = 0x10000400, 1006 PC_MODE_CNTL = 0x00003f1f, 1007 SP_DBG_ECO_CNTL = 0x10000000, 1008 RB_DBG_ECO_CNTL = 0x00000001, 1009 RB_DBG_ECO_CNTL_blit = 0x00000001, 1010 RB_UNKNOWN_8E01 = 0x0, 1011 VPC_DBG_ECO_CNTL = 0x02000000, 1012 UCHE_UNKNOWN_0E12 = 0x40000000, 1013 1014 RB_UNKNOWN_8E06 = 0x02082000, 1015 ), 1016 raw_magic_regs = [ 1017 [A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00000000], 1018 [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000], 1019 [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000080], 1020 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00000000], 1021 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00431800], 1022 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE0A, 0x00800000], 1023 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6C, 0x00000000], 1024 [A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000], 1025 [A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x01585600], 1026 [A6XXRegs.REG_A7XX_VFD_UNKNOWN_A600, 0x00008000], 1027 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000], 1028 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000], 1029 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080], 1030 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE73, 0x00000000], 1031 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000], 1032 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000], 1033 [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000], 1034 [A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000], 1035 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840], 1036 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62], 1037 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8009, 0x00000000], 1038 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800A, 0x00000000], 1039 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800B, 0x00000000], 1040 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800C, 0x00000000], 1041 1042 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2, 0x00000000], 1043 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000], 1044 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4, 0x00000000], 1045 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4+1, 0x00000000], 1046 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6, 0x00000000], 1047 [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6+1, 0x00000000], 1048 1049 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000], 1050 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_810B, 0x3], 1051 1052 [A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AC, 0x00000000], 1053 [A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000], 1054 [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000], 1055 [A6XXRegs.REG_A7XX_RB_UNKNOWN_88F5, 0x00000000], 1056 1057 # Shading rate group 1058 [A6XXRegs.REG_A6XX_RB_UNKNOWN_88F4, 0x00000000], 1059 [A6XXRegs.REG_A7XX_HLSQ_UNKNOWN_A9AD, 0x00000000], 1060 [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80F4, 0x00000000], 1061 1062 [0x930a, 0], 1063 [0x960a, 1], 1064 [A6XXRegs.REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL, 0], 1065 [A6XXRegs.REG_A7XX_SP_PS_ALIASED_COMPONENTS, 0], 1066 ], 1067 )) 1068 1069template = """\ 1070/* Copyright (C) 2021 Google, Inc. 1071 * 1072 * Permission is hereby granted, free of charge, to any person obtaining a 1073 * copy of this software and associated documentation files (the "Software"), 1074 * to deal in the Software without restriction, including without limitation 1075 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1076 * and/or sell copies of the Software, and to permit persons to whom the 1077 * Software is furnished to do so, subject to the following conditions: 1078 * 1079 * The above copyright notice and this permission notice (including the next 1080 * paragraph) shall be included in all copies or substantial portions of the 1081 * Software. 1082 * 1083 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1084 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1085 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1086 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1087 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 1088 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 1089 * IN THE SOFTWARE. 1090 */ 1091 1092#include "freedreno_dev_info.h" 1093#include "util/u_debug.h" 1094#include "util/log.h" 1095 1096#include <stdlib.h> 1097 1098/* Map python to C: */ 1099#define True true 1100#define False false 1101 1102%for info in s.gpu_infos: 1103static const struct fd_dev_info __info${s.info_index(info)} = ${str(info)}; 1104%endfor 1105 1106static const struct fd_dev_rec fd_dev_recs[] = { 1107%for id, info in s.gpus.items(): 1108 { {${id.gpu_id}, ${hex(id.chip_id)}}, "${id.name}", &__info${s.info_index(info)} }, 1109%endfor 1110}; 1111 1112void 1113fd_dev_info_apply_dbg_options(struct fd_dev_info *info) 1114{ 1115 const char *env = debug_get_option("FD_DEV_FEATURES", NULL); 1116 if (!env || !*env) 1117 return; 1118 1119 char *features = strdup(env); 1120 char *feature, *feature_end; 1121 feature = strtok_r(features, ":", &feature_end); 1122 while (feature != NULL) { 1123 char *name, *name_end; 1124 name = strtok_r(feature, "=", &name_end); 1125 1126 if (!name) { 1127 mesa_loge("Invalid feature \\"%s\\" in FD_DEV_FEATURES", feature); 1128 exit(1); 1129 } 1130 1131 char *value = strtok_r(NULL, "=", &name_end); 1132 1133 feature = strtok_r(NULL, ":", &feature_end); 1134 1135%for (prop, gen), val in unique_props.items(): 1136 <% 1137 if isinstance(val, bool): 1138 parse_value = "debug_parse_bool_option" 1139 else: 1140 parse_value = "debug_parse_num_option" 1141 %> 1142 if (strcmp(name, "${prop}") == 0) { 1143 info->${gen}.${prop} = ${parse_value}(value, info->${gen}.${prop}); 1144 continue; 1145 } 1146%endfor 1147 1148 mesa_loge("Invalid feature \\"%s\\" in FD_DEV_FEATURES", name); 1149 exit(1); 1150 } 1151 1152 free(features); 1153} 1154""" 1155 1156print(Template(template).render(s=s, unique_props=A6XXProps.unique_props)) 1157 1158