1 /* 2 * Copyright © 2023 Igalia S.L. 3 * SPDX-License-Identifier: MIT 4 */ 5 6 #ifndef __FREEDRENO_GPU_EVENT_H__ 7 #define __FREEDRENO_GPU_EVENT_H__ 8 9 #include "adreno_pm4.xml.h" 10 11 enum fd_gpu_event : uint32_t { 12 FD_WRITE_PRIMITIVE_COUNTS = 0, 13 FD_START_PRIMITIVE_CTRS, 14 FD_STOP_PRIMITIVE_CTRS, 15 FD_START_FRAGMENT_CTRS, 16 FD_STOP_FRAGMENT_CTRS, 17 FD_START_COMPUTE_CTRS, 18 FD_STOP_COMPUTE_CTRS, 19 FD_ZPASS_DONE, 20 FD_RB_DONE, 21 FD_FLUSH_SO_0, 22 FD_FLUSH_SO_1, 23 FD_FLUSH_SO_2, 24 FD_FLUSH_SO_3, 25 FD_CACHE_FLUSH, 26 FD_CACHE_INVALIDATE, 27 FD_CCU_INVALIDATE_DEPTH, 28 FD_CCU_INVALIDATE_COLOR, 29 FD_CCU_FLUSH_BLIT_CACHE, 30 FD_CCU_FLUSH_DEPTH, 31 FD_CCU_FLUSH_COLOR, 32 FD_LRZ_CLEAR, 33 FD_LRZ_FLUSH, 34 FD_BLIT, 35 FD_LABEL, 36 37 FD_GPU_EVENT_MAX, 38 }; 39 40 struct fd_gpu_event_info { 41 enum vgt_event_type raw_event; 42 bool needs_seqno; 43 }; 44 45 template <chip CHIP> 46 constexpr struct fd_gpu_event_info fd_gpu_events[FD_GPU_EVENT_MAX] = {}; 47 48 template <> 49 constexpr inline struct fd_gpu_event_info fd_gpu_events<A6XX>[FD_GPU_EVENT_MAX] = { 50 {WRITE_PRIMITIVE_COUNTS, false}, /* FD_WRITE_PRIMITIVE_COUNTS */ 51 {START_PRIMITIVE_CTRS, false}, /* FD_START_PRIMITIVE_CTRS */ 52 {STOP_PRIMITIVE_CTRS, false}, /* FD_STOP_PRIMITIVE_CTRS */ 53 {START_FRAGMENT_CTRS, false}, /* FD_START_FRAGMENT_CTRS */ 54 {STOP_FRAGMENT_CTRS, false}, /* FD_STOP_FRAGMENT_CTRS */ 55 {START_COMPUTE_CTRS, false}, /* FD_START_COMPUTE_CTRS */ 56 {STOP_COMPUTE_CTRS, false}, /* FD_STOP_COMPUTE_CTRS */ 57 {ZPASS_DONE, false}, /* FD_ZPASS_DONE */ 58 {RB_DONE_TS, true}, /* FD_RB_DONE */ 59 {FLUSH_SO_0, false}, /* FD_FLUSH_SO_0 */ 60 {FLUSH_SO_1, false}, /* FD_FLUSH_SO_1 */ 61 {FLUSH_SO_2, false}, /* FD_FLUSH_SO_2 */ 62 {FLUSH_SO_3, false}, /* FD_FLUSH_SO_3 */ 63 {CACHE_FLUSH_TS, true}, /* FD_CACHE_FLUSH */ 64 {CACHE_INVALIDATE, false}, /* FD_CACHE_INVALIDATE */ 65 {PC_CCU_INVALIDATE_DEPTH, false}, /* FD_CCU_INVALIDATE_DEPTH */ 66 {PC_CCU_INVALIDATE_COLOR, false}, /* FD_CCU_INVALIDATE_COLOR */ 67 {PC_CCU_RESOLVE_TS, true}, /* FD_CCU_FLUSH_BLIT_CACHE */ 68 {PC_CCU_FLUSH_DEPTH_TS, true}, /* FD_CCU_FLUSH_DEPTH */ 69 {PC_CCU_FLUSH_COLOR_TS, true}, /* FD_CCU_FLUSH_COLOR */ 70 {LRZ_CLEAR, false}, /* FD_LRZ_CLEAR */ 71 {LRZ_FLUSH, false}, /* FD_LRZ_FLUSH */ 72 {BLIT, false}, /* FD_BLIT */ 73 {LABEL, false}, /* FD_LABEL */ 74 }; 75 76 template <> 77 constexpr inline struct fd_gpu_event_info fd_gpu_events<A7XX>[FD_GPU_EVENT_MAX] = { 78 {WRITE_PRIMITIVE_COUNTS, false}, /* FD_WRITE_PRIMITIVE_COUNTS */ 79 {START_PRIMITIVE_CTRS, false}, /* FD_START_PRIMITIVE_CTRS */ 80 {STOP_PRIMITIVE_CTRS, false}, /* FD_STOP_PRIMITIVE_CTRS */ 81 {START_FRAGMENT_CTRS, false}, /* FD_START_FRAGMENT_CTRS */ 82 {STOP_FRAGMENT_CTRS, false}, /* FD_STOP_FRAGMENT_CTRS */ 83 {START_COMPUTE_CTRS, false}, /* FD_START_COMPUTE_CTRS */ 84 {STOP_COMPUTE_CTRS, false}, /* FD_STOP_COMPUTE_CTRS */ 85 {ZPASS_DONE, false}, /* FD_ZPASS_DONE */ 86 {RB_DONE_TS, true}, /* FD_RB_DONE */ 87 {FLUSH_SO_0, false}, /* FD_FLUSH_SO_0 */ 88 {FLUSH_SO_1, false}, /* FD_FLUSH_SO_1 */ 89 {FLUSH_SO_2, false}, /* FD_FLUSH_SO_2 */ 90 {FLUSH_SO_3, false}, /* FD_FLUSH_SO_3 */ 91 {CACHE_FLUSH7, false}, /* FD_CACHE_FLUSH */ 92 {CACHE_INVALIDATE7, false}, /* FD_CACHE_INVALIDATE */ 93 {CCU_INVALIDATE_DEPTH, false}, /* FD_CCU_INVALIDATE_DEPTH */ 94 {CCU_INVALIDATE_COLOR, false}, /* FD_CCU_INVALIDATE_COLOR */ 95 {CCU_RESOLVE_CLEAN, false}, /* FD_CCU_FLUSH_BLIT_CACHE */ 96 {CCU_FLUSH_DEPTH, false}, /* FD_CCU_FLUSH_DEPTH */ 97 {CCU_FLUSH_COLOR, false}, /* FD_CCU_FLUSH_COLOR */ 98 {LRZ_CLEAR, false}, /* FD_LRZ_CLEAR */ 99 {LRZ_FLUSH, false}, /* FD_LRZ_FLUSH */ 100 {BLIT, false}, /* FD_BLIT */ 101 {LABEL, false}, /* FD_LABEL */ 102 }; 103 104 #endif