1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <math.h>
28 #include "util/half_float.h"
29 #include "util/u_math.h"
30
31 #include "ir3.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
34
35 #define swap(a, b) \
36 do { \
37 __typeof(a) __tmp = (a); \
38 (a) = (b); \
39 (b) = __tmp; \
40 } while (0)
41
42 /*
43 * Copy Propagate:
44 */
45
46 struct ir3_cp_ctx {
47 struct ir3 *shader;
48 struct ir3_shader_variant *so;
49 bool progress;
50 };
51
52 /* is it a type preserving mov, with ok flags?
53 *
54 * @instr: the mov to consider removing
55 * @dst_instr: the instruction consuming the mov (instr)
56 *
57 * TODO maybe drop allow_flags since this is only false when dst is
58 * NULL (ie. outputs)
59 */
60 static bool
is_eligible_mov(struct ir3_instruction * instr,struct ir3_instruction * dst_instr,bool allow_flags)61 is_eligible_mov(struct ir3_instruction *instr,
62 struct ir3_instruction *dst_instr, bool allow_flags)
63 {
64 if (is_same_type_mov(instr)) {
65 struct ir3_register *dst = instr->dsts[0];
66 struct ir3_register *src = instr->srcs[0];
67 struct ir3_instruction *src_instr = ssa(src);
68
69 /* only if mov src is SSA (not const/immed): */
70 if (!src_instr)
71 return false;
72
73 /* no indirect: */
74 if (dst->flags & IR3_REG_RELATIV)
75 return false;
76 if (src->flags & IR3_REG_RELATIV)
77 return false;
78
79 if (src->flags & IR3_REG_ARRAY)
80 return false;
81
82 if (!allow_flags)
83 if (src->flags & (IR3_REG_FABS | IR3_REG_FNEG | IR3_REG_SABS |
84 IR3_REG_SNEG | IR3_REG_BNOT))
85 return false;
86
87 return true;
88 }
89 return false;
90 }
91
92 /* we can end up with extra cmps.s from frontend, which uses a
93 *
94 * cmps.s p0.x, cond, 0
95 *
96 * as a way to mov into the predicate register. But frequently 'cond'
97 * is itself a cmps.s/cmps.f/cmps.u. So detect this special case.
98 */
99 static bool
is_foldable_double_cmp(struct ir3_instruction * cmp)100 is_foldable_double_cmp(struct ir3_instruction *cmp)
101 {
102 struct ir3_instruction *cond = ssa(cmp->srcs[0]);
103 return (cmp->dsts[0]->num == regid(REG_P0, 0)) && cond &&
104 (cmp->srcs[1]->flags & IR3_REG_IMMED) &&
105 (cmp->srcs[1]->iim_val == 0) &&
106 (cmp->cat2.condition == IR3_COND_NE) &&
107 (!cond->address || cond->address->def->instr->block == cmp->block);
108 }
109
110 /* propagate register flags from src to dst.. negates need special
111 * handling to cancel each other out.
112 */
113 static void
combine_flags(unsigned * dstflags,struct ir3_instruction * src)114 combine_flags(unsigned *dstflags, struct ir3_instruction *src)
115 {
116 unsigned srcflags = src->srcs[0]->flags;
117
118 /* if what we are combining into already has (abs) flags,
119 * we can drop (neg) from src:
120 */
121 if (*dstflags & IR3_REG_FABS)
122 srcflags &= ~IR3_REG_FNEG;
123 if (*dstflags & IR3_REG_SABS)
124 srcflags &= ~IR3_REG_SNEG;
125
126 if (srcflags & IR3_REG_FABS)
127 *dstflags |= IR3_REG_FABS;
128 if (srcflags & IR3_REG_SABS)
129 *dstflags |= IR3_REG_SABS;
130 if (srcflags & IR3_REG_FNEG)
131 *dstflags ^= IR3_REG_FNEG;
132 if (srcflags & IR3_REG_SNEG)
133 *dstflags ^= IR3_REG_SNEG;
134 if (srcflags & IR3_REG_BNOT)
135 *dstflags ^= IR3_REG_BNOT;
136
137 *dstflags &= ~IR3_REG_SSA;
138 *dstflags |= srcflags & IR3_REG_SSA;
139 *dstflags |= srcflags & IR3_REG_CONST;
140 *dstflags |= srcflags & IR3_REG_IMMED;
141 *dstflags |= srcflags & IR3_REG_RELATIV;
142 *dstflags |= srcflags & IR3_REG_ARRAY;
143 *dstflags |= srcflags & IR3_REG_SHARED;
144
145 /* if src of the src is boolean we can drop the (abs) since we know
146 * the source value is already a postitive integer. This cleans
147 * up the absnegs that get inserted when converting between nir and
148 * native boolean (see ir3_b2n/n2b)
149 */
150 struct ir3_instruction *srcsrc = ssa(src->srcs[0]);
151 if (srcsrc && is_bool(srcsrc))
152 *dstflags &= ~IR3_REG_SABS;
153 }
154
155 /* Tries lowering an immediate register argument to a const buffer access by
156 * adding to the list of immediates to be pushed to the const buffer when
157 * switching to this shader.
158 */
159 static bool
lower_immed(struct ir3_cp_ctx * ctx,struct ir3_instruction * instr,unsigned n,struct ir3_register * reg,unsigned new_flags)160 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, unsigned n,
161 struct ir3_register *reg, unsigned new_flags)
162 {
163 if (ctx->shader->compiler->load_shader_consts_via_preamble)
164 return false;
165
166 if (!(new_flags & IR3_REG_IMMED))
167 return false;
168
169 new_flags &= ~IR3_REG_IMMED;
170 new_flags |= IR3_REG_CONST;
171
172 if (!ir3_valid_flags(instr, n, new_flags))
173 return false;
174
175 reg = ir3_reg_clone(ctx->shader, reg);
176
177 /* Half constant registers seems to handle only 32-bit values
178 * within floating-point opcodes. So convert back to 32-bit values.
179 */
180 bool f_opcode =
181 (is_cat2_float(instr->opc) || is_cat3_float(instr->opc)) ? true : false;
182 if (f_opcode && (new_flags & IR3_REG_HALF))
183 reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
184
185 /* in some cases, there are restrictions on (abs)/(neg) plus const..
186 * so just evaluate those and clear the flags:
187 */
188 if (new_flags & IR3_REG_SABS) {
189 reg->iim_val = abs(reg->iim_val);
190 new_flags &= ~IR3_REG_SABS;
191 }
192
193 if (new_flags & IR3_REG_FABS) {
194 reg->fim_val = fabs(reg->fim_val);
195 new_flags &= ~IR3_REG_FABS;
196 }
197
198 if (new_flags & IR3_REG_SNEG) {
199 reg->iim_val = -reg->iim_val;
200 new_flags &= ~IR3_REG_SNEG;
201 }
202
203 if (new_flags & IR3_REG_FNEG) {
204 reg->fim_val = -reg->fim_val;
205 new_flags &= ~IR3_REG_FNEG;
206 }
207
208 /* Reallocate for 4 more elements whenever it's necessary. Note that ir3
209 * printing relies on having groups of 4 dwords, so we fill the unused
210 * slots with a dummy value.
211 */
212 struct ir3_const_state *const_state = ir3_const_state(ctx->so);
213 if (const_state->immediates_count == const_state->immediates_size) {
214 const_state->immediates = rerzalloc(
215 const_state, const_state->immediates,
216 __typeof__(const_state->immediates[0]), const_state->immediates_size,
217 const_state->immediates_size + 4);
218 const_state->immediates_size += 4;
219
220 for (int i = const_state->immediates_count;
221 i < const_state->immediates_size; i++)
222 const_state->immediates[i] = 0xd0d0d0d0;
223 }
224
225 int i;
226 for (i = 0; i < const_state->immediates_count; i++) {
227 if (const_state->immediates[i] == reg->uim_val)
228 break;
229 }
230
231 if (i == const_state->immediates_count) {
232 /* Add on a new immediate to be pushed, if we have space left in the
233 * constbuf.
234 */
235 if (const_state->offsets.immediate + const_state->immediates_count / 4 >=
236 ir3_max_const(ctx->so))
237 return false;
238
239 const_state->immediates[i] = reg->uim_val;
240 const_state->immediates_count++;
241 }
242
243 reg->flags = new_flags;
244 reg->num = i + (4 * const_state->offsets.immediate);
245
246 instr->srcs[n] = reg;
247
248 return true;
249 }
250
251 static void
unuse(struct ir3_instruction * instr)252 unuse(struct ir3_instruction *instr)
253 {
254 assert(instr->use_count > 0);
255
256 if (--instr->use_count == 0) {
257 struct ir3_block *block = instr->block;
258
259 instr->barrier_class = 0;
260 instr->barrier_conflict = 0;
261
262 /* we don't want to remove anything in keeps (which could
263 * be things like array store's)
264 */
265 for (unsigned i = 0; i < block->keeps_count; i++) {
266 assert(block->keeps[i] != instr);
267 }
268 }
269 }
270
271 /**
272 * Handles the special case of the 2nd src (n == 1) to "normal" mad
273 * instructions, which cannot reference a constant. See if it is
274 * possible to swap the 1st and 2nd sources.
275 */
276 static bool
try_swap_mad_two_srcs(struct ir3_instruction * instr,unsigned new_flags)277 try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
278 {
279 if (!is_mad(instr->opc))
280 return false;
281
282 /* If we've already tried, nothing more to gain.. we will only
283 * have previously swapped if the original 2nd src was const or
284 * immed. So swapping back won't improve anything and could
285 * result in an infinite "progress" loop.
286 */
287 if (instr->cat3.swapped)
288 return false;
289
290 /* cat3 doesn't encode immediate, but we can lower immediate
291 * to const if that helps:
292 */
293 if (new_flags & IR3_REG_IMMED) {
294 new_flags &= ~IR3_REG_IMMED;
295 new_flags |= IR3_REG_CONST;
296 }
297
298 /* If the reason we couldn't fold without swapping is something
299 * other than const source, then swapping won't help:
300 */
301 if (!(new_flags & IR3_REG_CONST))
302 return false;
303
304 instr->cat3.swapped = true;
305
306 /* NOTE: pre-swap first two src's before valid_flags(),
307 * which might try to dereference the n'th src:
308 */
309 swap(instr->srcs[0], instr->srcs[1]);
310
311 bool valid_swap =
312 /* can we propagate mov if we move 2nd src to first? */
313 ir3_valid_flags(instr, 0, new_flags) &&
314 /* and does first src fit in second slot? */
315 ir3_valid_flags(instr, 1, instr->srcs[1]->flags);
316
317 if (!valid_swap) {
318 /* put things back the way they were: */
319 swap(instr->srcs[0], instr->srcs[1]);
320 } /* otherwise leave things swapped */
321
322 return valid_swap;
323 }
324
325 /* Values that are uniform inside a loop can become divergent outside
326 * it if the loop has a divergent trip count. This means that we can't
327 * propagate a copy of a shared to non-shared register if it would
328 * make the shared reg's live range extend outside of its loop. Users
329 * outside the loop would see the value for the thread(s) that last
330 * exited the loop, rather than for their own thread.
331 */
332 static bool
is_valid_shared_copy(struct ir3_instruction * dst_instr,struct ir3_instruction * src_instr,struct ir3_register * src_reg)333 is_valid_shared_copy(struct ir3_instruction *dst_instr,
334 struct ir3_instruction *src_instr,
335 struct ir3_register *src_reg)
336 {
337 return !(src_reg->flags & IR3_REG_SHARED) ||
338 dst_instr->block->loop_id == src_instr->block->loop_id;
339 }
340
341 /**
342 * Handle cp for a given src register. This additionally handles
343 * the cases of collapsing immedate/const (which replace the src
344 * register with a non-ssa src) or collapsing mov's from relative
345 * src (which needs to also fixup the address src reference by the
346 * instruction).
347 */
348 static bool
reg_cp(struct ir3_cp_ctx * ctx,struct ir3_instruction * instr,struct ir3_register * reg,unsigned n)349 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
350 struct ir3_register *reg, unsigned n)
351 {
352 struct ir3_instruction *src = ssa(reg);
353
354 if (is_eligible_mov(src, instr, true)) {
355 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
356 struct ir3_register *src_reg = src->srcs[0];
357 unsigned new_flags = reg->flags;
358
359 if (!is_valid_shared_copy(instr, src, src_reg))
360 return false;
361
362 combine_flags(&new_flags, src);
363
364 if (ir3_valid_flags(instr, n, new_flags)) {
365 if (new_flags & IR3_REG_ARRAY) {
366 assert(!(reg->flags & IR3_REG_ARRAY));
367 reg->array = src_reg->array;
368 }
369 reg->flags = new_flags;
370 reg->def = src_reg->def;
371
372 instr->barrier_class |= src->barrier_class;
373 instr->barrier_conflict |= src->barrier_conflict;
374
375 unuse(src);
376 reg->def->instr->use_count++;
377
378 return true;
379 }
380 } else if ((is_same_type_mov(src) || is_const_mov(src)) &&
381 /* cannot collapse const/immed/etc into control flow: */
382 opc_cat(instr->opc) != 0) {
383 /* immed/const/etc cases, which require some special handling: */
384 struct ir3_register *src_reg = src->srcs[0];
385 unsigned new_flags = reg->flags;
386
387 if (!is_valid_shared_copy(instr, src, src_reg))
388 return false;
389
390 if (src_reg->flags & IR3_REG_ARRAY)
391 return false;
392
393 combine_flags(&new_flags, src);
394
395 if (!ir3_valid_flags(instr, n, new_flags)) {
396 /* See if lowering an immediate to const would help. */
397 if (lower_immed(ctx, instr, n, src_reg, new_flags))
398 return true;
399
400 /* special case for "normal" mad instructions, we can
401 * try swapping the first two args if that fits better.
402 *
403 * the "plain" MAD's (ie. the ones that don't shift first
404 * src prior to multiply) can swap their first two srcs if
405 * src[0] is !CONST and src[1] is CONST:
406 */
407 if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
408 return true;
409 } else {
410 return false;
411 }
412 }
413
414 /* Here we handle the special case of mov from
415 * CONST and/or RELATIV. These need to be handled
416 * specially, because in the case of move from CONST
417 * there is no src ir3_instruction so we need to
418 * replace the ir3_register. And in the case of
419 * RELATIV we need to handle the address register
420 * dependency.
421 */
422 if (src_reg->flags & IR3_REG_CONST) {
423 /* an instruction cannot reference two different
424 * address registers:
425 */
426 if ((src_reg->flags & IR3_REG_RELATIV) &&
427 conflicts(instr->address, reg->def->instr->address))
428 return false;
429
430 /* These macros expand to a mov in an if statement */
431 if ((src_reg->flags & IR3_REG_RELATIV) &&
432 is_subgroup_cond_mov_macro(instr))
433 return false;
434
435 /* This seems to be a hw bug, or something where the timings
436 * just somehow don't work out. This restriction may only
437 * apply if the first src is also CONST.
438 */
439 if ((opc_cat(instr->opc) == 3) && (n == 2) &&
440 (src_reg->flags & IR3_REG_RELATIV) && (src_reg->array.offset == 0))
441 return false;
442
443 /* When narrowing constant from 32b to 16b, it seems
444 * to work only for float. So we should do this only with
445 * float opcodes.
446 */
447 if (src->cat1.dst_type == TYPE_F16) {
448 /* TODO: should we have a way to tell phi/collect to use a
449 * float move so that this is legal?
450 */
451 if (is_meta(instr))
452 return false;
453 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
454 return false;
455 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
456 return false;
457 } else if (src->cat1.dst_type == TYPE_U16) {
458 /* Since we set CONSTANT_DEMOTION_ENABLE, a float reference of
459 * what was a U16 value read from the constbuf would incorrectly
460 * do 32f->16f conversion, when we want to read a 16f value.
461 */
462 if (is_cat2_float(instr->opc) || is_cat3_float(instr->opc))
463 return false;
464 if (instr->opc == OPC_MOV && type_float(instr->cat1.src_type))
465 return false;
466 }
467
468 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
469 src_reg->flags = new_flags;
470 instr->srcs[n] = src_reg;
471
472 if (src_reg->flags & IR3_REG_RELATIV)
473 ir3_instr_set_address(instr, reg->def->instr->address->def->instr);
474
475 return true;
476 }
477
478 if (src_reg->flags & IR3_REG_IMMED) {
479 int32_t iim_val = src_reg->iim_val;
480
481 assert((opc_cat(instr->opc) == 1) ||
482 (opc_cat(instr->opc) == 2) ||
483 (opc_cat(instr->opc) == 6) ||
484 is_meta(instr) ||
485 (is_mad(instr->opc) && (n == 0)));
486
487 if ((opc_cat(instr->opc) == 2) &&
488 !ir3_cat2_int(instr->opc)) {
489 iim_val = ir3_flut(src_reg);
490 if (iim_val < 0) {
491 /* Fall back to trying to load the immediate as a const: */
492 return lower_immed(ctx, instr, n, src_reg, new_flags);
493 }
494 }
495
496 if (new_flags & IR3_REG_SABS)
497 iim_val = abs(iim_val);
498
499 if (new_flags & IR3_REG_SNEG)
500 iim_val = -iim_val;
501
502 if (new_flags & IR3_REG_BNOT)
503 iim_val = ~iim_val;
504
505 if (ir3_valid_flags(instr, n, new_flags) &&
506 ir3_valid_immediate(instr, iim_val)) {
507 new_flags &= ~(IR3_REG_SABS | IR3_REG_SNEG | IR3_REG_BNOT);
508 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
509 src_reg->flags = new_flags;
510 src_reg->iim_val = iim_val;
511 instr->srcs[n] = src_reg;
512
513 return true;
514 } else {
515 /* Fall back to trying to load the immediate as a const: */
516 return lower_immed(ctx, instr, n, src_reg, new_flags);
517 }
518 }
519 }
520
521 return false;
522 }
523
524 /* Handle special case of eliminating output mov, and similar cases where
525 * there isn't a normal "consuming" instruction. In this case we cannot
526 * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
527 * be eliminated)
528 */
529 static struct ir3_instruction *
eliminate_output_mov(struct ir3_cp_ctx * ctx,struct ir3_instruction * instr)530 eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
531 {
532 if (is_eligible_mov(instr, NULL, false)) {
533 struct ir3_register *reg = instr->srcs[0];
534 if (!(reg->flags & IR3_REG_ARRAY)) {
535 struct ir3_instruction *src_instr = ssa(reg);
536 assert(src_instr);
537 ctx->progress = true;
538 return src_instr;
539 }
540 }
541 return instr;
542 }
543
544 /**
545 * Find instruction src's which are mov's that can be collapsed, replacing
546 * the mov dst with the mov src
547 */
548 static void
instr_cp(struct ir3_cp_ctx * ctx,struct ir3_instruction * instr)549 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
550 {
551 if (instr->srcs_count == 0)
552 return;
553
554 if (ir3_instr_check_mark(instr))
555 return;
556
557 /* walk down the graph from each src: */
558 bool progress;
559 do {
560 progress = false;
561 foreach_src_n (reg, n, instr) {
562 struct ir3_instruction *src = ssa(reg);
563
564 if (!src)
565 continue;
566
567 instr_cp(ctx, src);
568
569 /* TODO non-indirect access we could figure out which register
570 * we actually want and allow cp..
571 */
572 if ((reg->flags & IR3_REG_ARRAY) && src->opc != OPC_META_PHI)
573 continue;
574
575 /* Don't CP absneg into meta instructions, that won't end well: */
576 if (is_meta(instr) &&
577 (src->opc == OPC_ABSNEG_F || src->opc == OPC_ABSNEG_S))
578 continue;
579
580 /* Don't CP mova and mova1 into their users */
581 if (writes_addr0(src) || writes_addr1(src))
582 continue;
583
584 progress |= reg_cp(ctx, instr, reg, n);
585 ctx->progress |= progress;
586 }
587 } while (progress);
588
589 /* After folding a mov's source we may wind up with a type-converting mov
590 * of an immediate. This happens e.g. with texture descriptors, since we
591 * narrow the descriptor (which may be a constant) to a half-reg in ir3.
592 * By converting the immediate in-place to the destination type, we can
593 * turn the mov into a same-type mov so that it can be further propagated.
594 */
595 if (instr->opc == OPC_MOV && (instr->srcs[0]->flags & IR3_REG_IMMED) &&
596 instr->cat1.src_type != instr->cat1.dst_type &&
597 /* Only do uint types for now, until we generate other types of
598 * mov's during instruction selection.
599 */
600 full_type(instr->cat1.src_type) == TYPE_U32 &&
601 full_type(instr->cat1.dst_type) == TYPE_U32) {
602 uint32_t uimm = instr->srcs[0]->uim_val;
603 if (instr->cat1.dst_type == TYPE_U16)
604 uimm &= 0xffff;
605 instr->srcs[0]->uim_val = uimm;
606 if (instr->dsts[0]->flags & IR3_REG_HALF)
607 instr->srcs[0]->flags |= IR3_REG_HALF;
608 else
609 instr->srcs[0]->flags &= ~IR3_REG_HALF;
610 instr->cat1.src_type = instr->cat1.dst_type;
611 ctx->progress = true;
612 }
613
614 /* Re-write the instruction writing predicate register to get rid
615 * of the double cmps.
616 */
617 if ((instr->opc == OPC_CMPS_S) && is_foldable_double_cmp(instr)) {
618 struct ir3_instruction *cond = ssa(instr->srcs[0]);
619 switch (cond->opc) {
620 case OPC_CMPS_S:
621 case OPC_CMPS_F:
622 case OPC_CMPS_U:
623 instr->opc = cond->opc;
624 instr->flags = cond->flags;
625 instr->cat2 = cond->cat2;
626 if (cond->address)
627 ir3_instr_set_address(instr, cond->address->def->instr);
628 instr->srcs[0] = ir3_reg_clone(ctx->shader, cond->srcs[0]);
629 instr->srcs[1] = ir3_reg_clone(ctx->shader, cond->srcs[1]);
630 instr->barrier_class |= cond->barrier_class;
631 instr->barrier_conflict |= cond->barrier_conflict;
632 unuse(cond);
633 ctx->progress = true;
634 break;
635 default:
636 break;
637 }
638 }
639
640 /* Handle converting a sam.s2en (taking samp/tex idx params via register)
641 * into a normal sam (encoding immediate samp/tex idx) if they are
642 * immediate. This saves some instructions and regs in the common case
643 * where we know samp/tex at compile time. This needs to be done in the
644 * frontend for bindless tex, though, so don't replicate it here.
645 */
646 if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
647 !(instr->flags & IR3_INSTR_B) &&
648 !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
649 /* The first src will be a collect, if both of it's
650 * two sources are mov from imm, then we can
651 */
652 struct ir3_instruction *samp_tex = ssa(instr->srcs[0]);
653
654 assert(samp_tex->opc == OPC_META_COLLECT);
655
656 struct ir3_register *samp = samp_tex->srcs[0];
657 struct ir3_register *tex = samp_tex->srcs[1];
658
659 if ((samp->flags & IR3_REG_IMMED) && (tex->flags & IR3_REG_IMMED) &&
660 (samp->iim_val < 16) && (tex->iim_val < 16)) {
661 instr->flags &= ~IR3_INSTR_S2EN;
662 instr->cat5.samp = samp->iim_val;
663 instr->cat5.tex = tex->iim_val;
664
665 /* shuffle around the regs to remove the first src: */
666 instr->srcs_count--;
667 for (unsigned i = 0; i < instr->srcs_count; i++) {
668 instr->srcs[i] = instr->srcs[i + 1];
669 }
670
671 ctx->progress = true;
672 }
673 }
674 }
675
676 bool
ir3_cp(struct ir3 * ir,struct ir3_shader_variant * so)677 ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
678 {
679 struct ir3_cp_ctx ctx = {
680 .shader = ir,
681 .so = so,
682 };
683
684 /* This is a bit annoying, and probably wouldn't be necessary if we
685 * tracked a reverse link from producing instruction to consumer.
686 * But we need to know when we've eliminated the last consumer of
687 * a mov, so we need to do a pass to first count consumers of a
688 * mov.
689 */
690 foreach_block (block, &ir->block_list) {
691 foreach_instr (instr, &block->instr_list) {
692
693 /* by the way, we don't account for false-dep's, so the CP
694 * pass should always happen before false-dep's are inserted
695 */
696 assert(instr->deps_count == 0);
697
698 foreach_ssa_src (src, instr) {
699 src->use_count++;
700 }
701 }
702 }
703
704 ir3_clear_mark(ir);
705
706 foreach_block (block, &ir->block_list) {
707 if (block->condition) {
708 instr_cp(&ctx, block->condition);
709 block->condition = eliminate_output_mov(&ctx, block->condition);
710 }
711
712 for (unsigned i = 0; i < block->keeps_count; i++) {
713 instr_cp(&ctx, block->keeps[i]);
714 block->keeps[i] = eliminate_output_mov(&ctx, block->keeps[i]);
715 }
716 }
717
718 return ctx.progress;
719 }
720