1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 * SPDX-License-Identifier: MIT
5 *
6 * based in part on anv driver which is:
7 * Copyright © 2015 Intel Corporation
8 */
9
10 #ifndef TU_PIPELINE_H
11 #define TU_PIPELINE_H
12
13 #include "tu_common.h"
14
15 #include "tu_cs.h"
16 #include "tu_descriptor_set.h"
17 #include "tu_shader.h"
18 #include "tu_suballoc.h"
19
20 enum tu_dynamic_state
21 {
22 TU_DYNAMIC_STATE_VIEWPORT,
23 TU_DYNAMIC_STATE_SCISSOR,
24 TU_DYNAMIC_STATE_RAST,
25 TU_DYNAMIC_STATE_DEPTH_BIAS,
26 TU_DYNAMIC_STATE_BLEND_CONSTANTS,
27 TU_DYNAMIC_STATE_DS,
28 TU_DYNAMIC_STATE_RB_DEPTH_CNTL,
29 TU_DYNAMIC_STATE_SAMPLE_LOCATIONS,
30 TU_DYNAMIC_STATE_VB_STRIDE,
31 TU_DYNAMIC_STATE_BLEND,
32 TU_DYNAMIC_STATE_VERTEX_INPUT,
33 TU_DYNAMIC_STATE_PATCH_CONTROL_POINTS,
34 TU_DYNAMIC_STATE_COUNT,
35 };
36
37 struct cache_entry;
38
39 struct tu_lrz_blend
40 {
41 bool valid;
42 bool reads_dest;
43 };
44
45 struct tu_bandwidth
46 {
47 uint32_t color_bandwidth_per_sample;
48 uint32_t depth_cpp_per_sample;
49 uint32_t stencil_cpp_per_sample;
50 bool valid;
51 };
52
53 struct tu_nir_shaders
54 {
55 struct vk_pipeline_cache_object base;
56
57 /* This is optional, and is only filled out when a library pipeline is
58 * compiled with RETAIN_LINK_TIME_OPTIMIZATION_INFO.
59 */
60 nir_shader *nir[MESA_SHADER_STAGES];
61 };
62
63 extern const struct vk_pipeline_cache_object_ops tu_nir_shaders_ops;
64
65 static bool inline
tu6_shared_constants_enable(const struct tu_pipeline_layout * layout,const struct ir3_compiler * compiler)66 tu6_shared_constants_enable(const struct tu_pipeline_layout *layout,
67 const struct ir3_compiler *compiler)
68 {
69 return layout->push_constant_size > 0 &&
70 layout->push_constant_size <= (compiler->shared_consts_size * 16);
71 }
72
73 enum ir3_push_consts_type
74 tu_push_consts_type(const struct tu_pipeline_layout *layout,
75 const struct ir3_compiler *compiler);
76
77 struct tu_program_descriptor_linkage
78 {
79 struct ir3_const_state const_state;
80
81 uint32_t constlen;
82
83 struct tu_const_state tu_const_state;
84 };
85
86 struct tu_program_state
87 {
88 struct tu_draw_state config_state;
89 struct tu_draw_state vs_state, vs_binning_state;
90 struct tu_draw_state hs_state;
91 struct tu_draw_state ds_state;
92 struct tu_draw_state gs_state, gs_binning_state;
93 struct tu_draw_state vpc_state;
94 struct tu_draw_state fs_state;
95
96 struct tu_push_constant_range shared_consts;
97
98 struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES];
99
100 unsigned dynamic_descriptor_offsets[MAX_SETS];
101
102 bool per_view_viewport;
103 };
104
105 struct tu_pipeline_executable {
106 gl_shader_stage stage;
107
108 struct ir3_info stats;
109 bool is_binning;
110
111 char *nir_from_spirv;
112 char *nir_final;
113 char *disasm;
114 };
115
116 enum tu_pipeline_type {
117 TU_PIPELINE_GRAPHICS,
118 TU_PIPELINE_GRAPHICS_LIB,
119 TU_PIPELINE_COMPUTE,
120 };
121
122 struct tu_pipeline
123 {
124 struct vk_object_base base;
125 enum tu_pipeline_type type;
126
127 struct tu_cs cs;
128 struct tu_suballoc_bo bo;
129
130 VkShaderStageFlags active_stages;
131 uint32_t active_desc_sets;
132
133 /* mask of enabled dynamic states
134 * if BIT(i) is set, pipeline->dynamic_state[i] is used
135 */
136 uint32_t set_state_mask;
137 struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT];
138
139 struct {
140 bool raster_order_attachment_access;
141 } ds;
142
143 /* Misc. info from the fragment output interface state that is used
144 * elsewhere.
145 */
146 struct {
147 bool raster_order_attachment_access;
148 } output;
149
150 /* In other words - framebuffer fetch support */
151 struct {
152 /* If the pipeline sets SINGLE_PRIM_MODE for sysmem. */
153 bool sysmem_single_prim_mode;
154 struct tu_draw_state state_sysmem, state_gmem;
155 } prim_order;
156
157 /* draw states for the pipeline */
158 struct tu_draw_state load_state;
159
160 struct tu_shader *shaders[MESA_SHADER_STAGES];
161
162 struct tu_program_state program;
163
164 struct tu_lrz_blend lrz_blend;
165 struct tu_bandwidth bandwidth;
166
167 void *executables_mem_ctx;
168 /* tu_pipeline_executable */
169 struct util_dynarray executables;
170 };
171
172 struct tu_graphics_lib_pipeline {
173 struct tu_pipeline base;
174
175 VkGraphicsPipelineLibraryFlagsEXT state;
176
177 struct vk_graphics_pipeline_state graphics_state;
178
179 /* For vk_graphics_pipeline_state */
180 void *state_data;
181
182 struct tu_nir_shaders *nir_shaders;
183 struct {
184 nir_shader *nir;
185 struct tu_shader_key key;
186 } shaders[MESA_SHADER_FRAGMENT + 1];
187
188 /* Used to stitch together an overall layout for the final pipeline. */
189 struct tu_descriptor_set_layout *layouts[MAX_SETS];
190 unsigned num_sets;
191 unsigned push_constant_size;
192 bool independent_sets;
193 };
194
195 struct tu_graphics_pipeline {
196 struct tu_pipeline base;
197
198 struct vk_dynamic_graphics_state dynamic_state;
199
200 /* Only used if the sample locations are static but the enable is dynamic.
201 * Otherwise we should be able to precompile the draw state.
202 */
203 struct vk_sample_locations_state sample_locations;
204
205 bool feedback_loop_color, feedback_loop_ds;
206 bool feedback_loop_may_involve_textures;
207 };
208
209 struct tu_compute_pipeline {
210 struct tu_pipeline base;
211
212 uint32_t local_size[3];
213 uint32_t instrlen;
214 };
215
216 VK_DEFINE_NONDISP_HANDLE_CASTS(tu_pipeline, base, VkPipeline,
217 VK_OBJECT_TYPE_PIPELINE)
218
219 #define TU_DECL_PIPELINE_DOWNCAST(pipe_type, pipe_enum) \
220 static inline struct tu_##pipe_type##_pipeline * \
221 tu_pipeline_to_##pipe_type(struct tu_pipeline *pipeline) \
222 { \
223 assert(pipeline->type == pipe_enum); \
224 return (struct tu_##pipe_type##_pipeline *) pipeline; \
225 }
226
227 TU_DECL_PIPELINE_DOWNCAST(graphics, TU_PIPELINE_GRAPHICS)
228 TU_DECL_PIPELINE_DOWNCAST(graphics_lib, TU_PIPELINE_GRAPHICS_LIB)
229 TU_DECL_PIPELINE_DOWNCAST(compute, TU_PIPELINE_COMPUTE)
230
231 VkOffset2D tu_fdm_per_bin_offset(VkExtent2D frag_area, VkRect2D bin);
232
233 template <chip CHIP>
234 uint32_t tu_emit_draw_state(struct tu_cmd_buffer *cmd);
235
236 struct tu_pvtmem_config {
237 uint64_t iova;
238 uint32_t per_fiber_size;
239 uint32_t per_sp_size;
240 bool per_wave;
241 };
242
243 template <chip CHIP>
244 void
245 tu6_emit_xs_config(struct tu_cs *cs,
246 gl_shader_stage stage,
247 const struct ir3_shader_variant *xs);
248
249 template <chip CHIP>
250 void
251 tu6_emit_shared_consts_enable(struct tu_cs *cs, bool shared_consts_enable);
252
253 template <chip CHIP>
254 void
255 tu6_emit_vpc(struct tu_cs *cs,
256 const struct ir3_shader_variant *vs,
257 const struct ir3_shader_variant *hs,
258 const struct ir3_shader_variant *ds,
259 const struct ir3_shader_variant *gs,
260 const struct ir3_shader_variant *fs);
261
262 void
263 tu_fill_render_pass_state(struct vk_render_pass_state *rp,
264 const struct tu_render_pass *pass,
265 const struct tu_subpass *subpass);
266
267 #endif /* TU_PIPELINE_H */
268