1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_texture.h"
28
29 #include "hw/common.xml.h"
30
31 #include "etnaviv_clear_blit.h"
32 #include "etnaviv_context.h"
33 #include "etnaviv_emit.h"
34 #include "etnaviv_format.h"
35 #include "etnaviv_texture_desc.h"
36 #include "etnaviv_texture_state.h"
37 #include "etnaviv_translate.h"
38 #include "util/u_inlines.h"
39 #include "util/u_memory.h"
40
41 #include "drm-uapi/drm_fourcc.h"
42
43 static void
etna_bind_sampler_states(struct pipe_context * pctx,enum pipe_shader_type shader,unsigned start_slot,unsigned num_samplers,void ** samplers)44 etna_bind_sampler_states(struct pipe_context *pctx, enum pipe_shader_type shader,
45 unsigned start_slot, unsigned num_samplers,
46 void **samplers)
47 {
48 /* bind fragment sampler */
49 struct etna_context *ctx = etna_context(pctx);
50 struct etna_screen *screen = ctx->screen;
51 int offset;
52
53 switch (shader) {
54 case PIPE_SHADER_FRAGMENT:
55 offset = 0;
56 ctx->num_fragment_samplers = num_samplers;
57 break;
58 case PIPE_SHADER_VERTEX:
59 offset = screen->specs.vertex_sampler_offset;
60 break;
61 default:
62 assert(!"Invalid shader");
63 return;
64 }
65
66 uint32_t mask = 1 << offset;
67 for (int idx = 0; idx < num_samplers; ++idx, mask <<= 1) {
68 ctx->sampler[offset + idx] = samplers[idx];
69 if (samplers[idx])
70 ctx->active_samplers |= mask;
71 else
72 ctx->active_samplers &= ~mask;
73 }
74
75 ctx->dirty |= ETNA_DIRTY_SAMPLERS;
76 }
77
78 static bool
etna_configure_sampler_ts(struct etna_sampler_ts * sts,struct pipe_sampler_view * pview,bool enable)79 etna_configure_sampler_ts(struct etna_sampler_ts *sts, struct pipe_sampler_view *pview, bool enable)
80 {
81 bool dirty = (sts->enable != enable);
82
83 assert(sts);
84 sts->enable = enable;
85
86 if (!enable) {
87 sts->TS_SAMPLER_CONFIG = 0;
88 sts->TS_SAMPLER_STATUS_BASE.bo = NULL;
89 return dirty;
90 }
91
92 struct etna_resource *rsc = etna_resource(pview->texture);
93 struct etna_resource_level *lev = &rsc->levels[0];
94
95 if ((lev->clear_value & 0xffffffff) != sts->TS_SAMPLER_CLEAR_VALUE ||
96 (lev->clear_value >> 32) != sts->TS_SAMPLER_CLEAR_VALUE2)
97 dirty = true;
98
99 assert(rsc->ts_bo && etna_resource_level_ts_valid(lev));
100
101 sts->mode = lev->ts_mode;
102 sts->comp = lev->ts_compress_fmt >= 0;
103 sts->TS_SAMPLER_CONFIG =
104 VIVS_TS_SAMPLER_CONFIG_ENABLE |
105 COND(lev->ts_compress_fmt >= 0, VIVS_TS_SAMPLER_CONFIG_COMPRESSION) |
106 VIVS_TS_SAMPLER_CONFIG_COMPRESSION_FORMAT(lev->ts_compress_fmt);
107 sts->TS_SAMPLER_CLEAR_VALUE = lev->clear_value;
108 sts->TS_SAMPLER_CLEAR_VALUE2 = lev->clear_value >> 32;
109 sts->TS_SAMPLER_STATUS_BASE.bo = rsc->ts_bo;
110 sts->TS_SAMPLER_STATUS_BASE.offset = lev->ts_offset;
111 sts->TS_SAMPLER_STATUS_BASE.flags = ETNA_RELOC_READ;
112
113 return dirty;
114 }
115
116 /* Return true if the GPU can use sampler TS with this sampler view.
117 * Sampler TS is an optimization used when rendering to textures, where
118 * a resolve-in-place can be avoided when rendering has left a (valid) TS.
119 */
120 static bool
etna_can_use_sampler_ts(struct pipe_sampler_view * view,int num)121 etna_can_use_sampler_ts(struct pipe_sampler_view *view, int num)
122 {
123 struct etna_resource *rsc = etna_resource(view->texture);
124 struct etna_screen *screen = etna_screen(rsc->base.screen);
125
126 /* Sampler TS can be used under the following conditions: */
127
128 /* The resource TS is valid for level 0. */
129 if (!etna_resource_level_ts_valid(&rsc->levels[0]))
130 return false;
131
132 /* The hardware supports it. */
133 if (!VIV_FEATURE(screen, chipMinorFeatures2, TEXTURE_TILED_READ))
134 return false;
135
136 /* The sampler view will be bound to sampler < VIVS_TS_SAMPLER__LEN.
137 * HALTI5 adds a mapping from sampler to sampler TS unit, but this is AFAIK
138 * absent on earlier models. */
139 if (num >= VIVS_TS_SAMPLER__LEN)
140 return false;
141
142 /* It is a texture, not a buffer. */
143 if (rsc->base.target == PIPE_BUFFER)
144 return false;
145
146 /* Does not use compression or the hardware supports V4 compression. */
147 if (rsc->levels[0].ts_compress_fmt >= 0 && !screen->specs.v4_compression)
148 return false;
149
150 /* The sampler will have one LOD, and it happens to be level 0.
151 * (It is not sure if the hw supports it for other levels, but available
152 * state strongly suggests only one at a time). */
153 if (view->u.tex.first_level != 0 ||
154 MIN2(view->u.tex.last_level, rsc->base.last_level) != 0)
155 return false;
156
157 return true;
158 }
159
160 void
etna_update_sampler_source(struct pipe_sampler_view * view,int num)161 etna_update_sampler_source(struct pipe_sampler_view *view, int num)
162 {
163 struct etna_resource *base = etna_resource(view->texture);
164 struct etna_resource *to = base, *from = base;
165 struct etna_context *ctx = etna_context(view->context);
166 bool enable_sampler_ts = false;
167
168 if (base->shared && !_mesa_set_search(ctx->updated_resources, view->texture)) {
169 for (int i = view->u.tex.first_level; i <= view->u.tex.last_level; i++)
170 etna_resource_level_mark_changed(&base->levels[i]);
171
172 pipe_reference(NULL, &view->texture->reference);
173 _mesa_set_add(ctx->updated_resources, view->texture);
174 }
175
176 if (base->render && etna_resource_newer(etna_resource(base->render), base))
177 from = etna_resource(base->render);
178
179 if (base->texture)
180 to = etna_resource(base->texture);
181
182 if ((to != from) && etna_resource_older(to, from)) {
183 etna_copy_resource(view->context, &to->base, &from->base,
184 view->u.tex.first_level,
185 MIN2(view->texture->last_level, view->u.tex.last_level));
186 ctx->dirty |= ETNA_DIRTY_TEXTURE_CACHES;
187 } else if (to == from) {
188 if (etna_can_use_sampler_ts(view, num)) {
189 enable_sampler_ts = true;
190 } else if (etna_resource_needs_flush(to)) {
191 /* Resolve TS if needed */
192 etna_copy_resource(view->context, &to->base, &from->base,
193 view->u.tex.first_level,
194 MIN2(view->texture->last_level, view->u.tex.last_level));
195 ctx->dirty |= ETNA_DIRTY_TEXTURE_CACHES;
196 }
197 }
198
199 if (etna_configure_sampler_ts(ctx->ts_for_sampler_view(view), view, enable_sampler_ts)) {
200 ctx->dirty |= ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_TEXTURE_CACHES;
201 ctx->dirty_sampler_views |= (1 << num);
202 }
203 }
204
205 static bool
etna_resource_sampler_compatible(struct etna_resource * res)206 etna_resource_sampler_compatible(struct etna_resource *res)
207 {
208 if (util_format_is_compressed(res->base.format))
209 return true;
210
211 struct etna_screen *screen = etna_screen(res->base.screen);
212 /* This GPU supports texturing from supertiled textures? */
213 if (res->layout == ETNA_LAYOUT_SUPER_TILED && VIV_FEATURE(screen, chipMinorFeatures2, SUPERTILED_TEXTURE))
214 return true;
215
216 /* This GPU supports texturing from linear textures? */
217 if (res->layout == ETNA_LAYOUT_LINEAR && VIV_FEATURE(screen, chipMinorFeatures1, LINEAR_TEXTURE_SUPPORT))
218 return true;
219
220 /* Otherwise, only support tiled layouts */
221 if (res->layout != ETNA_LAYOUT_TILED)
222 return false;
223
224 /* If we have HALIGN support, we can allow for the RS padding */
225 if (VIV_FEATURE(screen, chipMinorFeatures1, TEXTURE_HALIGN))
226 return true;
227
228 /* Non-HALIGN GPUs only accept 4x4 tile-aligned textures */
229 if (res->halign != TEXTURE_HALIGN_FOUR)
230 return false;
231
232 return true;
233 }
234
235 struct etna_resource *
etna_texture_handle_incompatible(struct pipe_context * pctx,struct pipe_resource * prsc)236 etna_texture_handle_incompatible(struct pipe_context *pctx, struct pipe_resource *prsc)
237 {
238 struct etna_resource *res = etna_resource(prsc);
239
240 if (!etna_resource_sampler_compatible(res)) {
241 /* The original resource is not compatible with the sampler.
242 * Allocate an appropriately tiled texture. */
243 if (!res->texture) {
244 struct pipe_resource templat = *prsc;
245
246 templat.bind &= ~(PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET |
247 PIPE_BIND_BLENDABLE);
248 res->texture =
249 etna_resource_alloc(pctx->screen, ETNA_LAYOUT_TILED,
250 DRM_FORMAT_MOD_LINEAR, &templat);
251 }
252
253 if (!res->texture) {
254 return NULL;
255 }
256 res = etna_resource(res->texture);
257 }
258 return res;
259 }
260
261 static void
set_sampler_views(struct etna_context * ctx,unsigned start,unsigned end,unsigned nr,bool take_ownership,struct pipe_sampler_view ** views)262 set_sampler_views(struct etna_context *ctx, unsigned start, unsigned end,
263 unsigned nr, bool take_ownership, struct pipe_sampler_view **views)
264 {
265 unsigned i, j;
266 uint32_t mask = 1 << start;
267 uint32_t prev_active_sampler_views = ctx->active_sampler_views;
268
269 for (i = start, j = 0; j < nr; i++, j++, mask <<= 1) {
270 struct pipe_sampler_view *view = views ? views[j] : NULL;
271
272 if (take_ownership) {
273 pipe_sampler_view_reference(&ctx->sampler_view[i], NULL);
274 ctx->sampler_view[i] = view;
275 } else {
276 pipe_sampler_view_reference(&ctx->sampler_view[i], view);
277 }
278 if (view) {
279 ctx->active_sampler_views |= mask;
280 ctx->dirty_sampler_views |= mask;
281 } else
282 ctx->active_sampler_views &= ~mask;
283 }
284
285 for (; i < end; i++, mask <<= 1) {
286 pipe_sampler_view_reference(&ctx->sampler_view[i], NULL);
287 ctx->active_sampler_views &= ~mask;
288 }
289
290 /* sampler views that changed state (even to inactive) are also dirty */
291 ctx->dirty_sampler_views |= ctx->active_sampler_views ^ prev_active_sampler_views;
292 }
293
294 static inline void
etna_fragtex_set_sampler_views(struct etna_context * ctx,unsigned nr,bool take_ownership,struct pipe_sampler_view ** views)295 etna_fragtex_set_sampler_views(struct etna_context *ctx, unsigned nr,
296 bool take_ownership,
297 struct pipe_sampler_view **views)
298 {
299 struct etna_screen *screen = ctx->screen;
300 unsigned start = 0;
301 unsigned end = start + screen->specs.fragment_sampler_count;
302
303 set_sampler_views(ctx, start, end, nr, take_ownership, views);
304 ctx->num_fragment_sampler_views = nr;
305 }
306
307
308 static inline void
etna_vertex_set_sampler_views(struct etna_context * ctx,unsigned nr,bool take_ownership,struct pipe_sampler_view ** views)309 etna_vertex_set_sampler_views(struct etna_context *ctx, unsigned nr,
310 bool take_ownership,
311 struct pipe_sampler_view **views)
312 {
313 struct etna_screen *screen = ctx->screen;
314 unsigned start = screen->specs.vertex_sampler_offset;
315 unsigned end = start + screen->specs.vertex_sampler_count;
316
317 set_sampler_views(ctx, start, end, nr, take_ownership, views);
318 }
319
320 static void
etna_set_sampler_views(struct pipe_context * pctx,enum pipe_shader_type shader,unsigned start_slot,unsigned num_views,unsigned unbind_num_trailing_slots,bool take_ownership,struct pipe_sampler_view ** views)321 etna_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,
322 unsigned start_slot, unsigned num_views,
323 unsigned unbind_num_trailing_slots,
324 bool take_ownership,
325 struct pipe_sampler_view **views)
326 {
327 struct etna_context *ctx = etna_context(pctx);
328 assert(start_slot == 0);
329
330 ctx->dirty |= ETNA_DIRTY_SAMPLER_VIEWS | ETNA_DIRTY_TEXTURE_CACHES;
331
332 switch (shader) {
333 case PIPE_SHADER_FRAGMENT:
334 etna_fragtex_set_sampler_views(ctx, num_views, take_ownership, views);
335 break;
336 case PIPE_SHADER_VERTEX:
337 etna_vertex_set_sampler_views(ctx, num_views, take_ownership, views);
338 break;
339 default:;
340 }
341 }
342
343 static void
etna_texture_barrier(struct pipe_context * pctx,unsigned flags)344 etna_texture_barrier(struct pipe_context *pctx, unsigned flags)
345 {
346 struct etna_context *ctx = etna_context(pctx);
347
348 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
349 VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH |
350 VIVS_GL_FLUSH_CACHE_TEXTURE);
351 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
352 VIVS_GL_FLUSH_CACHE_TEXTUREVS);
353 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
354 }
355
356 uint32_t
active_samplers_bits(struct etna_context * ctx)357 active_samplers_bits(struct etna_context *ctx)
358 {
359 return ctx->active_sampler_views & ctx->active_samplers;
360 }
361
362 void
etna_texture_init(struct pipe_context * pctx)363 etna_texture_init(struct pipe_context *pctx)
364 {
365 struct etna_context *ctx = etna_context(pctx);
366 struct etna_screen *screen = ctx->screen;
367
368 pctx->bind_sampler_states = etna_bind_sampler_states;
369 pctx->set_sampler_views = etna_set_sampler_views;
370 pctx->texture_barrier = etna_texture_barrier;
371
372 if (screen->specs.halti >= 5) {
373 u_suballocator_init(&ctx->tex_desc_allocator, pctx, 4096, 0,
374 PIPE_USAGE_IMMUTABLE, 0, true);
375 etna_texture_desc_init(pctx);
376 } else {
377 etna_texture_state_init(pctx);
378 }
379 }
380
381 void
etna_texture_fini(struct pipe_context * pctx)382 etna_texture_fini(struct pipe_context *pctx)
383 {
384 struct etna_context *ctx = etna_context(pctx);
385 struct etna_screen *screen = ctx->screen;
386
387 if (screen->specs.halti >= 5)
388 u_suballocator_destroy(&ctx->tex_desc_allocator);
389 }
390