1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_memory.h"
29 #include "util/u_prim.h"
30 #include "util/u_string.h"
31
32 #include "freedreno_resource.h"
33 #include "freedreno_state.h"
34
35 #include "fd5_context.h"
36 #include "fd5_draw.h"
37 #include "fd5_emit.h"
38 #include "fd5_format.h"
39 #include "fd5_program.h"
40 #include "fd5_zsa.h"
41
42 static void
draw_impl(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd5_emit * emit,unsigned index_offset)43 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
44 struct fd5_emit *emit, unsigned index_offset) assert_dt
45 {
46 const struct pipe_draw_info *info = emit->info;
47 enum pc_di_primtype primtype = ctx->screen->primtypes[info->mode];
48
49 fd5_emit_state(ctx, ring, emit);
50
51 if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
52 fd5_emit_vertex_bufs(ring, emit);
53
54 OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
55 OUT_RING(ring, info->index_size ? emit->draw->index_bias
56 : emit->draw->start); /* VFD_INDEX_OFFSET */
57 OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */
58
59 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
60 OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
61 info->restart_index
62 : 0xffffffff);
63
64 fd5_emit_render_cntl(ctx, false, emit->binning_pass);
65 fd5_draw_emit(ctx->batch, ring, primtype,
66 emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY, info,
67 emit->indirect, emit->draw, index_offset);
68 }
69
70 static bool
fd5_draw_vbo(struct fd_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draw,unsigned index_offset)71 fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
72 unsigned drawid_offset,
73 const struct pipe_draw_indirect_info *indirect,
74 const struct pipe_draw_start_count_bias *draw,
75 unsigned index_offset) in_dt
76 {
77 struct fd5_emit emit = {
78 .debug = &ctx->debug,
79 .vtx = &ctx->vtx,
80 .info = info,
81 .drawid_offset = drawid_offset,
82 .indirect = indirect,
83 .draw = draw,
84 .key = {
85 .vs = ctx->prog.vs,
86 .fs = ctx->prog.fs,
87 .key = {
88 .rasterflat = ctx->rasterizer->flatshade,
89 },
90 .clip_plane_enable = ctx->rasterizer->clip_plane_enable,
91 },
92 .rasterflat = ctx->rasterizer->flatshade,
93 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
94 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
95 };
96
97 ir3_fixup_shader_state(&ctx->base, &emit.key.key);
98
99 unsigned dirty = ctx->dirty;
100
101 emit.prog = fd5_program_state(
102 ir3_cache_lookup(ctx->shader_cache, &emit.key, &ctx->debug));
103
104 /* bail if compile failed: */
105 if (!emit.prog)
106 return false;
107
108 fd_blend_tracking(ctx);
109
110 const struct ir3_shader_variant *vp = fd5_emit_get_vp(&emit);
111 const struct ir3_shader_variant *fp = fd5_emit_get_fp(&emit);
112
113 ir3_update_max_tf_vtx(ctx, vp);
114
115 /* do regular pass first: */
116
117 if (unlikely(ctx->stats_users > 0)) {
118 ctx->stats.vs_regs += ir3_shader_halfregs(vp);
119 ctx->stats.fs_regs += ir3_shader_halfregs(fp);
120 }
121
122 /* figure out whether we need to disable LRZ write for binning
123 * pass using draw pass's fp:
124 */
125 emit.no_lrz_write = fp->writes_pos || fp->no_earlyz || fp->has_kill;
126
127 emit.binning_pass = false;
128 emit.dirty = dirty;
129
130 draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
131
132 /* and now binning pass: */
133 emit.binning_pass = true;
134 emit.dirty = dirty & ~(FD_DIRTY_BLEND);
135 emit.vs = NULL; /* we changed key so need to refetch vp */
136 emit.fs = NULL;
137 draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
138
139 if (emit.streamout_mask) {
140 struct fd_ringbuffer *ring = ctx->batch->draw;
141
142 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
143 if (emit.streamout_mask & (1 << i)) {
144 fd5_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
145 }
146 }
147 }
148
149 fd_context_all_clean(ctx);
150
151 return true;
152 }
153
154 static void
fd5_draw_vbos(struct fd_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws,unsigned index_offset)155 fd5_draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info,
156 unsigned drawid_offset,
157 const struct pipe_draw_indirect_info *indirect,
158 const struct pipe_draw_start_count_bias *draws,
159 unsigned num_draws,
160 unsigned index_offset)
161 assert_dt
162 {
163 for (unsigned i = 0; i < num_draws; i++)
164 fd5_draw_vbo(ctx, info, drawid_offset, indirect, &draws[i], index_offset);
165 }
166
167 static void
fd5_clear_lrz(struct fd_batch * batch,struct fd_resource * zsbuf,double depth)168 fd5_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
169 {
170 struct fd_ringbuffer *ring;
171 uint32_t clear = util_pack_z(PIPE_FORMAT_Z16_UNORM, depth);
172
173 ring = fd_batch_get_prologue(batch);
174
175 OUT_WFI5(ring);
176
177 OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
178 OUT_RING(ring, 0x10000000);
179
180 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
181 OUT_RING(ring, 0x20fffff);
182
183 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
184 OUT_RING(ring,
185 A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0f) |
186 A5XX_GRAS_SU_CNTL_LINE_MODE(zsbuf->b.b.nr_samples > 1 ?
187 RECTANGULAR : BRESENHAM));
188
189 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
190 OUT_RING(ring, 0x00000000);
191
192 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
193 OUT_RING(ring, 0x00000181);
194
195 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
196 OUT_RING(ring, 0x00000000);
197
198 OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
199 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM) |
200 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) |
201 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
202 OUT_RING(ring, A5XX_RB_MRT_PITCH(zsbuf->lrz_pitch * 2));
203 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf->lrz)));
204 OUT_RELOC(ring, zsbuf->lrz, 0x1000, 0, 0);
205
206 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
207 OUT_RING(ring, 0x00000000);
208
209 OUT_PKT4(ring, REG_A5XX_RB_DEST_MSAA_CNTL, 1);
210 OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE));
211
212 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
213 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0));
214
215 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
216 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(0xf));
217
218 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
219 OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
220
221 OUT_PKT4(ring, REG_A5XX_VSC_RESOLVE_CNTL, 2);
222 OUT_RING(ring, A5XX_VSC_RESOLVE_CNTL_X(zsbuf->lrz_width) |
223 A5XX_VSC_RESOLVE_CNTL_Y(zsbuf->lrz_height));
224 OUT_RING(ring, 0x00000000); // XXX UNKNOWN_0CDE
225
226 OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
227 OUT_RING(ring, A5XX_RB_CNTL_BYPASS);
228
229 OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
230 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) | A5XX_RB_RESOLVE_CNTL_1_Y(0));
231 OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(zsbuf->lrz_width - 1) |
232 A5XX_RB_RESOLVE_CNTL_2_Y(zsbuf->lrz_height - 1));
233
234 fd5_emit_blit(batch, ring);
235 }
236
237 static bool
fd5_clear(struct fd_context * ctx,enum fd_buffer_mask buffers,const union pipe_color_union * color,double depth,unsigned stencil)238 fd5_clear(struct fd_context *ctx, enum fd_buffer_mask buffers,
239 const union pipe_color_union *color, double depth,
240 unsigned stencil) assert_dt
241 {
242 struct fd_ringbuffer *ring = ctx->batch->draw;
243 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
244
245 if ((buffers & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) &&
246 is_z32(pfb->zsbuf->format))
247 return false;
248
249 fd5_emit_render_cntl(ctx, true, false);
250
251 if (buffers & FD_BUFFER_COLOR) {
252 for (int i = 0; i < pfb->nr_cbufs; i++) {
253 union util_color uc = {0};
254
255 if (!pfb->cbufs[i])
256 continue;
257
258 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
259 continue;
260
261 enum pipe_format pfmt = pfb->cbufs[i]->format;
262
263 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
264 union pipe_color_union swapped;
265 switch (fd5_pipe2swap(pfmt)) {
266 case WZYX:
267 swapped.ui[0] = color->ui[0];
268 swapped.ui[1] = color->ui[1];
269 swapped.ui[2] = color->ui[2];
270 swapped.ui[3] = color->ui[3];
271 break;
272 case WXYZ:
273 swapped.ui[2] = color->ui[0];
274 swapped.ui[1] = color->ui[1];
275 swapped.ui[0] = color->ui[2];
276 swapped.ui[3] = color->ui[3];
277 break;
278 case ZYXW:
279 swapped.ui[3] = color->ui[0];
280 swapped.ui[0] = color->ui[1];
281 swapped.ui[1] = color->ui[2];
282 swapped.ui[2] = color->ui[3];
283 break;
284 case XYZW:
285 swapped.ui[3] = color->ui[0];
286 swapped.ui[2] = color->ui[1];
287 swapped.ui[1] = color->ui[2];
288 swapped.ui[0] = color->ui[3];
289 break;
290 }
291
292 util_pack_color_union(pfmt, &uc, &swapped);
293
294 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
295 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0 + i));
296
297 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
298 OUT_RING(ring,
299 A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(0xf));
300
301 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 4);
302 OUT_RING(ring, uc.ui[0]); /* RB_CLEAR_COLOR_DW0 */
303 OUT_RING(ring, uc.ui[1]); /* RB_CLEAR_COLOR_DW1 */
304 OUT_RING(ring, uc.ui[2]); /* RB_CLEAR_COLOR_DW2 */
305 OUT_RING(ring, uc.ui[3]); /* RB_CLEAR_COLOR_DW3 */
306
307 fd5_emit_blit(ctx->batch, ring);
308 }
309 }
310
311 if (pfb->zsbuf && (buffers & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))) {
312 uint32_t clear = util_pack_z_stencil(pfb->zsbuf->format, depth, stencil);
313 uint32_t mask = 0;
314
315 if (buffers & FD_BUFFER_DEPTH)
316 mask |= 0x1;
317
318 if (buffers & FD_BUFFER_STENCIL)
319 mask |= 0x2;
320
321 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
322 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_ZS));
323
324 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
325 OUT_RING(ring,
326 A5XX_RB_CLEAR_CNTL_FAST_CLEAR | A5XX_RB_CLEAR_CNTL_MASK(mask));
327
328 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
329 OUT_RING(ring, clear); /* RB_CLEAR_COLOR_DW0 */
330
331 fd5_emit_blit(ctx->batch, ring);
332
333 if (pfb->zsbuf && (buffers & FD_BUFFER_DEPTH)) {
334 struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
335 if (zsbuf->lrz) {
336 zsbuf->lrz_valid = true;
337 fd5_clear_lrz(ctx->batch, zsbuf, depth);
338 }
339 }
340 }
341
342 /* disable fast clear to not interfere w/ gmem->mem, etc.. */
343 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
344 OUT_RING(ring, 0x00000000); /* RB_CLEAR_CNTL */
345
346 return true;
347 }
348
349 void
fd5_draw_init(struct pipe_context * pctx)350 fd5_draw_init(struct pipe_context *pctx) disable_thread_safety_analysis
351 {
352 struct fd_context *ctx = fd_context(pctx);
353 ctx->draw_vbos = fd5_draw_vbos;
354 ctx->clear = fd5_clear;
355 }
356