1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/format/u_format.h"
29 #include "util/u_helpers.h"
30 #include "util/u_memory.h"
31 #include "util/u_string.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_query_hw.h"
35 #include "freedreno_resource.h"
36
37 #include "fd5_blend.h"
38 #include "fd5_blitter.h"
39 #include "fd5_context.h"
40 #include "fd5_emit.h"
41 #include "fd5_format.h"
42 #include "fd5_image.h"
43 #include "fd5_program.h"
44 #include "fd5_rasterizer.h"
45 #include "fd5_screen.h"
46 #include "fd5_texture.h"
47 #include "fd5_zsa.h"
48
49 #define emit_const_user fd5_emit_const_user
50 #define emit_const_bo fd5_emit_const_bo
51 #include "ir3_const.h"
52
53 /* regid: base const register
54 * prsc or dwords: buffer containing constant values
55 * sizedwords: size of const value buffer
56 */
57 static void
fd5_emit_const_user(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t sizedwords,const uint32_t * dwords)58 fd5_emit_const_user(struct fd_ringbuffer *ring,
59 const struct ir3_shader_variant *v, uint32_t regid,
60 uint32_t sizedwords, const uint32_t *dwords)
61 {
62 emit_const_asserts(ring, v, regid, sizedwords);
63
64 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sizedwords);
65 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) |
66 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
67 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) |
68 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords / 4));
69 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
70 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
71 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
72 for (int i = 0; i < sizedwords; i++)
73 OUT_RING(ring, ((uint32_t *)dwords)[i]);
74 }
75
76 static void
fd5_emit_const_bo(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t offset,uint32_t sizedwords,struct fd_bo * bo)77 fd5_emit_const_bo(struct fd_ringbuffer *ring,
78 const struct ir3_shader_variant *v, uint32_t regid,
79 uint32_t offset, uint32_t sizedwords, struct fd_bo *bo)
80 {
81 uint32_t dst_off = regid / 4;
82 assert(dst_off % 4 == 0);
83 uint32_t num_unit = sizedwords / 4;
84 assert(num_unit % 4 == 0);
85
86 emit_const_asserts(ring, v, regid, sizedwords);
87
88 OUT_PKT7(ring, CP_LOAD_STATE4, 3);
89 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(dst_off) |
90 CP_LOAD_STATE4_0_STATE_SRC(SS4_INDIRECT) |
91 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v->type)) |
92 CP_LOAD_STATE4_0_NUM_UNIT(num_unit));
93 OUT_RELOC(ring, bo, offset, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
94 }
95
96 static void
fd5_emit_const_ptrs(struct fd_ringbuffer * ring,gl_shader_stage type,uint32_t regid,uint32_t num,struct fd_bo ** bos,uint32_t * offsets)97 fd5_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type,
98 uint32_t regid, uint32_t num, struct fd_bo **bos,
99 uint32_t *offsets)
100 {
101 uint32_t anum = align(num, 2);
102 uint32_t i;
103
104 assert((regid % 4) == 0);
105
106 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
107 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) |
108 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
109 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
110 CP_LOAD_STATE4_0_NUM_UNIT(anum / 2));
111 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
112 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
113 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
114
115 for (i = 0; i < num; i++) {
116 if (bos[i]) {
117 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
118 } else {
119 OUT_RING(ring, 0xbad00000 | (i << 16));
120 OUT_RING(ring, 0xbad00000 | (i << 16));
121 }
122 }
123
124 for (; i < anum; i++) {
125 OUT_RING(ring, 0xffffffff);
126 OUT_RING(ring, 0xffffffff);
127 }
128 }
129
130 static bool
is_stateobj(struct fd_ringbuffer * ring)131 is_stateobj(struct fd_ringbuffer *ring)
132 {
133 return false;
134 }
135
136 static void
emit_const_ptrs(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t dst_offset,uint32_t num,struct fd_bo ** bos,uint32_t * offsets)137 emit_const_ptrs(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
138 uint32_t dst_offset, uint32_t num, struct fd_bo **bos,
139 uint32_t *offsets)
140 {
141 /* TODO inline this */
142 assert(dst_offset + num <= v->constlen * 4);
143 fd5_emit_const_ptrs(ring, v->type, dst_offset, num, bos, offsets);
144 }
145
146 void
fd5_emit_cs_consts(const struct ir3_shader_variant * v,struct fd_ringbuffer * ring,struct fd_context * ctx,const struct pipe_grid_info * info)147 fd5_emit_cs_consts(const struct ir3_shader_variant *v,
148 struct fd_ringbuffer *ring, struct fd_context *ctx,
149 const struct pipe_grid_info *info)
150 {
151 ir3_emit_cs_consts(v, ring, ctx, info);
152 }
153
154 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
155 * the same as a6xx then move this somewhere common ;-)
156 *
157 * Entry layout looks like (total size, 0x60 bytes):
158 */
159
160 struct PACKED bcolor_entry {
161 uint32_t fp32[4];
162 uint16_t ui16[4];
163 int16_t si16[4];
164
165 uint16_t fp16[4];
166 uint16_t rgb565;
167 uint16_t rgb5a1;
168 uint16_t rgba4;
169 uint8_t __pad0[2];
170 uint8_t ui8[4];
171 int8_t si8[4];
172 uint32_t rgb10a2;
173 uint32_t z24; /* also s8? */
174
175 uint16_t
176 srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
177 uint8_t __pad1[56];
178 };
179
180 #define FD5_BORDER_COLOR_SIZE 0x80
181 #define FD5_BORDER_COLOR_UPLOAD_SIZE \
182 (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
183
184 static void
setup_border_colors(struct fd_texture_stateobj * tex,struct bcolor_entry * entries)185 setup_border_colors(struct fd_texture_stateobj *tex,
186 struct bcolor_entry *entries)
187 {
188 unsigned i, j;
189 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
190
191 for (i = 0; i < tex->num_samplers; i++) {
192 struct bcolor_entry *e = &entries[i];
193 struct pipe_sampler_state *sampler = tex->samplers[i];
194 union pipe_color_union *bc;
195
196 if (!sampler)
197 continue;
198
199 bc = &sampler->border_color;
200
201 enum pipe_format format = sampler->border_color_format;
202 const struct util_format_description *desc =
203 util_format_description(format);
204
205 e->rgb565 = 0;
206 e->rgb5a1 = 0;
207 e->rgba4 = 0;
208 e->rgb10a2 = 0;
209 e->z24 = 0;
210
211 for (j = 0; j < 4; j++) {
212 int c = desc->swizzle[j];
213 int cd = c;
214
215 /*
216 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
217 * stencil border color value in bc->ui[0] but according
218 * to desc->swizzle and desc->channel, the .x component
219 * is NONE and the stencil value is in the y component.
220 * Meanwhile the hardware wants this in the .x componetn.
221 */
222 if ((format == PIPE_FORMAT_X24S8_UINT) ||
223 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
224 if (j == 0) {
225 c = 1;
226 cd = 0;
227 } else {
228 continue;
229 }
230 }
231
232 if (c >= 4)
233 continue;
234
235 if (desc->channel[c].pure_integer) {
236 uint16_t clamped;
237 switch (desc->channel[c].size) {
238 case 2:
239 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
240 clamped = CLAMP(bc->ui[j], 0, 0x3);
241 break;
242 case 8:
243 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
244 clamped = CLAMP(bc->i[j], -128, 127);
245 else
246 clamped = CLAMP(bc->ui[j], 0, 255);
247 break;
248 case 10:
249 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
250 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
251 break;
252 case 16:
253 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
254 clamped = CLAMP(bc->i[j], -32768, 32767);
255 else
256 clamped = CLAMP(bc->ui[j], 0, 65535);
257 break;
258 default:
259 unreachable("Unexpected bit size");
260 case 32:
261 clamped = 0;
262 break;
263 }
264 e->fp32[cd] = bc->ui[j];
265 e->fp16[cd] = clamped;
266 } else {
267 float f = bc->f[j];
268 float f_u = CLAMP(f, 0, 1);
269 float f_s = CLAMP(f, -1, 1);
270
271 e->fp32[c] = fui(f);
272 e->fp16[c] = _mesa_float_to_half(f);
273 e->srgb[c] = _mesa_float_to_half(f_u);
274 e->ui16[c] = f_u * 0xffff;
275 e->si16[c] = f_s * 0x7fff;
276 e->ui8[c] = f_u * 0xff;
277 e->si8[c] = f_s * 0x7f;
278 if (c == 1)
279 e->rgb565 |= (int)(f_u * 0x3f) << 5;
280 else if (c < 3)
281 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
282 if (c == 3)
283 e->rgb5a1 |= (f_u > 0.5f) ? 0x8000 : 0;
284 else
285 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
286 if (c == 3)
287 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
288 else
289 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
290 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
291 if (c == 0)
292 e->z24 = f_u * 0xffffff;
293 }
294 }
295
296 #ifdef DEBUG
297 memset(&e->__pad0, 0, sizeof(e->__pad0));
298 memset(&e->__pad1, 0, sizeof(e->__pad1));
299 #endif
300 }
301 }
302
303 static void
emit_border_color(struct fd_context * ctx,struct fd_ringbuffer * ring)304 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring) assert_dt
305 {
306 struct fd5_context *fd5_ctx = fd5_context(ctx);
307 struct bcolor_entry *entries;
308 unsigned off;
309 void *ptr;
310
311 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
312
313 const unsigned int alignment =
314 util_next_power_of_two(FD5_BORDER_COLOR_UPLOAD_SIZE);
315 u_upload_alloc(fd5_ctx->border_color_uploader, 0,
316 FD5_BORDER_COLOR_UPLOAD_SIZE, alignment,
317 &off, &fd5_ctx->border_color_buf, &ptr);
318
319 entries = ptr;
320
321 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
322 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
323 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
324
325 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
326 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
327
328 u_upload_unmap(fd5_ctx->border_color_uploader);
329 }
330
331 static bool
emit_textures(struct fd_context * ctx,struct fd_ringbuffer * ring,enum a4xx_state_block sb,struct fd_texture_stateobj * tex)332 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
333 enum a4xx_state_block sb,
334 struct fd_texture_stateobj *tex) assert_dt
335 {
336 bool needs_border = false;
337 unsigned bcolor_offset =
338 (sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0;
339 unsigned i;
340
341 if (tex->num_samplers > 0) {
342 /* output sampler state: */
343 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers));
344 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
345 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
346 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
347 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers));
348 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
349 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
350 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
351 for (i = 0; i < tex->num_samplers; i++) {
352 static const struct fd5_sampler_stateobj dummy_sampler = {};
353 const struct fd5_sampler_stateobj *sampler =
354 tex->samplers[i] ? fd5_sampler_stateobj(tex->samplers[i])
355 : &dummy_sampler;
356 OUT_RING(ring, sampler->texsamp0);
357 OUT_RING(ring, sampler->texsamp1);
358 OUT_RING(ring, sampler->texsamp2 |
359 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset + i));
360 OUT_RING(ring, sampler->texsamp3);
361
362 needs_border |= sampler->needs_border;
363 }
364 }
365
366 if (tex->num_textures > 0) {
367 unsigned num_textures = tex->num_textures;
368
369 /* emit texture state: */
370 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures));
371 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
372 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
373 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
374 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
375 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
376 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
377 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
378 for (i = 0; i < tex->num_textures; i++) {
379 static const struct fd5_pipe_sampler_view dummy_view = {};
380 const struct fd5_pipe_sampler_view *view =
381 tex->textures[i] ? fd5_pipe_sampler_view(tex->textures[i])
382 : &dummy_view;
383 enum a5xx_tile_mode tile_mode = TILE5_LINEAR;
384
385 if (view->base.texture)
386 tile_mode = fd_resource(view->base.texture)->layout.tile_mode;
387
388 OUT_RING(ring,
389 view->texconst0 | A5XX_TEX_CONST_0_TILE_MODE(tile_mode));
390 OUT_RING(ring, view->texconst1);
391 OUT_RING(ring, view->texconst2);
392 OUT_RING(ring, view->texconst3);
393 if (view->base.texture) {
394 struct fd_resource *rsc = fd_resource(view->base.texture);
395 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
396 rsc = rsc->stencil;
397 OUT_RELOC(ring, rsc->bo, view->offset,
398 (uint64_t)view->texconst5 << 32, 0);
399 } else {
400 OUT_RING(ring, 0x00000000);
401 OUT_RING(ring, view->texconst5);
402 }
403 OUT_RING(ring, view->texconst6);
404 OUT_RING(ring, view->texconst7);
405 OUT_RING(ring, view->texconst8);
406 OUT_RING(ring, view->texconst9);
407 OUT_RING(ring, view->texconst10);
408 OUT_RING(ring, view->texconst11);
409 }
410 }
411
412 return needs_border;
413 }
414
415 static void
emit_ssbos(struct fd_context * ctx,struct fd_ringbuffer * ring,enum a4xx_state_block sb,struct fd_shaderbuf_stateobj * so,const struct ir3_shader_variant * v)416 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
417 enum a4xx_state_block sb, struct fd_shaderbuf_stateobj *so,
418 const struct ir3_shader_variant *v)
419 {
420 unsigned count = util_last_bit(so->enabled_mask);
421
422 if (count == 0)
423 return;
424
425 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + 2 * count);
426 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
427 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
428 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
429 CP_LOAD_STATE4_0_NUM_UNIT(count));
430 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
431 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
432 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
433
434 for (unsigned i = 0; i < count; i++) {
435 struct pipe_shader_buffer *buf = &so->sb[i];
436 unsigned sz = buf->buffer_size;
437
438 /* Unlike a6xx, SSBO size is in bytes. */
439 OUT_RING(ring, A5XX_SSBO_1_0_WIDTH(sz & MASK(16)));
440 OUT_RING(ring, A5XX_SSBO_1_1_HEIGHT(sz >> 16));
441 }
442
443 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + 2 * count);
444 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
445 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
446 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
447 CP_LOAD_STATE4_0_NUM_UNIT(count));
448 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_UBO) |
449 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
450 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
451 for (unsigned i = 0; i < count; i++) {
452 struct pipe_shader_buffer *buf = &so->sb[i];
453
454 if (buf->buffer) {
455 struct fd_resource *rsc = fd_resource(buf->buffer);
456 OUT_RELOC(ring, rsc->bo, buf->buffer_offset, 0, 0);
457 } else {
458 OUT_RING(ring, 0x00000000);
459 OUT_RING(ring, 0x00000000);
460 }
461 }
462 }
463
464 void
fd5_emit_vertex_bufs(struct fd_ringbuffer * ring,struct fd5_emit * emit)465 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
466 {
467 int32_t i, j;
468 const struct fd_vertex_state *vtx = emit->vtx;
469 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
470
471 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
472 if (vp->inputs[i].sysval)
473 continue;
474 if (vp->inputs[i].compmask) {
475 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
476 const struct pipe_vertex_buffer *vb =
477 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
478 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
479 enum pipe_format pfmt = elem->src_format;
480 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
481 bool isint = util_format_is_pure_integer(pfmt);
482 uint32_t off = vb->buffer_offset + elem->src_offset;
483 uint32_t size = vb->buffer.resource->width0 - off;
484 assert(fmt != VFMT5_NONE);
485
486 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
487 OUT_RELOC(ring, rsc->bo, off, 0, 0);
488 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
489 OUT_RING(ring, elem->src_stride); /* VFD_FETCH[j].STRIDE */
490
491 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
492 OUT_RING(
493 ring,
494 A5XX_VFD_DECODE_INSTR_IDX(j) | A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
495 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) |
496 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt)) |
497 A5XX_VFD_DECODE_INSTR_UNK30 |
498 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT));
499 OUT_RING(
500 ring,
501 MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
502
503 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
504 OUT_RING(ring,
505 A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
506 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
507
508 j++;
509 }
510 }
511
512 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
513 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
514 }
515
516 void
fd5_emit_state(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd5_emit * emit)517 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
518 struct fd5_emit *emit)
519 {
520 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
521 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
522 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
523 const enum fd_dirty_3d_state dirty = emit->dirty;
524 bool needs_border = false;
525
526 emit_marker5(ring, 5);
527
528 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
529 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
530
531 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
532 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
533 }
534
535 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
536 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
537 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
538 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
539 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
540 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
541 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
542 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
543 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
544 }
545
546 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
547 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
548 uint32_t rb_alpha_control = zsa->rb_alpha_control;
549
550 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
551 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
552
553 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
554 OUT_RING(ring, rb_alpha_control);
555
556 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
557 OUT_RING(ring, zsa->rb_stencil_control);
558 }
559
560 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
561 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
562 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
563
564 if (pfb->zsbuf) {
565 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
566 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
567
568 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
569 gras_lrz_cntl = 0;
570 else if (emit->binning_pass && blend->lrz_write && zsa->lrz_write)
571 gras_lrz_cntl |= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE;
572
573 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
574 OUT_RING(ring, gras_lrz_cntl);
575 }
576 }
577
578 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
579 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
580 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
581
582 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2);
583 OUT_RING(ring, zsa->rb_stencilrefmask |
584 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
585 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
586 A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
587 }
588
589 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
590 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
591 bool fragz = fp->no_earlyz || fp->has_kill || zsa->base.alpha_enabled ||
592 fp->writes_pos;
593
594 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
595 OUT_RING(ring, zsa->rb_depth_cntl);
596
597 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
598 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
599 COND(fragz && fp->fragcoord_compmask != 0,
600 A5XX_RB_DEPTH_PLANE_CNTL_UNK1));
601
602 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
603 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
604 COND(fragz && fp->fragcoord_compmask != 0,
605 A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
606 }
607
608 /* NOTE: scissor enabled bit is part of rasterizer state: */
609 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
610 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
611
612 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
613 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
614 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
615 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx) |
616 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy));
617
618 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
619 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
620 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
621 OUT_RING(ring,
622 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx) |
623 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy));
624
625 ctx->batch->max_scissor.minx =
626 MIN2(ctx->batch->max_scissor.minx, scissor->minx);
627 ctx->batch->max_scissor.miny =
628 MIN2(ctx->batch->max_scissor.miny, scissor->miny);
629 ctx->batch->max_scissor.maxx =
630 MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
631 ctx->batch->max_scissor.maxy =
632 MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
633 }
634
635 if (dirty & FD_DIRTY_VIEWPORT) {
636 struct pipe_viewport_state *vp = & ctx->viewport[0];
637
638 fd_wfi(ctx->batch, ring);
639
640 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
641 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(vp->translate[0]));
642 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(vp->scale[0]));
643 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(vp->translate[1]));
644 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(vp->scale[1]));
645 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(vp->translate[2]));
646 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(vp->scale[2]));
647 }
648
649 if (dirty & FD_DIRTY_PROG)
650 fd5_program_emit(ctx, ring, emit);
651
652 if (dirty & FD_DIRTY_RASTERIZER) {
653 struct fd5_rasterizer_stateobj *rasterizer =
654 fd5_rasterizer_stateobj(ctx->rasterizer);
655
656 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
657 OUT_RING(ring, rasterizer->gras_su_cntl |
658 A5XX_GRAS_SU_CNTL_LINE_MODE(pfb->samples > 1 ?
659 RECTANGULAR : BRESENHAM));
660
661 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
662 OUT_RING(ring, rasterizer->gras_su_point_minmax);
663 OUT_RING(ring, rasterizer->gras_su_point_size);
664
665 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
666 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
667 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
668 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
669
670 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
671 OUT_RING(ring, rasterizer->pc_raster_cntl);
672
673 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
674 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
675 }
676
677 /* note: must come after program emit.. because there is some overlap
678 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
679 * values from fd5_program_emit() to avoid having to re-emit the prog
680 * every time rast state changes.
681 *
682 * Since the primitive restart state is not part of a tracked object, we
683 * re-emit this register every time.
684 */
685 if (emit->info && ctx->rasterizer) {
686 struct fd5_rasterizer_stateobj *rasterizer =
687 fd5_rasterizer_stateobj(ctx->rasterizer);
688 unsigned max_loc = fd5_context(ctx)->max_loc;
689
690 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
691 OUT_RING(ring,
692 rasterizer->pc_primitive_cntl |
693 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc) |
694 COND(emit->info->primitive_restart && emit->info->index_size,
695 A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART));
696 }
697
698 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
699 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
700 unsigned nr = pfb->nr_cbufs;
701
702 if (emit->binning_pass)
703 nr = 0;
704 else if (ctx->rasterizer->rasterizer_discard)
705 nr = 0;
706
707 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
708 OUT_RING(ring,
709 A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
710 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
711
712 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
713 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
714 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
715 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
716 }
717
718 ir3_emit_vs_consts(vp, ring, ctx, emit->info, emit->indirect, emit->draw);
719 if (!emit->binning_pass)
720 ir3_emit_fs_consts(fp, ring, ctx);
721
722 const struct ir3_stream_output_info *info = &vp->stream_output;
723 if (info->num_outputs) {
724 struct fd_streamout_stateobj *so = &ctx->streamout;
725
726 for (unsigned i = 0; i < so->num_targets; i++) {
727 struct fd_stream_output_target *target =
728 fd_stream_output_target(so->targets[i]);
729
730 if (!target)
731 continue;
732
733 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
734 /* VPC_SO[i].BUFFER_BASE_LO: */
735 OUT_RELOC(ring, fd_resource(target->base.buffer)->bo, 0, 0, 0);
736 OUT_RING(ring, target->base.buffer_size + target->base.buffer_offset);
737
738 struct fd_bo *offset_bo = fd_resource(target->offset_buf)->bo;
739
740 if (so->reset & (1 << i)) {
741 assert(so->offsets[i] == 0);
742
743 OUT_PKT7(ring, CP_MEM_WRITE, 3);
744 OUT_RELOC(ring, offset_bo, 0, 0, 0);
745 OUT_RING(ring, target->base.buffer_offset);
746
747 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 1);
748 OUT_RING(ring, target->base.buffer_offset);
749 } else {
750 OUT_PKT7(ring, CP_MEM_TO_REG, 3);
751 OUT_RING(ring,
752 CP_MEM_TO_REG_0_REG(REG_A5XX_VPC_SO_BUFFER_OFFSET(i)) |
753 CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
754 CP_MEM_TO_REG_0_CNT(0));
755 OUT_RELOC(ring, offset_bo, 0, 0, 0);
756 }
757
758 // After a draw HW would write the new offset to offset_bo
759 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(i), 2);
760 OUT_RELOC(ring, offset_bo, 0, 0, 0);
761
762 so->reset &= ~(1 << i);
763
764 emit->streamout_mask |= (1 << i);
765 }
766 }
767
768 if (!emit->streamout_mask && info->num_outputs) {
769 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 4);
770 OUT_RING(ring, REG_A5XX_VPC_SO_CNTL);
771 OUT_RING(ring, 0);
772 OUT_RING(ring, REG_A5XX_VPC_SO_BUF_CNTL);
773 OUT_RING(ring, 0);
774 } else if (emit->streamout_mask && !(dirty & FD_DIRTY_PROG)) {
775 /* reemit the program (if we haven't already) to re-enable streamout. We
776 * really should switch to setting up program state at compile time so we
777 * can separate the SO state from the rest, and not recompute all the
778 * time.
779 */
780 fd5_program_emit(ctx, ring, emit);
781 }
782
783 if (dirty & FD_DIRTY_BLEND) {
784 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
785 uint32_t i;
786
787 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
788 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
789 bool is_int = util_format_is_pure_integer(format);
790 bool has_alpha = util_format_has_alpha(format);
791 uint32_t control = blend->rb_mrt[i].control;
792
793 if (is_int) {
794 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
795 control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
796 }
797
798 if (!has_alpha) {
799 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
800 }
801
802 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
803 OUT_RING(ring, control);
804
805 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
806 OUT_RING(ring, blend->rb_mrt[i].blend_control);
807 }
808
809 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
810 OUT_RING(ring, blend->sp_blend_cntl);
811 }
812
813 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
814 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
815
816 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
817 OUT_RING(ring, blend->rb_blend_cntl |
818 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
819 }
820
821 if (dirty & FD_DIRTY_BLEND_COLOR) {
822 struct pipe_blend_color *bcolor = &ctx->blend_color;
823
824 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
825 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
826 A5XX_RB_BLEND_RED_UINT(CLAMP(bcolor->color[0], 0.f, 1.f) * 0xff) |
827 A5XX_RB_BLEND_RED_SINT(CLAMP(bcolor->color[0], -1.f, 1.f) * 0x7f));
828 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
829 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
830 A5XX_RB_BLEND_GREEN_UINT(CLAMP(bcolor->color[1], 0.f, 1.f) * 0xff) |
831 A5XX_RB_BLEND_GREEN_SINT(CLAMP(bcolor->color[1], -1.f, 1.f) * 0x7f));
832 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
833 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
834 A5XX_RB_BLEND_BLUE_UINT(CLAMP(bcolor->color[2], 0.f, 1.f) * 0xff) |
835 A5XX_RB_BLEND_BLUE_SINT(CLAMP(bcolor->color[2], -1.f, 1.f) * 0x7f));
836 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
837 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
838 A5XX_RB_BLEND_ALPHA_UINT(CLAMP(bcolor->color[3], 0.f, 1.f) * 0xff) |
839 A5XX_RB_BLEND_ALPHA_SINT(CLAMP(bcolor->color[3], -1.f, 1.f) * 0x7f));
840 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
841 }
842
843 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
844 needs_border |=
845 emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
846 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
847 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
848 }
849
850 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {
851 needs_border |=
852 emit_textures(ctx, ring, SB4_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);
853 }
854
855 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
856 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_FRAGMENT].enabled_mask
857 ? ~0
858 : ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
859
860 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
861 OUT_RING(ring, 0);
862
863 if (needs_border)
864 emit_border_color(ctx, ring);
865
866 if (!emit->binning_pass) {
867 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
868 emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT],
869 fp);
870
871 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE)
872 fd5_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT, fp);
873 }
874 }
875
876 void
fd5_emit_cs_state(struct fd_context * ctx,struct fd_ringbuffer * ring,struct ir3_shader_variant * cp)877 fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
878 struct ir3_shader_variant *cp)
879 {
880 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
881
882 if (dirty & FD_DIRTY_SHADER_TEX) {
883 bool needs_border = false;
884 needs_border |=
885 emit_textures(ctx, ring, SB4_CS_TEX, &ctx->tex[PIPE_SHADER_COMPUTE]);
886
887 if (needs_border)
888 emit_border_color(ctx, ring);
889
890 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
891 OUT_RING(ring, 0);
892
893 OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);
894 OUT_RING(ring, 0);
895
896 OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);
897 OUT_RING(ring, 0);
898
899 OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);
900 OUT_RING(ring, 0);
901
902 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
903 OUT_RING(ring, 0);
904 }
905
906 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
907 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask
908 ? ~0
909 : ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
910
911 if (dirty & FD_DIRTY_SHADER_SSBO)
912 emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE],
913 cp);
914
915 if (dirty & FD_DIRTY_SHADER_IMAGE)
916 fd5_emit_images(ctx, ring, PIPE_SHADER_COMPUTE, cp);
917 }
918
919 /* emit setup at begin of new cmdstream buffer (don't rely on previous
920 * state, there could have been a context switch between ioctls):
921 */
922 void
fd5_emit_restore(struct fd_batch * batch,struct fd_ringbuffer * ring)923 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
924 {
925 struct fd_context *ctx = batch->ctx;
926
927 fd5_set_render_mode(ctx, ring, BYPASS);
928 fd5_cache_flush(batch, ring);
929
930 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
931 OUT_RING(ring, 0xfffff);
932
933 /*
934 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
935 0000000500024048: 70d08003 00000000 001c5000 00000005
936 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
937 0000000500024058: 70d08003 00000010 001c7000 00000005
938
939 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
940 0000000500024068: 70268000
941 */
942
943 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
944 OUT_RING(ring, 0xffffffff);
945
946 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
947 OUT_RING(ring, 0x00000012);
948
949 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
950 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0f) |
951 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0f));
952 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5f));
953
954 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
955 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
956
957 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
958 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
959
960 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
961 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
962
963 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
964 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
965
966 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
967 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
968 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
969
970 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
971 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
972
973 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
974 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
975
976 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
977 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
978
979 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
980 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
981
982 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
983 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
984
985 if (ctx->screen->gpu_id == 540) {
986 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
987 OUT_RING(ring, 0x800); /* SP_DBG_ECO_CNTL */
988
989 OUT_PKT4(ring, REG_A5XX_HLSQ_DBG_ECO_CNTL, 1);
990 OUT_RING(ring, 0x0);
991
992 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
993 OUT_RING(ring, 0x800400);
994 } else {
995 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
996 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
997 }
998
999 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
1000 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
1001
1002 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
1003 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
1004 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
1005
1006 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
1007 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
1008
1009 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
1010 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
1011
1012 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
1013 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
1014
1015 /* we don't use this yet.. probably best to disable.. */
1016 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1017 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1018 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1019 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1020 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1021 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1022
1023 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
1024 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
1025
1026 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
1027 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
1028
1029 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
1030 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
1031
1032 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
1033 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
1034
1035 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
1036 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
1037
1038 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1039 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1040 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1041 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1042
1043 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1044 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1045 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1046
1047 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
1048 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
1049
1050 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
1051 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
1052
1053 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
1054 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
1055
1056 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
1057 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
1058
1059 OUT_PKT4(ring, REG_A5XX_GRAS_SU_LAYERED, 1);
1060 OUT_RING(ring, 0x00000000); /* GRAS_SU_LAYERED */
1061
1062 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);
1063 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1064
1065 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
1066 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
1067
1068 OUT_PKT4(ring, REG_A5XX_PC_GS_LAYERED, 1);
1069 OUT_RING(ring, 0x00000000); /* PC_GS_LAYERED */
1070
1071 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
1072 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
1073
1074 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
1075 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
1076
1077 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1078 OUT_RING(ring, 0x00000000);
1079 OUT_RING(ring, 0x00000000);
1080 OUT_RING(ring, 0x00000000);
1081
1082 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
1083 OUT_RING(ring, 0x00000000);
1084 OUT_RING(ring, 0x00000000);
1085 OUT_RING(ring, 0x00000000);
1086 OUT_RING(ring, 0x00000000);
1087 OUT_RING(ring, 0x00000000);
1088 OUT_RING(ring, 0x00000000);
1089
1090 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
1091 OUT_RING(ring, 0x00000000);
1092 OUT_RING(ring, 0x00000000);
1093 OUT_RING(ring, 0x00000000);
1094 OUT_RING(ring, 0x00000000);
1095 OUT_RING(ring, 0x00000000);
1096 OUT_RING(ring, 0x00000000);
1097
1098 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
1099 OUT_RING(ring, 0x00000000);
1100 OUT_RING(ring, 0x00000000);
1101 OUT_RING(ring, 0x00000000);
1102
1103 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
1104 OUT_RING(ring, 0x00000000);
1105
1106 OUT_PKT4(ring, REG_A5XX_SP_HS_CTRL_REG0, 1);
1107 OUT_RING(ring, 0x00000000);
1108
1109 OUT_PKT4(ring, REG_A5XX_SP_GS_CTRL_REG0, 1);
1110 OUT_RING(ring, 0x00000000);
1111
1112 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
1113 OUT_RING(ring, 0x00000000);
1114 OUT_RING(ring, 0x00000000);
1115 OUT_RING(ring, 0x00000000);
1116 OUT_RING(ring, 0x00000000);
1117
1118 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
1119 OUT_RING(ring, 0x00000000);
1120 OUT_RING(ring, 0x00000000);
1121
1122 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
1123 OUT_RING(ring, 0x00000000);
1124 OUT_RING(ring, 0x00000000);
1125 OUT_RING(ring, 0x00000000);
1126
1127 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
1128 OUT_RING(ring, 0x00000000);
1129 OUT_RING(ring, 0x00000000);
1130 OUT_RING(ring, 0x00000000);
1131
1132 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
1133 OUT_RING(ring, 0x00000000);
1134 OUT_RING(ring, 0x00000000);
1135 OUT_RING(ring, 0x00000000);
1136
1137 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
1138 OUT_RING(ring, 0x00000000);
1139 OUT_RING(ring, 0x00000000);
1140 OUT_RING(ring, 0x00000000);
1141
1142 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
1143 OUT_RING(ring, 0x00000000);
1144 OUT_RING(ring, 0x00000000);
1145 OUT_RING(ring, 0x00000000);
1146
1147 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
1148 OUT_RING(ring, 0x00000000);
1149 OUT_RING(ring, 0x00000000);
1150 OUT_RING(ring, 0x00000000);
1151
1152 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
1153 OUT_RING(ring, 0x00000000);
1154 }
1155
1156 static void
fd5_mem_to_mem(struct fd_ringbuffer * ring,struct pipe_resource * dst,unsigned dst_off,struct pipe_resource * src,unsigned src_off,unsigned sizedwords)1157 fd5_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1158 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1159 unsigned sizedwords)
1160 {
1161 struct fd_bo *src_bo = fd_resource(src)->bo;
1162 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1163 unsigned i;
1164
1165 for (i = 0; i < sizedwords; i++) {
1166 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1167 OUT_RING(ring, 0x00000000);
1168 OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
1169 OUT_RELOC(ring, src_bo, src_off, 0, 0);
1170
1171 dst_off += 4;
1172 src_off += 4;
1173 }
1174 }
1175
1176 void
fd5_emit_init_screen(struct pipe_screen * pscreen)1177 fd5_emit_init_screen(struct pipe_screen *pscreen)
1178 {
1179 struct fd_screen *screen = fd_screen(pscreen);
1180 screen->emit_ib = fd5_emit_ib;
1181 screen->mem_to_mem = fd5_mem_to_mem;
1182 }
1183
1184 void
fd5_emit_init(struct pipe_context * pctx)1185 fd5_emit_init(struct pipe_context *pctx)
1186 {
1187 }
1188