1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/bitset.h"
29 #include "util/format/u_format.h"
30 #include "util/u_inlines.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33
34 #include "freedreno_program.h"
35
36 #include "fd5_emit.h"
37 #include "fd5_format.h"
38 #include "fd5_program.h"
39 #include "fd5_texture.h"
40
41 #include "ir3_cache.h"
42
43 void
fd5_emit_shader(struct fd_ringbuffer * ring,const struct ir3_shader_variant * so)44 fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
45 {
46 const struct ir3_info *si = &so->info;
47 enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
48 enum a4xx_state_src src;
49 uint32_t i, sz, *bin;
50
51 if (FD_DBG(DIRECT)) {
52 sz = si->sizedwords;
53 src = SS4_DIRECT;
54 bin = fd_bo_map(so->bo);
55 } else {
56 sz = 0;
57 src = SS4_INDIRECT;
58 bin = NULL;
59 }
60
61 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
62 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
63 CP_LOAD_STATE4_0_STATE_SRC(src) |
64 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
65 CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen));
66 if (bin) {
67 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
68 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
69 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
70 } else {
71 OUT_RELOC(ring, so->bo, 0, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
72 }
73
74 /* for how clever coverity is, it is sometimes rather dull, and
75 * doesn't realize that the only case where bin==NULL, sz==0:
76 */
77 assume(bin || (sz == 0));
78
79 for (i = 0; i < sz; i++) {
80 OUT_RING(ring, bin[i]);
81 }
82 }
83
84 void
fd5_emit_shader_obj(struct fd_context * ctx,struct fd_ringbuffer * ring,const struct ir3_shader_variant * so,uint32_t shader_obj_reg)85 fd5_emit_shader_obj(struct fd_context *ctx, struct fd_ringbuffer *ring,
86 const struct ir3_shader_variant *so,
87 uint32_t shader_obj_reg)
88 {
89 ir3_get_private_mem(ctx, so);
90
91 OUT_PKT4(ring, shader_obj_reg, 6);
92 OUT_RELOC(ring, so->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
93
94 uint32_t per_sp_size = ctx->pvtmem[so->pvtmem_per_wave].per_sp_size;
95 OUT_RING(ring, A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(
96 ctx->pvtmem[so->pvtmem_per_wave].per_fiber_size) |
97 A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET(per_sp_size));
98 if (so->pvtmem_size > 0) { /* SP_xS_PVT_MEM_ADDR */
99 OUT_RELOC(ring, ctx->pvtmem[so->pvtmem_per_wave].bo, 0, 0, 0);
100 fd_ringbuffer_attach_bo(ring, ctx->pvtmem[so->pvtmem_per_wave].bo);
101 } else {
102 OUT_RING(ring, 0);
103 OUT_RING(ring, 0);
104 }
105 OUT_RING(ring, A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(per_sp_size));
106 }
107
108 /* TODO maybe some of this we could pre-compute once rather than having
109 * so much draw-time logic?
110 */
111 static void
emit_stream_out(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,struct ir3_shader_linkage * l)112 emit_stream_out(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
113 struct ir3_shader_linkage *l)
114 {
115 const struct ir3_stream_output_info *strmout = &v->stream_output;
116 unsigned ncomp[PIPE_MAX_SO_BUFFERS] = {0};
117 unsigned prog[align(l->max_loc, 2) / 2];
118
119 memset(prog, 0, sizeof(prog));
120
121 for (unsigned i = 0; i < strmout->num_outputs; i++) {
122 const struct ir3_stream_output *out = &strmout->output[i];
123 unsigned k = out->register_index;
124 unsigned idx;
125
126 ncomp[out->output_buffer] += out->num_components;
127
128 /* linkage map sorted by order frag shader wants things, so
129 * a bit less ideal here..
130 */
131 for (idx = 0; idx < l->cnt; idx++)
132 if (l->var[idx].slot == v->outputs[k].slot)
133 break;
134
135 assert(idx < l->cnt);
136
137 for (unsigned j = 0; j < out->num_components; j++) {
138 unsigned c = j + out->start_component;
139 unsigned loc = l->var[idx].loc + c;
140 unsigned off = j + out->dst_offset; /* in dwords */
141
142 if (loc & 1) {
143 prog[loc / 2] |= A5XX_VPC_SO_PROG_B_EN |
144 A5XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
145 A5XX_VPC_SO_PROG_B_OFF(off * 4);
146 } else {
147 prog[loc / 2] |= A5XX_VPC_SO_PROG_A_EN |
148 A5XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
149 A5XX_VPC_SO_PROG_A_OFF(off * 4);
150 }
151 }
152 }
153
154 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * ARRAY_SIZE(prog)));
155 OUT_RING(ring, REG_A5XX_VPC_SO_BUF_CNTL);
156 OUT_RING(ring, A5XX_VPC_SO_BUF_CNTL_ENABLE |
157 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) |
158 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) |
159 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) |
160 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3));
161 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(0));
162 OUT_RING(ring, ncomp[0]);
163 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(1));
164 OUT_RING(ring, ncomp[1]);
165 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(2));
166 OUT_RING(ring, ncomp[2]);
167 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(3));
168 OUT_RING(ring, ncomp[3]);
169 OUT_RING(ring, REG_A5XX_VPC_SO_CNTL);
170 OUT_RING(ring, A5XX_VPC_SO_CNTL_ENABLE);
171 for (unsigned i = 0; i < ARRAY_SIZE(prog); i++) {
172 OUT_RING(ring, REG_A5XX_VPC_SO_PROG);
173 OUT_RING(ring, prog[i]);
174 }
175 }
176
177 struct stage {
178 const struct ir3_shader_variant *v;
179 const struct ir3_info *i;
180 /* const sizes are in units of 4 * vec4 */
181 uint8_t constoff;
182 uint8_t constlen;
183 /* instr sizes are in units of 16 instructions */
184 uint8_t instroff;
185 uint8_t instrlen;
186 };
187
188 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES };
189
190 static void
setup_stages(struct fd5_emit * emit,struct stage * s)191 setup_stages(struct fd5_emit *emit, struct stage *s)
192 {
193 unsigned i;
194
195 s[VS].v = fd5_emit_get_vp(emit);
196 s[FS].v = fd5_emit_get_fp(emit);
197
198 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
199
200 for (i = 0; i < MAX_STAGES; i++) {
201 if (s[i].v) {
202 s[i].i = &s[i].v->info;
203 /* constlen is in units of 4 * vec4: */
204 assert(s[i].v->constlen % 4 == 0);
205 s[i].constlen = s[i].v->constlen / 4;
206 /* instrlen is already in units of 16 instr.. although
207 * probably we should ditch that and not make the compiler
208 * care about instruction group size of a3xx vs a5xx
209 */
210 s[i].instrlen = s[i].v->instrlen;
211 } else {
212 s[i].i = NULL;
213 s[i].constlen = 0;
214 s[i].instrlen = 0;
215 }
216 }
217
218 /* NOTE: at least for gles2, blob partitions VS at bottom of const
219 * space and FS taking entire remaining space. We probably don't
220 * need to do that the same way, but for now mimic what the blob
221 * does to make it easier to diff against register values from blob
222 *
223 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
224 * is run from external memory.
225 */
226 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
227 /* prioritize FS for internal memory: */
228 if (s[FS].instrlen < 64) {
229 /* if FS can fit, kick VS out to external memory: */
230 s[VS].instrlen = 0;
231 } else if (s[VS].instrlen < 64) {
232 /* otherwise if VS can fit, kick out FS: */
233 s[FS].instrlen = 0;
234 } else {
235 /* neither can fit, run both from external memory: */
236 s[VS].instrlen = 0;
237 s[FS].instrlen = 0;
238 }
239 }
240
241 unsigned constoff = 0;
242 for (i = 0; i < MAX_STAGES; i++) {
243 s[i].constoff = constoff;
244 constoff += s[i].constlen;
245 }
246
247 s[VS].instroff = 0;
248 s[FS].instroff = 64 - s[FS].instrlen;
249 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
250 }
251
252 static inline uint32_t
next_regid(uint32_t reg,uint32_t increment)253 next_regid(uint32_t reg, uint32_t increment)
254 {
255 if (VALIDREG(reg))
256 return reg + increment;
257 else
258 return regid(63, 0);
259 }
260 void
fd5_program_emit(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd5_emit * emit)261 fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
262 struct fd5_emit *emit)
263 {
264 struct stage s[MAX_STAGES];
265 uint32_t pos_regid, psize_regid, color_regid[8];
266 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid,
267 samp_mask_regid;
268 uint32_t ij_regid[IJ_COUNT], vertex_regid, instance_regid, clip0_regid,
269 clip1_regid;
270 enum a3xx_threadsize fssz;
271 uint8_t psize_loc = ~0;
272 int i, j;
273
274 setup_stages(emit, s);
275
276 bool do_streamout = (s[VS].v->stream_output.num_outputs > 0);
277 uint8_t clip_mask = s[VS].v->clip_mask,
278 cull_mask = s[VS].v->cull_mask;
279 uint8_t clip_cull_mask = clip_mask | cull_mask;
280
281 /* Unlike a6xx, we don't factor the rasterizer's clip enables in here. It's
282 * already handled by the frontend by storing 0.0 to the clipdist in the
283 * shader variant (using either nir_lower_clip_disable for clip distances
284 * from the source shader, or nir_lower_clip_vs for user clip planes).
285 * Masking the disabled clipdists off causes GPU hangs in tests like
286 * spec@glsl-1.20@execution@clipping@vs-clip-vertex-enables.
287 */
288
289 fssz = (s[FS].i->double_threadsize) ? FOUR_QUADS : TWO_QUADS;
290
291 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
292 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
293 clip0_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_CLIP_DIST0);
294 clip1_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_CLIP_DIST1);
295 vertex_regid =
296 ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
297 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
298
299 if (s[FS].v->color0_mrt) {
300 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
301 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
302 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
303 } else {
304 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
305 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
306 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
307 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
308 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
309 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
310 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
311 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
312 }
313
314 samp_id_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_ID);
315 samp_mask_regid =
316 ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_MASK_IN);
317 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
318 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
319 zwcoord_regid = next_regid(coord_regid, 2);
320 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
321 ij_regid[i] = ir3_find_sysval_regid(
322 s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
323
324 /* we could probably divide this up into things that need to be
325 * emitted if frag-prog is dirty vs if vert-prog is dirty..
326 */
327
328 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5);
329 OUT_RING(ring, A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
330 A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
331 COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED));
332 OUT_RING(ring, A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
333 A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
334 COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED));
335 OUT_RING(ring, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
336 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
337 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED));
338 OUT_RING(ring, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
339 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
340 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED));
341 OUT_RING(ring, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
342 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
343 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED));
344
345 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
346 OUT_RING(ring, 0x00000000);
347
348 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
349 OUT_RING(ring, A5XX_HLSQ_VS_CNTL_INSTRLEN(s[VS].instrlen) |
350 COND(s[VS].v && s[VS].v->has_ssbo,
351 A5XX_HLSQ_VS_CNTL_SSBO_ENABLE));
352 OUT_RING(ring, A5XX_HLSQ_FS_CNTL_INSTRLEN(s[FS].instrlen) |
353 COND(s[FS].v && s[FS].v->has_ssbo,
354 A5XX_HLSQ_FS_CNTL_SSBO_ENABLE));
355 OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen) |
356 COND(s[HS].v && s[HS].v->has_ssbo,
357 A5XX_HLSQ_HS_CNTL_SSBO_ENABLE));
358 OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen) |
359 COND(s[DS].v && s[DS].v->has_ssbo,
360 A5XX_HLSQ_DS_CNTL_SSBO_ENABLE));
361 OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen) |
362 COND(s[GS].v && s[GS].v->has_ssbo,
363 A5XX_HLSQ_GS_CNTL_SSBO_ENABLE));
364
365 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5);
366 OUT_RING(ring, A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
367 A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
368 COND(s[VS].v, A5XX_SP_VS_CONFIG_ENABLED));
369 OUT_RING(ring, A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
370 A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
371 COND(s[FS].v, A5XX_SP_FS_CONFIG_ENABLED));
372 OUT_RING(ring, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
373 A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
374 COND(s[HS].v, A5XX_SP_HS_CONFIG_ENABLED));
375 OUT_RING(ring, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
376 A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
377 COND(s[DS].v, A5XX_SP_DS_CONFIG_ENABLED));
378 OUT_RING(ring, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
379 A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
380 COND(s[GS].v, A5XX_SP_GS_CONFIG_ENABLED));
381
382 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
383 OUT_RING(ring, 0x00000000);
384
385 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
386 OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */
387 OUT_RING(ring, s[VS].instrlen); /* HLSQ_VS_INSTRLEN */
388
389 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
390 OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */
391 OUT_RING(ring, s[FS].instrlen); /* HLSQ_FS_INSTRLEN */
392
393 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
394 OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */
395 OUT_RING(ring, s[HS].instrlen); /* HLSQ_HS_INSTRLEN */
396
397 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
398 OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */
399 OUT_RING(ring, s[DS].instrlen); /* HLSQ_DS_INSTRLEN */
400
401 OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2);
402 OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */
403 OUT_RING(ring, s[GS].instrlen); /* HLSQ_GS_INSTRLEN */
404
405 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
406 OUT_RING(ring, 0x00000000); /* HLSQ_CS_CONSTLEN */
407 OUT_RING(ring, 0x00000000); /* HLSQ_CS_INSTRLEN */
408
409 OUT_PKT4(ring, REG_A5XX_SP_VS_CTRL_REG0, 1);
410 OUT_RING(
411 ring,
412 A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
413 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
414 COND(s[VS].instrlen != 0, A5XX_SP_VS_CTRL_REG0_BUFFER) |
415 /* XXX: 0x2 is only unset in
416 * dEQP-GLES3.functional.ubo.single_nested_struct_array.single_buffer.packed_instance_array_vertex
417 * on a collection of blob traces. That shader is 1091 instrs, 0
418 * half, 3 full, 108 constlen. Other >1091 instr non-VS shaders don't
419 * unset it, so that's not the trick.
420 */
421 0x2 |
422 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(s[VS].v)) |
423 COND(s[VS].v->need_pixlod, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
424
425 /* If we have streamout, link against the real FS in the binning program,
426 * rather than the dummy FS used for binning pass state, to ensure the
427 * OUTLOC's match. Depending on whether we end up doing sysmem or gmem, the
428 * actual streamout could happen with either the binning pass or draw pass
429 * program, but the same streamout stateobj is used in either case:
430 */
431 const struct ir3_shader_variant *link_fs = s[FS].v;
432 if (do_streamout && emit->binning_pass)
433 link_fs = emit->prog->fs;
434 struct ir3_shader_linkage l = {0};
435 ir3_link_shaders(&l, s[VS].v, link_fs, true);
436
437 uint8_t clip0_loc = l.clip0_loc;
438 uint8_t clip1_loc = l.clip1_loc;
439
440 OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
441 OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
442 OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
443 OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */
444 OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
445
446 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
447 ir3_link_stream_out(&l, s[VS].v);
448
449 /* a5xx appends pos/psize to end of the linkage map: */
450 if (VALIDREG(pos_regid))
451 ir3_link_add(&l, VARYING_SLOT_POS, pos_regid, 0xf, l.max_loc);
452
453 if (VALIDREG(psize_regid)) {
454 psize_loc = l.max_loc;
455 ir3_link_add(&l, VARYING_SLOT_PSIZ, psize_regid, 0x1, l.max_loc);
456 }
457
458 /* Handle the case where clip/cull distances aren't read by the FS. Make
459 * sure to avoid adding an output with an empty writemask if the user
460 * disables all the clip distances in the API so that the slot is unused.
461 */
462 if (clip0_loc == 0xff && VALIDREG(clip0_regid) &&
463 (clip_cull_mask & 0xf) != 0) {
464 clip0_loc = l.max_loc;
465 ir3_link_add(&l, VARYING_SLOT_CLIP_DIST0, clip0_regid,
466 clip_cull_mask & 0xf, l.max_loc);
467 }
468
469 if (clip1_loc == 0xff && VALIDREG(clip1_regid) &&
470 (clip_cull_mask >> 4) != 0) {
471 clip1_loc = l.max_loc;
472 ir3_link_add(&l, VARYING_SLOT_CLIP_DIST1, clip1_regid,
473 clip_cull_mask >> 4, l.max_loc);
474 }
475
476 /* If we have stream-out, we use the full shader for binning
477 * pass, rather than the optimized binning pass one, so that we
478 * have all the varying outputs available for xfb. So streamout
479 * state should always be derived from the non-binning pass
480 * program:
481 */
482 if (do_streamout && !emit->binning_pass)
483 emit_stream_out(ring, s[VS].v, &l);
484
485 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
486 uint32_t reg = 0;
487
488 OUT_PKT4(ring, REG_A5XX_SP_VS_OUT_REG(i), 1);
489
490 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
491 reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
492 j++;
493
494 reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
495 reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
496 j++;
497
498 OUT_RING(ring, reg);
499 }
500
501 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
502 uint32_t reg = 0;
503
504 OUT_PKT4(ring, REG_A5XX_SP_VS_VPC_DST_REG(i), 1);
505
506 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
507 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
508 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
509 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
510
511 OUT_RING(ring, reg);
512 }
513
514 fd5_emit_shader_obj(ctx, ring, s[VS].v, REG_A5XX_SP_VS_OBJ_START_LO);
515
516 if (s[VS].instrlen)
517 fd5_emit_shader(ring, s[VS].v);
518
519 // TODO depending on other bits in this reg (if any) set somewhere else?
520 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
521 OUT_RING(ring, COND(s[VS].v->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE));
522
523 OUT_PKT4(ring, REG_A5XX_SP_PRIMITIVE_CNTL, 1);
524 OUT_RING(ring, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
525
526 OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1);
527 OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l.max_loc) |
528 COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) |
529 0x10000); // XXX
530
531 fd5_context(ctx)->max_loc = l.max_loc;
532
533 if (emit->binning_pass) {
534 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
535 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
536 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
537 } else {
538 fd5_emit_shader_obj(ctx, ring, s[FS].v, REG_A5XX_SP_FS_OBJ_START_LO);
539 }
540
541 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
542 OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
543 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(TWO_QUADS) |
544 0x00000880); /* XXX HLSQ_CONTROL_0 */
545 OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
546 OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
547 A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
548 A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) |
549 A5XX_HLSQ_CONTROL_2_REG_CENTERRHW(ij_regid[IJ_PERSP_CENTER_RHW]));
550 OUT_RING(
551 ring,
552 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
553 A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
554 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(
555 ij_regid[IJ_PERSP_CENTROID]) |
556 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(
557 ij_regid[IJ_LINEAR_CENTROID]));
558 OUT_RING(
559 ring,
560 A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
561 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
562 A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
563 A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
564
565 OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
566 OUT_RING(
567 ring,
568 COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
569 0x40002 | /* XXX set pretty much everywhere */
570 COND(s[FS].instrlen != 0, A5XX_SP_FS_CTRL_REG0_BUFFER) |
571 A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
572 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
573 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
574 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(s[FS].v)) |
575 COND(s[FS].v->need_pixlod, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
576
577 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
578 OUT_RING(ring, 0x020fffff); /* XXX */
579
580 OUT_PKT4(ring, REG_A5XX_VPC_GS_SIV_CNTL, 1);
581 OUT_RING(ring, 0x0000ffff); /* XXX */
582
583 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
584 OUT_RING(ring, 0x00000010); /* XXX */
585
586 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
587 OUT_RING(ring,
588 CONDREG(ij_regid[IJ_PERSP_PIXEL], A5XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
589 CONDREG(ij_regid[IJ_PERSP_CENTROID],
590 A5XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
591 CONDREG(ij_regid[IJ_PERSP_SAMPLE],
592 A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
593 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
594 CONDREG(ij_regid[IJ_LINEAR_CENTROID],
595 A5XX_GRAS_CNTL_IJ_LINEAR_CENTROID) |
596 CONDREG(ij_regid[IJ_LINEAR_SAMPLE],
597 A5XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) |
598 COND(s[FS].v->fragcoord_compmask != 0,
599 A5XX_GRAS_CNTL_COORD_MASK(s[FS].v->fragcoord_compmask) |
600 A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
601 COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
602 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL));
603
604 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2);
605 OUT_RING(
606 ring,
607 CONDREG(ij_regid[IJ_PERSP_PIXEL],
608 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
609 CONDREG(ij_regid[IJ_PERSP_CENTROID],
610 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
611 CONDREG(ij_regid[IJ_PERSP_SAMPLE],
612 A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
613 CONDREG(ij_regid[IJ_LINEAR_PIXEL],
614 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
615 CONDREG(ij_regid[IJ_LINEAR_CENTROID],
616 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID) |
617 CONDREG(ij_regid[IJ_LINEAR_SAMPLE],
618 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) |
619 COND(s[FS].v->fragcoord_compmask != 0,
620 A5XX_RB_RENDER_CONTROL0_COORD_MASK(s[FS].v->fragcoord_compmask) |
621 A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
622 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
623 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL));
624 OUT_RING(ring,
625 CONDREG(samp_mask_regid, A5XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
626 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS) |
627 CONDREG(samp_id_regid, A5XX_RB_RENDER_CONTROL1_SAMPLEID));
628
629 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_REG(0), 8);
630 for (i = 0; i < 8; i++) {
631 OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
632 COND(color_regid[i] & HALF_REG_ID,
633 A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
634 }
635
636 OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
637 OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
638 A5XX_VPC_PACK_PSIZELOC(psize_loc));
639
640 if (!emit->binning_pass) {
641 uint32_t vinterp[8], vpsrepl[8];
642
643 memset(vinterp, 0, sizeof(vinterp));
644 memset(vpsrepl, 0, sizeof(vpsrepl));
645
646 /* looks like we need to do int varyings in the frag
647 * shader on a5xx (no flatshad reg? or a420.0 bug?):
648 *
649 * (sy)(ss)nop
650 * (sy)ldlv.u32 r0.x,l[r0.x], 1
651 * ldlv.u32 r0.y,l[r0.x+1], 1
652 * (ss)bary.f (ei)r63.x, 0, r0.x
653 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
654 * (rpt5)nop
655 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
656 *
657 * Possibly on later a5xx variants we'll be able to use
658 * something like the code below instead of workaround
659 * in the shader:
660 */
661 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
662 for (j = -1;
663 (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count;) {
664 /* NOTE: varyings are packed, so if compmask is 0xb
665 * then first, third, and fourth component occupy
666 * three consecutive varying slots:
667 */
668 unsigned compmask = s[FS].v->inputs[j].compmask;
669
670 uint32_t inloc = s[FS].v->inputs[j].inloc;
671
672 if (s[FS].v->inputs[j].flat ||
673 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
674 uint32_t loc = inloc;
675
676 for (i = 0; i < 4; i++) {
677 if (compmask & (1 << i)) {
678 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
679 // flatshade[loc / 32] |= 1 << (loc % 32);
680 loc++;
681 }
682 }
683 }
684
685 bool coord_mode = emit->sprite_coord_mode;
686 if (ir3_point_sprite(s[FS].v, j, emit->sprite_coord_enable,
687 &coord_mode)) {
688 /* mask is two 2-bit fields, where:
689 * '01' -> S
690 * '10' -> T
691 * '11' -> 1 - T (flip mode)
692 */
693 unsigned mask = coord_mode ? 0b1101 : 0b1001;
694 uint32_t loc = inloc;
695 if (compmask & 0x1) {
696 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
697 loc++;
698 }
699 if (compmask & 0x2) {
700 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
701 loc++;
702 }
703 if (compmask & 0x4) {
704 /* .z <- 0.0f */
705 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
706 loc++;
707 }
708 if (compmask & 0x8) {
709 /* .w <- 1.0f */
710 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
711 loc++;
712 }
713 }
714 }
715
716 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8);
717 for (i = 0; i < 8; i++)
718 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
719
720 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8);
721 for (i = 0; i < 8; i++)
722 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
723 }
724
725 OUT_PKT4(ring, REG_A5XX_GRAS_VS_CL_CNTL, 1);
726 OUT_RING(ring, A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(clip_mask) |
727 A5XX_GRAS_VS_CL_CNTL_CULL_MASK(cull_mask));
728
729 OUT_PKT4(ring, REG_A5XX_VPC_CLIP_CNTL, 1);
730 OUT_RING(ring, A5XX_VPC_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
731 A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
732 A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
733
734 OUT_PKT4(ring, REG_A5XX_PC_CLIP_CNTL, 1);
735 OUT_RING(ring, A5XX_PC_CLIP_CNTL_CLIP_MASK(clip_mask));
736
737 if (!emit->binning_pass)
738 if (s[FS].instrlen)
739 fd5_emit_shader(ring, s[FS].v);
740
741 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_1, 5);
742 OUT_RING(ring, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
743 A5XX_VFD_CONTROL_1_REGID4INST(instance_regid) | 0xfc0000);
744 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
745 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_3 */
746 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
747 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_5 */
748 }
749
750 static struct ir3_program_state *
fd5_program_create(void * data,const struct ir3_shader_variant * bs,const struct ir3_shader_variant * vs,const struct ir3_shader_variant * hs,const struct ir3_shader_variant * ds,const struct ir3_shader_variant * gs,const struct ir3_shader_variant * fs,const struct ir3_cache_key * key)751 fd5_program_create(void *data, const struct ir3_shader_variant *bs,
752 const struct ir3_shader_variant *vs,
753 const struct ir3_shader_variant *hs,
754 const struct ir3_shader_variant *ds,
755 const struct ir3_shader_variant *gs,
756 const struct ir3_shader_variant *fs,
757 const struct ir3_cache_key *key) in_dt
758 {
759 struct fd_context *ctx = fd_context(data);
760 struct fd5_program_state *state = CALLOC_STRUCT(fd5_program_state);
761
762 tc_assert_driver_thread(ctx->tc);
763
764 state->bs = bs;
765 state->vs = vs;
766 state->fs = fs;
767
768 return &state->base;
769 }
770
771 static void
fd5_program_destroy(void * data,struct ir3_program_state * state)772 fd5_program_destroy(void *data, struct ir3_program_state *state)
773 {
774 struct fd5_program_state *so = fd5_program_state(state);
775 free(so);
776 }
777
778 static const struct ir3_cache_funcs cache_funcs = {
779 .create_state = fd5_program_create,
780 .destroy_state = fd5_program_destroy,
781 };
782
783 void
fd5_prog_init(struct pipe_context * pctx)784 fd5_prog_init(struct pipe_context *pctx)
785 {
786 struct fd_context *ctx = fd_context(pctx);
787
788 ctx->shader_cache = ir3_cache_create(&cache_funcs, ctx);
789 ir3_prog_init(pctx);
790 fd_prog_init(pctx);
791 }
792