1 /*
2 * Copyright (C) 2019 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "drm/freedreno_ringbuffer.h"
28 #define FD_BO_NO_HARDPIN 1
29
30 #include "pipe/p_state.h"
31 #include "util/u_dump.h"
32 #include "u_tracepoints.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_tracepoints.h"
36
37 #include "fd6_barrier.h"
38 #include "fd6_compute.h"
39 #include "fd6_const.h"
40 #include "fd6_context.h"
41 #include "fd6_emit.h"
42 #include "fd6_pack.h"
43
44 /* maybe move to fd6_program? */
45 template <chip CHIP>
46 static void
cs_program_emit(struct fd_context * ctx,struct fd_ringbuffer * ring,struct ir3_shader_variant * v)47 cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
48 struct ir3_shader_variant *v)
49 assert_dt
50 {
51 const struct ir3_info *i = &v->info;
52 enum a6xx_threadsize thrsz_cs = i->double_threadsize ? THREAD128 : THREAD64;
53
54 OUT_REG(ring, HLSQ_INVALIDATE_CMD(CHIP, .vs_state = true, .hs_state = true,
55 .ds_state = true, .gs_state = true,
56 .fs_state = true, .cs_state = true,
57 .cs_ibo = true, .gfx_ibo = true, ));
58
59 OUT_REG(ring, HLSQ_CS_CNTL(
60 CHIP,
61 .constlen = v->constlen,
62 .enabled = true,
63 ));
64
65 OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 1);
66 OUT_RING(ring, A6XX_SP_CS_CONFIG_ENABLED |
67 COND(v->bindless_tex, A6XX_SP_CS_CONFIG_BINDLESS_TEX) |
68 COND(v->bindless_samp, A6XX_SP_CS_CONFIG_BINDLESS_SAMP) |
69 COND(v->bindless_ibo, A6XX_SP_CS_CONFIG_BINDLESS_IBO) |
70 COND(v->bindless_ubo, A6XX_SP_CS_CONFIG_BINDLESS_UBO) |
71 A6XX_SP_CS_CONFIG_NIBO(ir3_shader_nibo(v)) |
72 A6XX_SP_CS_CONFIG_NTEX(v->num_samp) |
73 A6XX_SP_CS_CONFIG_NSAMP(v->num_samp)); /* SP_CS_CONFIG */
74
75 uint32_t local_invocation_id, work_group_id;
76 local_invocation_id =
77 ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
78 work_group_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_WORKGROUP_ID);
79
80 enum a6xx_threadsize thrsz = ctx->screen->info->a6xx.supports_double_threadsize ? thrsz_cs : THREAD128;
81 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2);
82 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
83 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
84 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
85 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
86 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
87 A6XX_HLSQ_CS_CNTL_1_THREADSIZE(thrsz));
88 if (!ctx->screen->info->a6xx.supports_double_threadsize) {
89 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL_0, 1);
90 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_0_THREADSIZE(thrsz_cs));
91 }
92
93 if (ctx->screen->info->a6xx.has_lpac) {
94 OUT_PKT4(ring, REG_A6XX_SP_CS_CNTL_0, 2);
95 OUT_RING(ring, A6XX_SP_CS_CNTL_0_WGIDCONSTID(work_group_id) |
96 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
97 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
98 A6XX_SP_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
99 OUT_RING(ring, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
100 A6XX_SP_CS_CNTL_1_THREADSIZE(thrsz));
101 }
102
103 fd6_emit_shader(ctx, ring, v);
104 }
105
106 template <chip CHIP>
107 static void
fd6_launch_grid(struct fd_context * ctx,const struct pipe_grid_info * info)108 fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
109 {
110 struct fd6_compute_state *cs = (struct fd6_compute_state *)ctx->compute;
111 struct fd_ringbuffer *ring = ctx->batch->draw;
112
113 if (unlikely(!cs->v)) {
114 struct ir3_shader_state *hwcso = (struct ir3_shader_state *)cs->hwcso;
115 struct ir3_shader_key key = {};
116
117 cs->v = ir3_shader_variant(ir3_get_shader(hwcso), key, false, &ctx->debug);
118 if (!cs->v)
119 return;
120
121 cs->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
122 cs_program_emit<CHIP>(ctx, cs->stateobj, cs->v);
123
124 cs->user_consts_cmdstream_size = fd6_user_consts_cmdstream_size(cs->v);
125 }
126
127 trace_start_compute(&ctx->batch->trace, ring, !!info->indirect, info->work_dim,
128 info->block[0], info->block[1], info->block[2],
129 info->grid[0], info->grid[1], info->grid[2],
130 cs->v->shader_id);
131
132 if (ctx->batch->barrier)
133 fd6_barrier_flush(ctx->batch);
134
135 bool emit_instrlen_workaround =
136 cs->v->instrlen > ctx->screen->info->a6xx.instr_cache_size;
137
138 /* There appears to be a HW bug where in some rare circumstances it appears
139 * to accidentally use the FS instrlen instead of the CS instrlen, which
140 * affects all known gens. Based on various experiments it appears that the
141 * issue is that when prefetching a branch destination and there is a cache
142 * miss, when fetching from memory the HW bounds-checks the fetch against
143 * SP_CS_INSTRLEN, except when one of the two register contexts is active
144 * it accidentally fetches SP_FS_INSTRLEN from the other (inactive)
145 * context. To workaround it we set the FS instrlen here and do a dummy
146 * event to roll the context (because it fetches SP_FS_INSTRLEN from the
147 * "wrong" context). Because the bug seems to involve cache misses, we
148 * don't emit this if the entire CS program fits in cache, which will
149 * hopefully be the majority of cases.
150 *
151 * See https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19023
152 */
153 if (emit_instrlen_workaround) {
154 OUT_REG(ring, A6XX_SP_FS_INSTRLEN(cs->v->instrlen));
155 fd6_event_write(ctx->batch, ring, LABEL, false);
156 }
157
158 if (ctx->gen_dirty)
159 fd6_emit_cs_state<CHIP>(ctx, ring, cs);
160
161 if (ctx->gen_dirty & BIT(FD6_GROUP_CONST))
162 fd6_emit_cs_user_consts(ctx, ring, cs);
163
164 if (cs->v->need_driver_params || info->input)
165 fd6_emit_cs_driver_params(ctx, ring, cs, info);
166
167 OUT_PKT7(ring, CP_SET_MARKER, 1);
168 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
169
170 uint32_t shared_size =
171 MAX2(((int)(cs->v->cs.req_local_mem + info->variable_shared_mem) - 1) / 1024, 1);
172 OUT_PKT4(ring, REG_A6XX_SP_CS_UNKNOWN_A9B1, 1);
173 OUT_RING(ring, A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(shared_size) |
174 A6XX_SP_CS_UNKNOWN_A9B1_UNK6);
175
176 if (ctx->screen->info->a6xx.has_lpac) {
177 OUT_PKT4(ring, REG_A6XX_HLSQ_CS_UNKNOWN_B9D0, 1);
178 OUT_RING(ring, A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(shared_size) |
179 A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6);
180 }
181
182 const unsigned *local_size =
183 info->block; // v->shader->nir->info->workgroup_size;
184 const unsigned *num_groups = info->grid;
185 /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
186 const unsigned work_dim = info->work_dim ? info->work_dim : 3;
187
188 OUT_REG(ring,
189 HLSQ_CS_NDRANGE_0(
190 CHIP,
191 .kerneldim = work_dim,
192 .localsizex = local_size[0] - 1,
193 .localsizey = local_size[1] - 1,
194 .localsizez = local_size[2] - 1,
195 ),
196 HLSQ_CS_NDRANGE_1(
197 CHIP,
198 .globalsize_x = local_size[0] * num_groups[0],
199 ),
200 HLSQ_CS_NDRANGE_2(CHIP, .globaloff_x = 0),
201 HLSQ_CS_NDRANGE_3(
202 CHIP,
203 .globalsize_y = local_size[1] * num_groups[1],
204 ),
205 HLSQ_CS_NDRANGE_4(CHIP, .globaloff_y = 0),
206 HLSQ_CS_NDRANGE_5(
207 CHIP,
208 .globalsize_z = local_size[2] * num_groups[2],
209 ),
210 HLSQ_CS_NDRANGE_6(CHIP, .globaloff_z = 0),
211 );
212
213 OUT_REG(ring,
214 HLSQ_CS_KERNEL_GROUP_X(CHIP, 1),
215 HLSQ_CS_KERNEL_GROUP_Y(CHIP, 1),
216 HLSQ_CS_KERNEL_GROUP_Z(CHIP, 1),
217 );
218
219 if (info->indirect) {
220 struct fd_resource *rsc = fd_resource(info->indirect);
221
222 OUT_PKT7(ring, CP_EXEC_CS_INDIRECT, 4);
223 OUT_RING(ring, 0x00000000);
224 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */
225 OUT_RING(ring,
226 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size[0] - 1) |
227 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size[1] - 1) |
228 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size[2] - 1));
229 } else {
230 OUT_PKT7(ring, CP_EXEC_CS, 4);
231 OUT_RING(ring, 0x00000000);
232 OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(info->grid[0]));
233 OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(info->grid[1]));
234 OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(info->grid[2]));
235 }
236
237 trace_end_compute(&ctx->batch->trace, ring);
238
239 fd_context_all_clean(ctx);
240 }
241
242 static void *
fd6_compute_state_create(struct pipe_context * pctx,const struct pipe_compute_state * cso)243 fd6_compute_state_create(struct pipe_context *pctx,
244 const struct pipe_compute_state *cso)
245 {
246 struct fd6_compute_state *hwcso =
247 (struct fd6_compute_state *)calloc(1, sizeof(*hwcso));
248 hwcso->hwcso = ir3_shader_compute_state_create(pctx, cso);
249 return hwcso;
250 }
251
252 static void
fd6_compute_state_delete(struct pipe_context * pctx,void * _hwcso)253 fd6_compute_state_delete(struct pipe_context *pctx, void *_hwcso)
254 {
255 struct fd6_compute_state *hwcso = (struct fd6_compute_state *)_hwcso;
256 ir3_shader_state_delete(pctx, hwcso->hwcso);
257 if (hwcso->stateobj)
258 fd_ringbuffer_del(hwcso->stateobj);
259 free(hwcso);
260 }
261
262 template <chip CHIP>
263 void
fd6_compute_init(struct pipe_context * pctx)264 fd6_compute_init(struct pipe_context *pctx)
265 disable_thread_safety_analysis
266 {
267 struct fd_context *ctx = fd_context(pctx);
268
269 ctx->launch_grid = fd6_launch_grid<CHIP>;
270 pctx->create_compute_state = fd6_compute_state_create;
271 pctx->delete_compute_state = fd6_compute_state_delete;
272 }
273
274 /* Teach the compiler about needed variants: */
275 template void fd6_compute_init<A6XX>(struct pipe_context *pctx);
276 template void fd6_compute_init<A7XX>(struct pipe_context *pctx);
277