1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #define FD_BO_NO_HARDPIN 1
29
30 #include "pipe/p_state.h"
31 #include "util/format/u_format.h"
32 #include "util/u_helpers.h"
33 #include "util/u_memory.h"
34 #include "util/u_string.h"
35 #include "util/u_viewport.h"
36
37 #include "freedreno_query_hw.h"
38 #include "freedreno_resource.h"
39 #include "freedreno_state.h"
40 #include "freedreno_tracepoints.h"
41
42 #include "fd6_blend.h"
43 #include "fd6_const.h"
44 #include "fd6_context.h"
45 #include "fd6_compute.h"
46 #include "fd6_emit.h"
47 #include "fd6_image.h"
48 #include "fd6_pack.h"
49 #include "fd6_program.h"
50 #include "fd6_rasterizer.h"
51 #include "fd6_texture.h"
52 #include "fd6_zsa.h"
53
54 /* Helper to get tex stateobj.
55 */
56 static struct fd_ringbuffer *
tex_state(struct fd_context * ctx,enum pipe_shader_type type)57 tex_state(struct fd_context *ctx, enum pipe_shader_type type)
58 assert_dt
59 {
60 if (ctx->tex[type].num_textures == 0)
61 return NULL;
62
63 return fd_ringbuffer_ref(fd6_texture_state(ctx, type)->stateobj);
64 }
65
66 static struct fd_ringbuffer *
build_vbo_state(struct fd6_emit * emit)67 build_vbo_state(struct fd6_emit *emit) assert_dt
68 {
69 const struct fd_vertex_state *vtx = &emit->ctx->vtx;
70
71 const unsigned cnt = vtx->vertexbuf.count;
72 const unsigned dwords = cnt * 4; /* per vbo: reg64 + one reg32 + pkt hdr */
73
74 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
75 emit->ctx->batch->submit, 4 * dwords, FD_RINGBUFFER_STREAMING);
76
77 for (int32_t j = 0; j < cnt; j++) {
78 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 3);
79 const struct pipe_vertex_buffer *vb = &vtx->vertexbuf.vb[j];
80 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
81 if (rsc == NULL) {
82 OUT_RING(ring, 0);
83 OUT_RING(ring, 0);
84 OUT_RING(ring, 0);
85 } else {
86 uint32_t off = vb->buffer_offset;
87 uint32_t size = vb->buffer.resource->width0 - off;
88
89 OUT_RELOC(ring, rsc->bo, off, 0, 0);
90 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
91 }
92 }
93
94 return ring;
95 }
96
97 static enum a6xx_ztest_mode
compute_ztest_mode(struct fd6_emit * emit,bool lrz_valid)98 compute_ztest_mode(struct fd6_emit *emit, bool lrz_valid) assert_dt
99 {
100 if (emit->prog->lrz_mask.z_mode != A6XX_INVALID_ZTEST)
101 return emit->prog->lrz_mask.z_mode;
102
103 struct fd_context *ctx = emit->ctx;
104 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
105 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
106 const struct ir3_shader_variant *fs = emit->fs;
107
108 if (!zsa->base.depth_enabled) {
109 return A6XX_LATE_Z;
110 } else if ((fs->has_kill || zsa->alpha_test) &&
111 (zsa->writes_zs || !pfb->zsbuf)) {
112 /* Slightly odd, but seems like the hw wants us to select
113 * LATE_Z mode if there is no depth buffer + discard. Either
114 * that, or when occlusion query is enabled. See:
115 *
116 * dEQP-GLES31.functional.fbo.no_attachments.*
117 */
118 return lrz_valid ? A6XX_EARLY_LRZ_LATE_Z : A6XX_LATE_Z;
119 } else {
120 return A6XX_EARLY_Z;
121 }
122 }
123
124 /**
125 * Calculate normalized LRZ state based on zsa/prog/blend state, updating
126 * the zsbuf's lrz state as necessary to detect the cases where we need
127 * to invalidate lrz.
128 */
129 static struct fd6_lrz_state
compute_lrz_state(struct fd6_emit * emit)130 compute_lrz_state(struct fd6_emit *emit) assert_dt
131 {
132 struct fd_context *ctx = emit->ctx;
133 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
134 struct fd6_lrz_state lrz;
135
136 if (!pfb->zsbuf) {
137 memset(&lrz, 0, sizeof(lrz));
138 lrz.z_mode = compute_ztest_mode(emit, false);
139 return lrz;
140 }
141
142 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
143 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
144 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
145 bool reads_dest = blend->reads_dest;
146
147 lrz = zsa->lrz;
148
149 lrz.val &= emit->prog->lrz_mask.val;
150
151 /* normalize lrz state: */
152 if (reads_dest || blend->base.alpha_to_coverage) {
153 lrz.write = false;
154 }
155
156 /* Unwritten channels *that actually exist* are a form of blending
157 * reading the dest from the PoV of LRZ, but the valid dst channels
158 * isn't known when blend CSO is constructed so we need to handle
159 * that here.
160 */
161 if (ctx->all_mrt_channel_mask & ~blend->all_mrt_write_mask) {
162 lrz.write = false;
163 reads_dest = true;
164 }
165
166 /* Writing depth with blend enabled means we need to invalidate LRZ,
167 * because the written depth value could mean that a later draw with
168 * depth enabled (where we would otherwise write LRZ) could have
169 * fragments which don't pass the depth test due to this draw. For
170 * example, consider this sequence of draws, with depth mode GREATER:
171 *
172 * draw A:
173 * z=0.1, fragments pass
174 * draw B:
175 * z=0.4, fragments pass
176 * blend enabled (LRZ write disabled)
177 * depth write enabled
178 * draw C:
179 * z=0.2, fragments don't pass
180 * blend disabled
181 * depth write enabled
182 *
183 * Normally looking at the state in draw C, we'd assume we could
184 * enable LRZ write. But this would cause early-z/lrz to discard
185 * fragments from draw A which should be visible due to draw B.
186 */
187 if (reads_dest && zsa->writes_z && ctx->screen->driconf.conservative_lrz) {
188 if (!zsa->perf_warn_blend && rsc->lrz_valid) {
189 perf_debug_ctx(ctx, "Invalidating LRZ due to blend+depthwrite");
190 zsa->perf_warn_blend = true;
191 }
192 rsc->lrz_valid = false;
193 }
194
195 /* if we change depthfunc direction, bail out on using LRZ. The
196 * LRZ buffer encodes a min/max depth value per block, but if
197 * we switch from GT/GE <-> LT/LE, those values cannot be
198 * interpreted properly.
199 */
200 if (zsa->base.depth_enabled && (rsc->lrz_direction != FD_LRZ_UNKNOWN) &&
201 (rsc->lrz_direction != lrz.direction)) {
202 if (!zsa->perf_warn_zdir && rsc->lrz_valid) {
203 perf_debug_ctx(ctx, "Invalidating LRZ due to depth test direction change");
204 zsa->perf_warn_zdir = true;
205 }
206 rsc->lrz_valid = false;
207 }
208
209 if (zsa->invalidate_lrz || !rsc->lrz_valid) {
210 rsc->lrz_valid = false;
211 memset(&lrz, 0, sizeof(lrz));
212 }
213
214 lrz.z_mode = compute_ztest_mode(emit, rsc->lrz_valid);
215
216 /* Once we start writing to the real depth buffer, we lock in the
217 * direction for LRZ.. if we have to skip a LRZ write for any
218 * reason, it is still safe to have LRZ until there is a direction
219 * reversal. Prior to the reversal, since we disabled LRZ writes
220 * in the "unsafe" cases, this just means that the LRZ test may
221 * not early-discard some things that end up not passing a later
222 * test (ie. be overly concervative). But once you have a reversal
223 * of direction, it is possible to increase/decrease the z value
224 * to the point where the overly-conservative test is incorrect.
225 */
226 if (zsa->base.depth_writemask) {
227 rsc->lrz_direction = lrz.direction;
228 }
229
230 return lrz;
231 }
232
233 static struct fd_ringbuffer *
build_lrz(struct fd6_emit * emit)234 build_lrz(struct fd6_emit *emit) assert_dt
235 {
236 struct fd_context *ctx = emit->ctx;
237 struct fd6_context *fd6_ctx = fd6_context(ctx);
238 struct fd6_lrz_state lrz = compute_lrz_state(emit);
239
240 /* If the LRZ state has not changed, we can skip the emit: */
241 if (!ctx->last.dirty && (fd6_ctx->last.lrz.val == lrz.val))
242 return NULL;
243
244 fd6_ctx->last.lrz = lrz;
245
246 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
247 ctx->batch->submit, 8 * 4, FD_RINGBUFFER_STREAMING);
248
249 OUT_REG(ring,
250 A6XX_GRAS_LRZ_CNTL(.enable = lrz.enable, .lrz_write = lrz.write,
251 .greater = lrz.direction == FD_LRZ_GREATER,
252 .z_test_enable = lrz.test,
253 .z_bounds_enable = lrz.z_bounds_enable, ));
254 OUT_REG(ring, A6XX_RB_LRZ_CNTL(.enable = lrz.enable, ));
255
256 OUT_REG(ring, A6XX_RB_DEPTH_PLANE_CNTL(.z_mode = lrz.z_mode, ));
257
258 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_PLANE_CNTL(.z_mode = lrz.z_mode, ));
259
260 return ring;
261 }
262
263 static struct fd_ringbuffer *
build_scissor(struct fd6_emit * emit)264 build_scissor(struct fd6_emit *emit) assert_dt
265 {
266 struct fd_context *ctx = emit->ctx;
267 struct pipe_scissor_state *scissors = fd_context_get_scissor(ctx);
268 unsigned num_viewports = emit->prog->num_viewports;
269
270 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
271 emit->ctx->batch->submit, (1 + (2 * num_viewports)) * 4, FD_RINGBUFFER_STREAMING);
272
273 OUT_PKT4(ring, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0), 2 * num_viewports);
274 for (unsigned i = 0; i < num_viewports; i++) {
275 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(scissors[i].minx) |
276 A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(scissors[i].miny));
277 OUT_RING(ring, A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(scissors[i].maxx) |
278 A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(scissors[i].maxy));
279 }
280
281 return ring;
282 }
283
284 /* Combination of FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER_DISCARD |
285 * FD_DIRTY_PROG | FD_DIRTY_DUAL_BLEND
286 */
287 static struct fd_ringbuffer *
build_prog_fb_rast(struct fd6_emit * emit)288 build_prog_fb_rast(struct fd6_emit *emit) assert_dt
289 {
290 struct fd_context *ctx = emit->ctx;
291 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
292 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
293 const struct ir3_shader_variant *fs = emit->fs;
294
295 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
296 ctx->batch->submit, 9 * 4, FD_RINGBUFFER_STREAMING);
297
298 unsigned nr = pfb->nr_cbufs;
299
300 if (ctx->rasterizer->rasterizer_discard)
301 nr = 0;
302
303 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
304
305 if (blend->use_dual_src_blend)
306 nr++;
307
308 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
309 OUT_RING(ring, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
310 COND(fs->writes_smask && pfb->samples > 1,
311 A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
312 COND(fs->writes_stencilref,
313 A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF) |
314 COND(blend->use_dual_src_blend,
315 A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
316 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
317
318 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
319 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
320
321 unsigned mrt_components = 0;
322 for (unsigned i = 0; i < pfb->nr_cbufs; i++) {
323 if (!pfb->cbufs[i])
324 continue;
325 mrt_components |= 0xf << (i * 4);
326 }
327
328 /* dual source blending has an extra fs output in the 2nd slot */
329 if (blend->use_dual_src_blend)
330 mrt_components |= 0xf << 4;
331
332 mrt_components &= prog->mrt_components;
333
334 OUT_REG(ring, A6XX_SP_FS_RENDER_COMPONENTS(.dword = mrt_components));
335 OUT_REG(ring, A6XX_RB_RENDER_COMPONENTS(.dword = mrt_components));
336
337 return ring;
338 }
339
340 static struct fd_ringbuffer *
build_blend_color(struct fd6_emit * emit)341 build_blend_color(struct fd6_emit *emit) assert_dt
342 {
343 struct fd_context *ctx = emit->ctx;
344 struct pipe_blend_color *bcolor = &ctx->blend_color;
345 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
346 ctx->batch->submit, 5 * 4, FD_RINGBUFFER_STREAMING);
347
348 OUT_REG(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]),
349 A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]),
350 A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]),
351 A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
352
353 return ring;
354 }
355
356 static struct fd_ringbuffer *
build_sample_locations(struct fd6_emit * emit)357 build_sample_locations(struct fd6_emit *emit)
358 assert_dt
359 {
360 struct fd_context *ctx = emit->ctx;
361
362 if (!ctx->sample_locations_enabled) {
363 struct fd6_context *fd6_ctx = fd6_context(ctx);
364 return fd_ringbuffer_ref(fd6_ctx->sample_locations_disable_stateobj);
365 }
366
367 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
368 ctx->batch->submit, 9 * 4, FD_RINGBUFFER_STREAMING);
369
370 uint32_t sample_locations = 0;
371 for (int i = 0; i < 4; i++) {
372 float x = (ctx->sample_locations[i] & 0xf) / 16.0f;
373 float y = (16 - (ctx->sample_locations[i] >> 4)) / 16.0f;
374
375 x = CLAMP(x, 0.0f, 0.9375f);
376 y = CLAMP(y, 0.0f, 0.9375f);
377
378 sample_locations |=
379 (A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(x) |
380 A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(y)) << i*8;
381 }
382
383 OUT_REG(ring, A6XX_GRAS_SAMPLE_CONFIG(.location_enable = true),
384 A6XX_GRAS_SAMPLE_LOCATION_0(.dword = sample_locations));
385
386 OUT_REG(ring, A6XX_RB_SAMPLE_CONFIG(.location_enable = true),
387 A6XX_RB_SAMPLE_LOCATION_0(.dword = sample_locations));
388
389 OUT_REG(ring, A6XX_SP_TP_SAMPLE_CONFIG(.location_enable = true),
390 A6XX_SP_TP_SAMPLE_LOCATION_0(.dword = sample_locations));
391
392 return ring;
393 }
394
395 static void
fd6_emit_streamout(struct fd_ringbuffer * ring,struct fd6_emit * emit)396 fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
397 {
398 struct fd_context *ctx = emit->ctx;
399 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
400 const struct ir3_stream_output_info *info = prog->stream_output;
401 struct fd_streamout_stateobj *so = &ctx->streamout;
402 unsigned streamout_mask = 0;
403
404 if (!info)
405 return;
406
407 for (unsigned i = 0; i < so->num_targets; i++) {
408 struct fd_stream_output_target *target =
409 fd_stream_output_target(so->targets[i]);
410
411 if (!target)
412 continue;
413
414 target->stride = info->stride[i];
415
416 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE(i), 3);
417 /* VPC_SO[i].BUFFER_BASE_LO: */
418 OUT_RELOC(ring, fd_resource(target->base.buffer)->bo, 0, 0, 0);
419 OUT_RING(ring, target->base.buffer_size + target->base.buffer_offset);
420
421 struct fd_bo *offset_bo = fd_resource(target->offset_buf)->bo;
422
423 if (so->reset & (1 << i)) {
424 assert(so->offsets[i] == 0);
425
426 OUT_PKT7(ring, CP_MEM_WRITE, 3);
427 OUT_RELOC(ring, offset_bo, 0, 0, 0);
428 OUT_RING(ring, target->base.buffer_offset);
429
430 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 1);
431 OUT_RING(ring, target->base.buffer_offset);
432 } else {
433 OUT_PKT7(ring, CP_MEM_TO_REG, 3);
434 OUT_RING(ring, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
435 CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
436 CP_MEM_TO_REG_0_CNT(0));
437 OUT_RELOC(ring, offset_bo, 0, 0, 0);
438 }
439
440 // After a draw HW would write the new offset to offset_bo
441 OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE(i), 2);
442 OUT_RELOC(ring, offset_bo, 0, 0, 0);
443
444 so->reset &= ~(1 << i);
445
446 streamout_mask |= (1 << i);
447 }
448
449 if (streamout_mask) {
450 fd6_state_add_group(&emit->state, prog->streamout_stateobj, FD6_GROUP_SO);
451 } else if (ctx->last.streamout_mask != 0) {
452 /* If we transition from a draw with streamout to one without, turn
453 * off streamout.
454 */
455 fd6_state_add_group(&emit->state, fd6_context(ctx)->streamout_disable_stateobj,
456 FD6_GROUP_SO);
457 }
458
459 /* Make sure that any use of our TFB outputs (indirect draw source or shader
460 * UBO reads) comes after the TFB output is written. From the GL 4.6 core
461 * spec:
462 *
463 * "Buffers should not be bound or in use for both transform feedback and
464 * other purposes in the GL. Specifically, if a buffer object is
465 * simultaneously bound to a transform feedback buffer binding point
466 * and elsewhere in the GL, any writes to or reads from the buffer
467 * generate undefined values."
468 *
469 * So we idle whenever SO buffers change. Note that this function is called
470 * on every draw with TFB enabled, so check the dirty flag for the buffers
471 * themselves.
472 */
473 if (ctx->dirty & FD_DIRTY_STREAMOUT)
474 OUT_WFI5(ring);
475
476 ctx->last.streamout_mask = streamout_mask;
477 emit->streamout_mask = streamout_mask;
478 }
479
480 /**
481 * Stuff that less frequently changes and isn't (yet) moved into stategroups
482 */
483 static void
fd6_emit_non_ring(struct fd_ringbuffer * ring,struct fd6_emit * emit)484 fd6_emit_non_ring(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
485 {
486 struct fd_context *ctx = emit->ctx;
487 const enum fd_dirty_3d_state dirty = ctx->dirty;
488 unsigned num_viewports = emit->prog->num_viewports;
489
490 if (dirty & FD_DIRTY_STENCIL_REF) {
491 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
492
493 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
494 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
495 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
496 }
497
498 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_PROG)) {
499 for (unsigned i = 0; i < num_viewports; i++) {
500 struct pipe_scissor_state *scissor = &ctx->viewport_scissor[i];
501 struct pipe_viewport_state *vp = & ctx->viewport[i];
502
503 OUT_REG(ring, A6XX_GRAS_CL_VPORT_XOFFSET(i, vp->translate[0]),
504 A6XX_GRAS_CL_VPORT_XSCALE(i, vp->scale[0]),
505 A6XX_GRAS_CL_VPORT_YOFFSET(i, vp->translate[1]),
506 A6XX_GRAS_CL_VPORT_YSCALE(i, vp->scale[1]),
507 A6XX_GRAS_CL_VPORT_ZOFFSET(i, vp->translate[2]),
508 A6XX_GRAS_CL_VPORT_ZSCALE(i, vp->scale[2]));
509
510 OUT_REG(
511 ring,
512 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(i,
513 .x = scissor->minx,
514 .y = scissor->miny),
515 A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(i,
516 .x = scissor->maxx,
517 .y = scissor->maxy));
518 }
519
520 OUT_REG(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ(.horz = ctx->guardband.x,
521 .vert = ctx->guardband.y));
522 }
523
524 /* The clamp ranges are only used when the rasterizer wants depth
525 * clamping.
526 */
527 if ((dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) &&
528 fd_depth_clamp_enabled(ctx)) {
529 for (unsigned i = 0; i < num_viewports; i++) {
530 struct pipe_viewport_state *vp = & ctx->viewport[i];
531 float zmin, zmax;
532
533 util_viewport_zmin_zmax(vp, ctx->rasterizer->clip_halfz,
534 &zmin, &zmax);
535
536 OUT_REG(ring, A6XX_GRAS_CL_Z_CLAMP_MIN(i, zmin),
537 A6XX_GRAS_CL_Z_CLAMP_MAX(i, zmax));
538
539 /* TODO: what to do about this and multi viewport ? */
540 if (i == 0)
541 OUT_REG(ring, A6XX_RB_Z_CLAMP_MIN(zmin), A6XX_RB_Z_CLAMP_MAX(zmax));
542 }
543 }
544 }
545
546 static struct fd_ringbuffer*
build_prim_mode(struct fd6_emit * emit,struct fd_context * ctx,bool gmem)547 build_prim_mode(struct fd6_emit *emit, struct fd_context *ctx, bool gmem)
548 assert_dt
549 {
550 struct fd_ringbuffer *ring =
551 fd_submit_new_ringbuffer(emit->ctx->batch->submit, 2 * 4, FD_RINGBUFFER_STREAMING);
552 uint32_t prim_mode = NO_FLUSH;
553 if (emit->fs->fs.uses_fbfetch_output) {
554 if (gmem) {
555 prim_mode = (ctx->blend->blend_coherent || emit->fs->fs.fbfetch_coherent)
556 ? FLUSH_PER_OVERLAP : NO_FLUSH;
557 } else {
558 prim_mode = FLUSH_PER_OVERLAP_AND_OVERWRITE;
559 }
560 } else {
561 prim_mode = NO_FLUSH;
562 }
563 OUT_REG(ring, A6XX_GRAS_SC_CNTL(.ccusinglecachelinesize = 2,
564 .single_prim_mode = (enum a6xx_single_prim_mode)prim_mode));
565 return ring;
566 }
567
568 template <chip CHIP, fd6_pipeline_type PIPELINE>
569 void
fd6_emit_3d_state(struct fd_ringbuffer * ring,struct fd6_emit * emit)570 fd6_emit_3d_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
571 {
572 struct fd_context *ctx = emit->ctx;
573 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
574 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
575 const struct ir3_shader_variant *fs = emit->fs;
576
577 emit_marker6(ring, 5);
578
579 /* Special case, we need to re-emit bindless FS state w/ the
580 * fb-read state appended:
581 */
582 if ((emit->dirty_groups & BIT(FD6_GROUP_PROG)) && fs->fb_read) {
583 ctx->batch->gmem_reason |= FD_GMEM_FB_READ;
584 emit->dirty_groups |= BIT(FD6_GROUP_FS_BINDLESS);
585 }
586
587 u_foreach_bit (b, emit->dirty_groups) {
588 enum fd6_state_id group = (enum fd6_state_id)b;
589 struct fd_ringbuffer *state = NULL;
590
591 switch (group) {
592 case FD6_GROUP_VTXSTATE:
593 state = fd6_vertex_stateobj(ctx->vtx.vtx)->stateobj;
594 fd6_state_add_group(&emit->state, state, FD6_GROUP_VTXSTATE);
595 break;
596 case FD6_GROUP_VBO:
597 state = build_vbo_state(emit);
598 fd6_state_take_group(&emit->state, state, FD6_GROUP_VBO);
599 break;
600 case FD6_GROUP_ZSA:
601 state = fd6_zsa_state(
602 ctx,
603 util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])),
604 fd_depth_clamp_enabled(ctx));
605 fd6_state_add_group(&emit->state, state, FD6_GROUP_ZSA);
606 break;
607 case FD6_GROUP_LRZ:
608 state = build_lrz(emit);
609 if (state)
610 fd6_state_take_group(&emit->state, state, FD6_GROUP_LRZ);
611 break;
612 case FD6_GROUP_SCISSOR:
613 state = build_scissor(emit);
614 fd6_state_take_group(&emit->state, state, FD6_GROUP_SCISSOR);
615 break;
616 case FD6_GROUP_PROG:
617 fd6_state_add_group(&emit->state, prog->config_stateobj,
618 FD6_GROUP_PROG_CONFIG);
619 fd6_state_add_group(&emit->state, prog->stateobj, FD6_GROUP_PROG);
620 fd6_state_add_group(&emit->state, prog->binning_stateobj,
621 FD6_GROUP_PROG_BINNING);
622
623 /* emit remaining streaming program state, ie. what depends on
624 * other emit state, so cannot be pre-baked.
625 */
626 fd6_state_take_group(&emit->state, fd6_program_interp_state(emit),
627 FD6_GROUP_PROG_INTERP);
628 break;
629 case FD6_GROUP_RASTERIZER:
630 state = fd6_rasterizer_state<CHIP>(ctx, emit->primitive_restart);
631 fd6_state_add_group(&emit->state, state, FD6_GROUP_RASTERIZER);
632 break;
633 case FD6_GROUP_PROG_FB_RAST:
634 state = build_prog_fb_rast(emit);
635 fd6_state_take_group(&emit->state, state, FD6_GROUP_PROG_FB_RAST);
636 break;
637 case FD6_GROUP_BLEND:
638 state = fd6_blend_variant(ctx->blend, pfb->samples, ctx->sample_mask)
639 ->stateobj;
640 fd6_state_add_group(&emit->state, state, FD6_GROUP_BLEND);
641 break;
642 case FD6_GROUP_BLEND_COLOR:
643 state = build_blend_color(emit);
644 fd6_state_take_group(&emit->state, state, FD6_GROUP_BLEND_COLOR);
645 break;
646 case FD6_GROUP_SAMPLE_LOCATIONS:
647 state = build_sample_locations(emit);
648 fd6_state_take_group(&emit->state, state, FD6_GROUP_SAMPLE_LOCATIONS);
649 break;
650 case FD6_GROUP_VS_BINDLESS:
651 state = fd6_build_bindless_state<CHIP>(ctx, PIPE_SHADER_VERTEX, false);
652 fd6_state_take_group(&emit->state, state, FD6_GROUP_VS_BINDLESS);
653 break;
654 case FD6_GROUP_HS_BINDLESS:
655 state = fd6_build_bindless_state<CHIP>(ctx, PIPE_SHADER_TESS_CTRL, false);
656 fd6_state_take_group(&emit->state, state, FD6_GROUP_HS_BINDLESS);
657 break;
658 case FD6_GROUP_DS_BINDLESS:
659 state = fd6_build_bindless_state<CHIP>(ctx, PIPE_SHADER_TESS_EVAL, false);
660 fd6_state_take_group(&emit->state, state, FD6_GROUP_DS_BINDLESS);
661 break;
662 case FD6_GROUP_GS_BINDLESS:
663 state = fd6_build_bindless_state<CHIP>(ctx, PIPE_SHADER_GEOMETRY, false);
664 fd6_state_take_group(&emit->state, state, FD6_GROUP_GS_BINDLESS);
665 break;
666 case FD6_GROUP_FS_BINDLESS:
667 state = fd6_build_bindless_state<CHIP>(ctx, PIPE_SHADER_FRAGMENT, fs->fb_read);
668 fd6_state_take_group(&emit->state, state, FD6_GROUP_FS_BINDLESS);
669 break;
670 case FD6_GROUP_CONST:
671 state = fd6_build_user_consts<PIPELINE>(emit);
672 fd6_state_take_group(&emit->state, state, FD6_GROUP_CONST);
673 break;
674 case FD6_GROUP_DRIVER_PARAMS:
675 state = fd6_build_driver_params<PIPELINE>(emit);
676 fd6_state_take_group(&emit->state, state, FD6_GROUP_DRIVER_PARAMS);
677 break;
678 case FD6_GROUP_PRIMITIVE_PARAMS:
679 if (PIPELINE == HAS_TESS_GS) {
680 state = fd6_build_tess_consts(emit);
681 fd6_state_take_group(&emit->state, state, FD6_GROUP_PRIMITIVE_PARAMS);
682 }
683 break;
684 case FD6_GROUP_VS_TEX:
685 state = tex_state(ctx, PIPE_SHADER_VERTEX);
686 fd6_state_take_group(&emit->state, state, FD6_GROUP_VS_TEX);
687 break;
688 case FD6_GROUP_HS_TEX:
689 state = tex_state(ctx, PIPE_SHADER_TESS_CTRL);
690 fd6_state_take_group(&emit->state, state, FD6_GROUP_HS_TEX);
691 break;
692 case FD6_GROUP_DS_TEX:
693 state = tex_state(ctx, PIPE_SHADER_TESS_EVAL);
694 fd6_state_take_group(&emit->state, state, FD6_GROUP_DS_TEX);
695 break;
696 case FD6_GROUP_GS_TEX:
697 state = tex_state(ctx, PIPE_SHADER_GEOMETRY);
698 fd6_state_take_group(&emit->state, state, FD6_GROUP_GS_TEX);
699 break;
700 case FD6_GROUP_FS_TEX:
701 state = tex_state(ctx, PIPE_SHADER_FRAGMENT);
702 fd6_state_take_group(&emit->state, state, FD6_GROUP_FS_TEX);
703 break;
704 case FD6_GROUP_SO:
705 fd6_emit_streamout(ring, emit);
706 break;
707 case FD6_GROUP_PRIM_MODE_SYSMEM:
708 state = build_prim_mode(emit, ctx, false);
709 fd6_state_take_group(&emit->state, state, FD6_GROUP_PRIM_MODE_SYSMEM);
710 break;
711 case FD6_GROUP_PRIM_MODE_GMEM:
712 state = build_prim_mode(emit, ctx, true);
713 fd6_state_take_group(&emit->state, state, FD6_GROUP_PRIM_MODE_GMEM);
714 break;
715 case FD6_GROUP_NON_GROUP:
716 fd6_emit_non_ring(ring, emit);
717 break;
718 default:
719 break;
720 }
721 }
722
723 fd6_state_emit(&emit->state, ring);
724 }
725
726 template void fd6_emit_3d_state<A6XX, NO_TESS_GS>(struct fd_ringbuffer *ring, struct fd6_emit *emit);
727 template void fd6_emit_3d_state<A7XX, NO_TESS_GS>(struct fd_ringbuffer *ring, struct fd6_emit *emit);
728 template void fd6_emit_3d_state<A6XX, HAS_TESS_GS>(struct fd_ringbuffer *ring, struct fd6_emit *emit);
729 template void fd6_emit_3d_state<A7XX, HAS_TESS_GS>(struct fd_ringbuffer *ring, struct fd6_emit *emit);
730
731 template <chip CHIP>
732 void
fd6_emit_cs_state(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd6_compute_state * cs)733 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
734 struct fd6_compute_state *cs)
735 {
736 struct fd6_state state = {};
737
738 /* We want CP_SET_DRAW_STATE to execute immediately, otherwise we need to
739 * emit consts as draw state groups (which otherwise has no benefit outside
740 * of GMEM 3d using viz stream from binning pass).
741 *
742 * In particular, the PROG state group sets up the configuration for the
743 * const state, so it must execute before we start loading consts, rather
744 * than be deferred until CP_EXEC_CS.
745 */
746 OUT_PKT7(ring, CP_SET_MODE, 1);
747 OUT_RING(ring, 1);
748
749 uint32_t gen_dirty = ctx->gen_dirty &
750 (BIT(FD6_GROUP_PROG) | BIT(FD6_GROUP_CS_TEX) | BIT(FD6_GROUP_CS_BINDLESS));
751
752 u_foreach_bit (b, gen_dirty) {
753 enum fd6_state_id group = (enum fd6_state_id)b;
754
755 switch (group) {
756 case FD6_GROUP_PROG:
757 fd6_state_add_group(&state, cs->stateobj, FD6_GROUP_PROG);
758 break;
759 case FD6_GROUP_CS_TEX:
760 fd6_state_take_group(
761 &state,
762 tex_state(ctx, PIPE_SHADER_COMPUTE),
763 FD6_GROUP_CS_TEX);
764 break;
765 case FD6_GROUP_CS_BINDLESS:
766 fd6_state_take_group(
767 &state,
768 fd6_build_bindless_state<CHIP>(ctx, PIPE_SHADER_COMPUTE, false),
769 FD6_GROUP_CS_BINDLESS);
770 break;
771 default:
772 /* State-group unused for compute shaders */
773 break;
774 }
775 }
776
777 fd6_state_emit(&state, ring);
778 }
779
780 void
fd6_emit_ccu_cntl(struct fd_ringbuffer * ring,struct fd_screen * screen,bool gmem)781 fd6_emit_ccu_cntl(struct fd_ringbuffer *ring, struct fd_screen *screen, bool gmem)
782 {
783 enum a6xx_ccu_cache_size cache_size = (enum a6xx_ccu_cache_size)(screen->info->a6xx.gmem_ccu_color_cache_fraction);
784 uint32_t offset = gmem ? screen->ccu_offset_gmem : screen->ccu_offset_bypass;
785 uint32_t offset_hi = offset >> 21;
786 offset &= 0x1fffff;
787
788 OUT_REG(ring,
789 A6XX_RB_CCU_CNTL(.gmem_fast_clear_disable =
790 !screen->info->a6xx.has_gmem_fast_clear,
791 .concurrent_resolve =
792 screen->info->a6xx.concurrent_resolve,
793 .depth_offset_hi = 0,
794 .color_offset_hi = offset_hi,
795 .depth_cache_size = CCU_CACHE_SIZE_FULL,
796 .depth_offset = 0,
797 .color_cache_size = cache_size,
798 .color_offset = offset,
799 ));
800 }
801
802 template void fd6_emit_cs_state<A6XX>(struct fd_context *ctx, struct fd_ringbuffer *ring, struct fd6_compute_state *cs);
803 template void fd6_emit_cs_state<A7XX>(struct fd_context *ctx, struct fd_ringbuffer *ring, struct fd6_compute_state *cs);
804
805 /* emit setup at begin of new cmdstream buffer (don't rely on previous
806 * state, there could have been a context switch between ioctls):
807 */
808 template <chip CHIP>
809 void
fd6_emit_restore(struct fd_batch * batch,struct fd_ringbuffer * ring)810 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
811 {
812 struct fd_screen *screen = batch->ctx->screen;
813
814 if (!batch->nondraw) {
815 trace_start_state_restore(&batch->trace, ring);
816 }
817
818 OUT_PKT7(ring, CP_SET_MODE, 1);
819 OUT_RING(ring, 0);
820
821 fd6_cache_inv(batch, ring);
822
823 OUT_REG(ring,
824 HLSQ_INVALIDATE_CMD(CHIP, .vs_state = true, .hs_state = true,
825 .ds_state = true, .gs_state = true,
826 .fs_state = true, .cs_state = true,
827 .cs_ibo = true, .gfx_ibo = true,
828 .cs_shared_const = true,
829 .gfx_shared_const = true,
830 .cs_bindless = 0x1f, .gfx_bindless = 0x1f));
831
832 OUT_WFI5(ring);
833
834 WRITE(REG_A6XX_RB_DBG_ECO_CNTL, screen->info->a6xx.magic.RB_DBG_ECO_CNTL);
835 WRITE(REG_A6XX_SP_FLOAT_CNTL, A6XX_SP_FLOAT_CNTL_F16_NO_INF);
836 WRITE(REG_A6XX_SP_DBG_ECO_CNTL, screen->info->a6xx.magic.SP_DBG_ECO_CNTL);
837 WRITE(REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
838 WRITE(REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
839 WRITE(REG_A6XX_TPL1_DBG_ECO_CNTL, screen->info->a6xx.magic.TPL1_DBG_ECO_CNTL);
840 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
841 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
842
843 WRITE(REG_A6XX_VPC_DBG_ECO_CNTL, screen->info->a6xx.magic.VPC_DBG_ECO_CNTL);
844 WRITE(REG_A6XX_GRAS_DBG_ECO_CNTL, screen->info->a6xx.magic.GRAS_DBG_ECO_CNTL);
845 WRITE(REG_A6XX_HLSQ_DBG_ECO_CNTL, screen->info->a6xx.magic.HLSQ_DBG_ECO_CNTL);
846 WRITE(REG_A6XX_SP_CHICKEN_BITS, screen->info->a6xx.magic.SP_CHICKEN_BITS);
847 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
848 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
849 WRITE(REG_A6XX_HLSQ_SHARED_CONSTS, 0);
850 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, screen->info->a6xx.magic.UCHE_UNKNOWN_0E12);
851 WRITE(REG_A6XX_UCHE_CLIENT_PF, screen->info->a6xx.magic.UCHE_CLIENT_PF);
852 WRITE(REG_A6XX_RB_UNKNOWN_8E01, screen->info->a6xx.magic.RB_UNKNOWN_8E01);
853 WRITE(REG_A6XX_SP_UNKNOWN_A9A8, 0);
854 WRITE(REG_A6XX_SP_MODE_CONTROL,
855 A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
856 WRITE(REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
857 WRITE(REG_A6XX_VPC_UNKNOWN_9107, 0);
858 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
859 WRITE(REG_A6XX_PC_MODE_CNTL, screen->info->a6xx.magic.PC_MODE_CNTL);
860
861 WRITE(REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL, 0);
862 WRITE(REG_A6XX_GRAS_SAMPLE_CNTL, 0);
863 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0x2);
864
865 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
866 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
867 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
868 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
869 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
870 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
871 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
872 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
873
874 WRITE(REG_A6XX_VPC_POINT_COORD_INVERT, A6XX_VPC_POINT_COORD_INVERT(0).value);
875 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
876
877 WRITE(REG_A6XX_VPC_SO_DISABLE, A6XX_VPC_SO_DISABLE(true).value);
878
879 OUT_REG(ring, PC_RASTER_CNTL(CHIP));
880
881 WRITE(REG_A6XX_PC_MULTIVIEW_CNTL, 0);
882
883 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
884
885 WRITE(REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 0);
886 WRITE(REG_A6XX_GRAS_VS_LAYER_CNTL, 0);
887 WRITE(REG_A6XX_GRAS_SC_CNTL, A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(2));
888 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
889 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
890 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
891 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
892 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
893 /* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_MODE_CNTL
894 * but this seems to kill texture gather offsets.
895 */
896 WRITE(REG_A6XX_SP_TP_MODE_CNTL, 0xa0 |
897 A6XX_SP_TP_MODE_CNTL_ISAMMODE(ISAMMODE_GL));
898
899 OUT_REG(ring, HLSQ_CONTROL_5_REG(
900 CHIP,
901 .linelengthregid = INVALID_REG,
902 .foveationqualityregid = INVALID_REG,
903 ));
904
905 emit_marker6(ring, 7);
906
907 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
908 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
909
910 WRITE(REG_A6XX_VFD_MULTIVIEW_CNTL, 0);
911
912 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
913 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
914
915 /* Clear any potential pending state groups to be safe: */
916 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
917 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
918 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
919 CP_SET_DRAW_STATE__0_GROUP_ID(0));
920 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
921 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
922
923 OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_CNTL, 1);
924 OUT_RING(ring, 0x00000000); /* VPC_SO_STREAM_CNTL */
925
926 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
927 OUT_RING(ring, 0x00000000);
928
929 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
930 OUT_RING(ring, 0x00000000);
931
932 /* Initialize VFD_FETCH[n].SIZE to zero to avoid iova faults trying
933 * to fetch from a VFD_FETCH[n].BASE which we've potentially inherited
934 * from another process:
935 */
936 for (int32_t i = 0; i < 32; i++) {
937 OUT_PKT4(ring, REG_A6XX_VFD_FETCH_SIZE(i), 1);
938 OUT_RING(ring, 0);
939 }
940
941 /* This happens after all drawing has been emitted to the draw CS, so we know
942 * whether we need the tess BO pointers.
943 */
944 if (batch->tessellation) {
945 assert(screen->tess_bo);
946 fd_ringbuffer_attach_bo(ring, screen->tess_bo);
947 OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR, 2);
948 OUT_RELOC(ring, screen->tess_bo, 0, 0, 0);
949 /* Updating PC_TESSFACTOR_ADDR could race with the next draw which uses it. */
950 OUT_WFI5(ring);
951 }
952
953 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
954 struct fd_bo *bcolor_mem = fd6_ctx->bcolor_mem;
955
956 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR, 2);
957 OUT_RELOC(ring, bcolor_mem, 0, 0, 0);
958
959 OUT_PKT4(ring, REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR, 2);
960 OUT_RELOC(ring, bcolor_mem, 0, 0, 0);
961
962 if (!batch->nondraw) {
963 trace_end_state_restore(&batch->trace, ring);
964 }
965 }
966
967 template void fd6_emit_restore<A6XX>(struct fd_batch *batch, struct fd_ringbuffer *ring);
968 template void fd6_emit_restore<A7XX>(struct fd_batch *batch, struct fd_ringbuffer *ring);
969
970 static void
fd6_mem_to_mem(struct fd_ringbuffer * ring,struct pipe_resource * dst,unsigned dst_off,struct pipe_resource * src,unsigned src_off,unsigned sizedwords)971 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
972 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
973 unsigned sizedwords)
974 {
975 struct fd_bo *src_bo = fd_resource(src)->bo;
976 struct fd_bo *dst_bo = fd_resource(dst)->bo;
977 unsigned i;
978
979 fd_ringbuffer_attach_bo(ring, dst_bo);
980 fd_ringbuffer_attach_bo(ring, src_bo);
981
982 for (i = 0; i < sizedwords; i++) {
983 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
984 OUT_RING(ring, 0x00000000);
985 OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
986 OUT_RELOC(ring, src_bo, src_off, 0, 0);
987
988 dst_off += 4;
989 src_off += 4;
990 }
991 }
992
993 void
fd6_emit_init_screen(struct pipe_screen * pscreen)994 fd6_emit_init_screen(struct pipe_screen *pscreen)
995 {
996 struct fd_screen *screen = fd_screen(pscreen);
997 screen->mem_to_mem = fd6_mem_to_mem;
998 }
999