1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 *
24 */
25
26 #include <xf86drm.h>
27 #include <nouveau_drm.h>
28 #include "util/format/u_format.h"
29 #include "util/format/u_format_s3tc.h"
30 #include "util/u_screen.h"
31
32 #include "nv_object.xml.h"
33 #include "nv_m2mf.xml.h"
34 #include "nv30/nv30-40_3d.xml.h"
35 #include "nv30/nv01_2d.xml.h"
36
37 #include "nouveau_fence.h"
38 #include "nv30/nv30_screen.h"
39 #include "nv30/nv30_context.h"
40 #include "nv30/nv30_resource.h"
41 #include "nv30/nv30_format.h"
42 #include "nv30/nv30_winsys.h"
43
44 #define RANKINE_0397_CHIPSET 0x00000003
45 #define RANKINE_0497_CHIPSET 0x000001e0
46 #define RANKINE_0697_CHIPSET 0x00000010
47 #define CURIE_4097_CHIPSET 0x00000baf
48 #define CURIE_4497_CHIPSET 0x00005450
49 #define CURIE_4497_CHIPSET6X 0x00000088
50
51 static int
nv30_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)52 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
53 {
54 struct nv30_screen *screen = nv30_screen(pscreen);
55 struct nouveau_object *eng3d = screen->eng3d;
56 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
57
58 switch (param) {
59 /* non-boolean capabilities */
60 case PIPE_CAP_MAX_RENDER_TARGETS:
61 return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
62 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
63 return 4096;
64 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
65 return 10;
66 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
67 return 13;
68 case PIPE_CAP_GLSL_FEATURE_LEVEL:
69 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
70 return 120;
71 case PIPE_CAP_ENDIANNESS:
72 return PIPE_ENDIAN_LITTLE;
73 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
74 return 16;
75 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
76 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
77 case PIPE_CAP_MAX_VIEWPORTS:
78 return 1;
79 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
80 return 2048;
81 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
82 return 8 * 1024 * 1024;
83 case PIPE_CAP_MAX_VARYINGS:
84 return 8;
85
86 /* supported capabilities */
87 case PIPE_CAP_ANISOTROPIC_FILTER:
88 case PIPE_CAP_OCCLUSION_QUERY:
89 case PIPE_CAP_QUERY_TIME_ELAPSED:
90 case PIPE_CAP_QUERY_TIMESTAMP:
91 case PIPE_CAP_TEXTURE_SWIZZLE:
92 case PIPE_CAP_DEPTH_CLIP_DISABLE:
93 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
94 case PIPE_CAP_FS_COORD_ORIGIN_LOWER_LEFT:
95 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
96 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
97 case PIPE_CAP_TGSI_TEXCOORD:
98 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
99 case PIPE_CAP_CLEAR_SCISSORED:
100 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
101 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
102 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
103 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
104 case PIPE_CAP_QUERY_MEMORY_INFO:
105 return 1;
106 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
107 return PIPE_TEXTURE_TRANSFER_BLIT;
108 /* nv35 capabilities */
109 case PIPE_CAP_DEPTH_BOUNDS_TEST:
110 return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
111 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
112 case PIPE_CAP_SUPPORTED_PRIM_MODES:
113 return BITFIELD_MASK(MESA_PRIM_COUNT);
114 /* nv4x capabilities */
115 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
116 case PIPE_CAP_NPOT_TEXTURES:
117 case PIPE_CAP_CONDITIONAL_RENDER:
118 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
119 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
120 case PIPE_CAP_PRIMITIVE_RESTART:
121 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
122 return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
123 /* unsupported */
124 case PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART:
125 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
126 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
127 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
128 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
129 case PIPE_CAP_INDEP_BLEND_ENABLE:
130 case PIPE_CAP_INDEP_BLEND_FUNC:
131 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
132 case PIPE_CAP_SHADER_STENCIL_EXPORT:
133 case PIPE_CAP_VS_INSTANCEID:
134 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
135 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
136 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
137 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
138 case PIPE_CAP_MIN_TEXEL_OFFSET:
139 case PIPE_CAP_MAX_TEXEL_OFFSET:
140 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
141 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
142 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
143 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
144 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
145 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
146 case PIPE_CAP_MAX_VERTEX_STREAMS:
147 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
148 case PIPE_CAP_TEXTURE_BARRIER:
149 case PIPE_CAP_SEAMLESS_CUBE_MAP:
150 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
151 case PIPE_CAP_CUBE_MAP_ARRAY:
152 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
153 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
154 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
155 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
156 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
157 case PIPE_CAP_START_INSTANCE:
158 case PIPE_CAP_TEXTURE_MULTISAMPLE:
159 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
160 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
161 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
162 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
163 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
164 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
165 case PIPE_CAP_VS_LAYER_VIEWPORT:
166 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
167 case PIPE_CAP_TEXTURE_GATHER_SM5:
168 case PIPE_CAP_FAKE_SW_MSAA:
169 case PIPE_CAP_TEXTURE_QUERY_LOD:
170 case PIPE_CAP_SAMPLE_SHADING:
171 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
172 case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
173 case PIPE_CAP_USER_VERTEX_BUFFERS:
174 case PIPE_CAP_COMPUTE:
175 case PIPE_CAP_DRAW_INDIRECT:
176 case PIPE_CAP_MULTI_DRAW_INDIRECT:
177 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
178 case PIPE_CAP_FS_FINE_DERIVATIVE:
179 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
180 case PIPE_CAP_SAMPLER_VIEW_TARGET:
181 case PIPE_CAP_CLIP_HALFZ:
182 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
183 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
184 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
185 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
186 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
187 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
188 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
189 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
190 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
191 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
192 case PIPE_CAP_SHAREABLE_SHADERS:
193 case PIPE_CAP_DRAW_PARAMETERS:
194 case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
195 case PIPE_CAP_FS_POSITION_IS_SYSVAL:
196 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
197 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
198 case PIPE_CAP_INVALIDATE_BUFFER:
199 case PIPE_CAP_GENERATE_MIPMAP:
200 case PIPE_CAP_STRING_MARKER:
201 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
202 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
203 case PIPE_CAP_QUERY_BUFFER_OBJECT:
204 case PIPE_CAP_PCI_GROUP:
205 case PIPE_CAP_PCI_BUS:
206 case PIPE_CAP_PCI_DEVICE:
207 case PIPE_CAP_PCI_FUNCTION:
208 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
209 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
210 case PIPE_CAP_CULL_DISTANCE:
211 case PIPE_CAP_SHADER_GROUP_VOTE:
212 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
213 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
214 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
215 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
216 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
217 case PIPE_CAP_SHADER_CAN_READ_OUTPUTS:
218 case PIPE_CAP_NATIVE_FENCE_FD:
219 case PIPE_CAP_FBFETCH:
220 case PIPE_CAP_LEGACY_MATH_RULES:
221 case PIPE_CAP_DOUBLES:
222 case PIPE_CAP_INT64:
223 case PIPE_CAP_TGSI_TEX_TXF_LZ:
224 case PIPE_CAP_SHADER_CLOCK:
225 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
226 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
227 case PIPE_CAP_SHADER_BALLOT:
228 case PIPE_CAP_TES_LAYER_VIEWPORT:
229 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
230 case PIPE_CAP_POST_DEPTH_COVERAGE:
231 case PIPE_CAP_BINDLESS_TEXTURE:
232 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
233 case PIPE_CAP_QUERY_SO_OVERFLOW:
234 case PIPE_CAP_MEMOBJ:
235 case PIPE_CAP_LOAD_CONSTBUF:
236 case PIPE_CAP_TILE_RASTER_ORDER:
237 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
238 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
239 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
240 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
241 case PIPE_CAP_FENCE_SIGNAL:
242 case PIPE_CAP_CONSTBUF0_FLAGS:
243 case PIPE_CAP_PACKED_UNIFORMS:
244 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
245 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
246 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
247 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
248 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
249 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
250 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
251 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
252 case PIPE_CAP_TGSI_DIV:
253 case PIPE_CAP_IMAGE_ATOMIC_INC_WRAP:
254 case PIPE_CAP_IMAGE_STORE_FORMATTED:
255 return 0;
256
257 case PIPE_CAP_MAX_GS_INVOCATIONS:
258 return 32;
259 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
260 return 1 << 27;
261 case PIPE_CAP_VENDOR_ID:
262 return 0x10de;
263 case PIPE_CAP_DEVICE_ID: {
264 uint64_t device_id;
265 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
266 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
267 return -1;
268 }
269 return device_id;
270 }
271 case PIPE_CAP_ACCELERATED:
272 return 1;
273 case PIPE_CAP_VIDEO_MEMORY:
274 return dev->vram_size >> 20;
275 case PIPE_CAP_UMA:
276 return 0;
277 default:
278 return u_pipe_screen_get_param_defaults(pscreen, param);
279 }
280 }
281
282 static float
nv30_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)283 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
284 {
285 struct nv30_screen *screen = nv30_screen(pscreen);
286 struct nouveau_object *eng3d = screen->eng3d;
287
288 switch (param) {
289 case PIPE_CAPF_MIN_LINE_WIDTH:
290 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
291 case PIPE_CAPF_MIN_POINT_SIZE:
292 case PIPE_CAPF_MIN_POINT_SIZE_AA:
293 return 1;
294 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
295 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
296 return 0.1;
297 case PIPE_CAPF_MAX_LINE_WIDTH:
298 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
299 return 10.0;
300 case PIPE_CAPF_MAX_POINT_SIZE:
301 case PIPE_CAPF_MAX_POINT_SIZE_AA:
302 return 64.0;
303 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
304 return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
305 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
306 return 15.0;
307 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
308 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
309 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
310 return 0.0;
311 default:
312 debug_printf("unknown paramf %d\n", param);
313 return 0;
314 }
315 }
316
317 static int
nv30_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)318 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
319 enum pipe_shader_type shader,
320 enum pipe_shader_cap param)
321 {
322 struct nv30_screen *screen = nv30_screen(pscreen);
323 struct nouveau_object *eng3d = screen->eng3d;
324
325 switch (shader) {
326 case PIPE_SHADER_VERTEX:
327 switch (param) {
328 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
329 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
330 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
331 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
332 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
333 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
334 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
335 return 0;
336 case PIPE_SHADER_CAP_MAX_INPUTS:
337 case PIPE_SHADER_CAP_MAX_OUTPUTS:
338 return 16;
339 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
340 return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
341 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
342 return 1;
343 case PIPE_SHADER_CAP_MAX_TEMPS:
344 return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
345 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
346 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
347 return 0;
348 case PIPE_SHADER_CAP_CONT_SUPPORTED:
349 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
350 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
351 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
352 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
353 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
354 case PIPE_SHADER_CAP_SUBROUTINES:
355 case PIPE_SHADER_CAP_INTEGERS:
356 case PIPE_SHADER_CAP_INT64_ATOMICS:
357 case PIPE_SHADER_CAP_FP16:
358 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
359 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
360 case PIPE_SHADER_CAP_INT16:
361 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
362 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
363 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
364 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
365 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
366 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
367 return 0;
368 case PIPE_SHADER_CAP_SUPPORTED_IRS:
369 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
370 default:
371 debug_printf("unknown vertex shader param %d\n", param);
372 return 0;
373 }
374 break;
375 case PIPE_SHADER_FRAGMENT:
376 switch (param) {
377 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
378 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
379 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
380 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
381 return 4096;
382 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
383 return 0;
384 case PIPE_SHADER_CAP_MAX_INPUTS:
385 return 8; /* should be possible to do 10 with nv4x */
386 case PIPE_SHADER_CAP_MAX_OUTPUTS:
387 return 4;
388 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
389 return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
390 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
391 return 1;
392 case PIPE_SHADER_CAP_MAX_TEMPS:
393 return 32;
394 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
395 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
396 return 16;
397 case PIPE_SHADER_CAP_CONT_SUPPORTED:
398 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
399 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
400 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
401 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
402 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
403 case PIPE_SHADER_CAP_SUBROUTINES:
404 case PIPE_SHADER_CAP_INTEGERS:
405 case PIPE_SHADER_CAP_FP16:
406 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
407 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
408 case PIPE_SHADER_CAP_INT16:
409 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
410 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
411 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
412 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
413 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
414 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
415 return 0;
416 case PIPE_SHADER_CAP_SUPPORTED_IRS:
417 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
418 default:
419 debug_printf("unknown fragment shader param %d\n", param);
420 return 0;
421 }
422 break;
423 default:
424 return 0;
425 }
426 }
427
428 static bool
nv30_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bindings)429 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
430 enum pipe_format format,
431 enum pipe_texture_target target,
432 unsigned sample_count,
433 unsigned storage_sample_count,
434 unsigned bindings)
435 {
436 if (sample_count > nv30_screen(pscreen)->max_sample_count)
437 return false;
438
439 if (!(0x00000017 & (1 << sample_count)))
440 return false;
441
442 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
443 return false;
444
445 /* No way to render to a swizzled 3d texture. We don't necessarily know if
446 * it's swizzled or not here, but we have to assume anyways.
447 */
448 if (target == PIPE_TEXTURE_3D && (bindings & PIPE_BIND_RENDER_TARGET))
449 return false;
450
451 /* shared is always supported */
452 bindings &= ~PIPE_BIND_SHARED;
453
454 if (bindings & PIPE_BIND_INDEX_BUFFER) {
455 if (format != PIPE_FORMAT_R8_UINT &&
456 format != PIPE_FORMAT_R16_UINT &&
457 format != PIPE_FORMAT_R32_UINT)
458 return false;
459 bindings &= ~PIPE_BIND_INDEX_BUFFER;
460 }
461
462 return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
463 }
464
465 static const nir_shader_compiler_options nv30_base_compiler_options = {
466 .fuse_ffma32 = true,
467 .fuse_ffma64 = true,
468 .lower_bitops = true,
469 .lower_extract_byte = true,
470 .lower_extract_word = true,
471 .lower_fdiv = true,
472 .lower_fsat = true,
473 .lower_insert_byte = true,
474 .lower_insert_word = true,
475 .lower_fdph = true,
476 .lower_flrp32 = true,
477 .lower_flrp64 = true,
478 .lower_fmod = true,
479 .lower_fpow = true, /* In hardware as of nv40 FS */
480 .lower_uniforms_to_ubo = true,
481 .lower_vector_cmp = true,
482 .force_indirect_unrolling = nir_var_all,
483 .force_indirect_unrolling_sampler = true,
484 .max_unroll_iterations = 32,
485 .no_integers = true,
486
487 .use_interpolated_input_intrinsics = true,
488 };
489
490 static const void *
nv30_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)491 nv30_screen_get_compiler_options(struct pipe_screen *pscreen,
492 enum pipe_shader_ir ir,
493 enum pipe_shader_type shader)
494 {
495 struct nv30_screen *screen = nv30_screen(pscreen);
496 assert(ir == PIPE_SHADER_IR_NIR);
497
498 /* The FS compiler options are different between nv30 and nv40, and are set
499 * up at screen creation time.
500 */
501 if (shader == PIPE_SHADER_FRAGMENT)
502 return &screen->fs_compiler_options;
503
504 return &nv30_base_compiler_options;
505 }
506
507 static void
nv30_screen_fence_emit(struct pipe_context * pcontext,uint32_t * sequence,struct nouveau_bo * wait)508 nv30_screen_fence_emit(struct pipe_context *pcontext, uint32_t *sequence,
509 struct nouveau_bo *wait)
510 {
511 struct nv30_context *nv30 = nv30_context(pcontext);
512 struct nv30_screen *screen = nv30->screen;
513 struct nouveau_pushbuf *push = nv30->base.pushbuf;
514 struct nouveau_pushbuf_refn ref = { wait, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR };
515
516 *sequence = ++screen->base.fence.sequence;
517
518 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
519 PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
520 (2 /* size */ << 18) | (7 /* subchan */ << 13));
521 PUSH_DATA (push, 0);
522 PUSH_DATA (push, *sequence);
523
524 nouveau_pushbuf_refn(push, &ref, 1);
525 }
526
527 static uint32_t
nv30_screen_fence_update(struct pipe_screen * pscreen)528 nv30_screen_fence_update(struct pipe_screen *pscreen)
529 {
530 struct nv30_screen *screen = nv30_screen(pscreen);
531 struct nv04_notify *fence = screen->fence->data;
532 return *(uint32_t *)((char *)screen->notify->map + fence->offset);
533 }
534
535 static void
nv30_screen_destroy(struct pipe_screen * pscreen)536 nv30_screen_destroy(struct pipe_screen *pscreen)
537 {
538 struct nv30_screen *screen = nv30_screen(pscreen);
539
540 if (!nouveau_drm_screen_unref(&screen->base))
541 return;
542
543 nouveau_bo_ref(NULL, &screen->notify);
544
545 nouveau_heap_destroy(&screen->query_heap);
546 nouveau_heap_destroy(&screen->vp_exec_heap);
547 nouveau_heap_destroy(&screen->vp_data_heap);
548
549 nouveau_object_del(&screen->query);
550 nouveau_object_del(&screen->fence);
551 nouveau_object_del(&screen->ntfy);
552
553 nouveau_object_del(&screen->sifm);
554 nouveau_object_del(&screen->swzsurf);
555 nouveau_object_del(&screen->surf2d);
556 nouveau_object_del(&screen->m2mf);
557 nouveau_object_del(&screen->eng3d);
558 nouveau_object_del(&screen->null);
559
560 nouveau_screen_fini(&screen->base);
561 FREE(screen);
562 }
563
564 #define FAIL_SCREEN_INIT(str, err) \
565 do { \
566 NOUVEAU_ERR(str, err); \
567 screen->base.base.context_create = NULL; \
568 return &screen->base; \
569 } while(0)
570
571 struct nouveau_screen *
nv30_screen_create(struct nouveau_device * dev)572 nv30_screen_create(struct nouveau_device *dev)
573 {
574 struct nv30_screen *screen;
575 struct pipe_screen *pscreen;
576 struct nouveau_pushbuf *push;
577 struct nv04_fifo *fifo;
578 unsigned oclass = 0;
579 int ret, i;
580
581 switch (dev->chipset & 0xf0) {
582 case 0x30:
583 if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
584 oclass = NV30_3D_CLASS;
585 else
586 if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
587 oclass = NV34_3D_CLASS;
588 else
589 if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
590 oclass = NV35_3D_CLASS;
591 break;
592 case 0x40:
593 if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
594 oclass = NV40_3D_CLASS;
595 else
596 if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
597 oclass = NV44_3D_CLASS;
598 break;
599 case 0x60:
600 if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
601 oclass = NV44_3D_CLASS;
602 break;
603 default:
604 break;
605 }
606
607 if (!oclass) {
608 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
609 return NULL;
610 }
611
612 screen = CALLOC_STRUCT(nv30_screen);
613 if (!screen)
614 return NULL;
615
616 pscreen = &screen->base.base;
617 pscreen->destroy = nv30_screen_destroy;
618
619 /*
620 * Some modern apps try to use msaa without keeping in mind the
621 * restrictions on videomem of older cards. Resulting in dmesg saying:
622 * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
623 * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
624 * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
625 *
626 * Because we are running out of video memory, after which the program
627 * using the msaa visual freezes, and eventually the entire system freezes.
628 *
629 * To work around this we do not allow msaa visauls by default and allow
630 * the user to override this via NV30_MAX_MSAA.
631 */
632 screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
633 if (screen->max_sample_count > 4)
634 screen->max_sample_count = 4;
635
636 pscreen->get_param = nv30_screen_get_param;
637 pscreen->get_paramf = nv30_screen_get_paramf;
638 pscreen->get_shader_param = nv30_screen_get_shader_param;
639 pscreen->context_create = nv30_context_create;
640 pscreen->is_format_supported = nv30_screen_is_format_supported;
641 pscreen->get_compiler_options = nv30_screen_get_compiler_options;
642
643 nv30_resource_screen_init(pscreen);
644 nouveau_screen_init_vdec(&screen->base);
645
646 screen->base.fence.emit = nv30_screen_fence_emit;
647 screen->base.fence.update = nv30_screen_fence_update;
648
649 ret = nouveau_screen_init(&screen->base, dev);
650 if (ret)
651 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
652
653 screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
654 screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
655 if (oclass == NV40_3D_CLASS) {
656 screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
657 screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
658 }
659
660 screen->fs_compiler_options = nv30_base_compiler_options;
661 screen->fs_compiler_options.lower_fsat = false;
662 if (oclass >= NV40_3D_CLASS)
663 screen->fs_compiler_options.lower_fpow = false;
664
665 fifo = screen->base.channel->data;
666 push = screen->base.pushbuf;
667 push->rsvd_kick = 16;
668
669 ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
670 NULL, 0, &screen->null);
671 if (ret)
672 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
673
674 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
675 * this means that the address pointed at by the DMA object must
676 * be 4KiB aligned, which means this object needs to be the first
677 * one allocated on the channel.
678 */
679 ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
680 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
681 .length = 32 }, sizeof(struct nv04_notify),
682 &screen->fence);
683 if (ret)
684 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
685
686 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
687 ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
688 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
689 .length = 32 }, sizeof(struct nv04_notify),
690 &screen->ntfy);
691 if (ret)
692 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
693
694 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
695 * the remainder of the "notifier block" assigned by the kernel for
696 * use as query objects
697 */
698 ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
699 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
700 .length = 4096 - 128 }, sizeof(struct nv04_notify),
701 &screen->query);
702 if (ret)
703 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
704
705 ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
706 if (ret)
707 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
708
709 list_inithead(&screen->queries);
710
711 /* Vertex program resources (code/data), currently 6 of the constant
712 * slots are reserved to implement user clipping planes
713 */
714 if (oclass < NV40_3D_CLASS) {
715 nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
716 nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
717 } else {
718 nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
719 nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
720 }
721
722 ret = nouveau_bo_wrap(screen->base.device, fifo->notify, &screen->notify);
723 if (ret == 0)
724 ret = BO_MAP(&screen->base, screen->notify, 0, screen->base.client);
725 if (ret)
726 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
727
728 ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
729 NULL, 0, &screen->eng3d);
730 if (ret)
731 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
732
733 BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
734 PUSH_DATA (push, screen->eng3d->handle);
735 BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
736 PUSH_DATA (push, screen->ntfy->handle);
737 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */
738 PUSH_DATA (push, fifo->gart); /* TEXTURE1 */
739 PUSH_DATA (push, fifo->vram); /* COLOR1 */
740 PUSH_DATA (push, screen->null->handle); /* UNK190 */
741 PUSH_DATA (push, fifo->vram); /* COLOR0 */
742 PUSH_DATA (push, fifo->vram); /* ZETA */
743 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */
744 PUSH_DATA (push, fifo->gart); /* VTXBUF1 */
745 PUSH_DATA (push, screen->fence->handle); /* FENCE */
746 PUSH_DATA (push, screen->query->handle); /* QUERY - intr 0x80 if nullobj */
747 PUSH_DATA (push, screen->null->handle); /* UNK1AC */
748 PUSH_DATA (push, screen->null->handle); /* UNK1B0 */
749 if (screen->eng3d->oclass < NV40_3D_CLASS) {
750 BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
751 PUSH_DATA (push, 0x00100000);
752 BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
753 PUSH_DATA (push, 3);
754
755 BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
756 PUSH_DATA (push, 0);
757 BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
758 PUSH_DATA (push, fui(0.0));
759 PUSH_DATA (push, fui(0.0));
760 PUSH_DATA (push, fui(1.0));
761 BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
762 for (i = 0; i < 16; i++)
763 PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
764
765 BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
766 PUSH_DATA (push, 0);
767 } else {
768 BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
769 PUSH_DATA (push, fifo->vram);
770 PUSH_DATA (push, fifo->vram); /* COLOR3 */
771
772 BEGIN_NV04(push, SUBC_3D(0x1450), 1);
773 PUSH_DATA (push, 0x00000004);
774
775 BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
776 PUSH_DATA (push, 0x00000010);
777 PUSH_DATA (push, 0x01000100);
778 PUSH_DATA (push, 0xff800006);
779
780 /* vtxprog output routing */
781 BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
782 PUSH_DATA (push, 0x06144321);
783 BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
784 PUSH_DATA (push, 0xedcba987);
785 PUSH_DATA (push, 0x0000006f);
786 BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
787 PUSH_DATA (push, 0x00171615);
788 BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
789 PUSH_DATA (push, 0x001b1a19);
790
791 BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
792 PUSH_DATA (push, 0x0020ffff);
793 BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
794 PUSH_DATA (push, 0x01d300d4);
795
796 BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
797 PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
798 }
799
800 ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
801 NULL, 0, &screen->m2mf);
802 if (ret)
803 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
804
805 BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
806 PUSH_DATA (push, screen->m2mf->handle);
807 BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
808 PUSH_DATA (push, screen->ntfy->handle);
809
810 ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
811 NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
812 if (ret)
813 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
814
815 BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
816 PUSH_DATA (push, screen->surf2d->handle);
817 BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
818 PUSH_DATA (push, screen->ntfy->handle);
819
820 if (dev->chipset < 0x40)
821 oclass = NV30_SURFACE_SWZ_CLASS;
822 else
823 oclass = NV40_SURFACE_SWZ_CLASS;
824
825 ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
826 NULL, 0, &screen->swzsurf);
827 if (ret)
828 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
829
830 BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
831 PUSH_DATA (push, screen->swzsurf->handle);
832 BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
833 PUSH_DATA (push, screen->ntfy->handle);
834
835 if (dev->chipset < 0x40)
836 oclass = NV30_SIFM_CLASS;
837 else
838 oclass = NV40_SIFM_CLASS;
839
840 ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
841 NULL, 0, &screen->sifm);
842 if (ret)
843 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
844
845 BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
846 PUSH_DATA (push, screen->sifm->handle);
847 BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
848 PUSH_DATA (push, screen->ntfy->handle);
849 BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
850 PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
851 PUSH_KICK (push);
852
853 return &screen->base;
854 }
855