1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <errno.h>
24 #include <xf86drm.h>
25 #include <nouveau_drm.h>
26 #include "util/format/u_format.h"
27 #include "util/format/u_format_s3tc.h"
28 #include "util/u_screen.h"
29 #include "pipe/p_screen.h"
30
31 #include "nv50_ir_driver.h"
32
33 #include "nv50/nv50_context.h"
34 #include "nv50/nv50_screen.h"
35
36 #include "nouveau_vp3_video.h"
37
38 #include "nv_object.xml.h"
39
40 /* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */
41 #define LOCAL_WARPS_ALLOC 32
42 /* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */
43 #define STACK_WARPS_ALLOC 32
44
45 #define THREADS_IN_WARP 32
46
47 static bool
nv50_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bindings)48 nv50_screen_is_format_supported(struct pipe_screen *pscreen,
49 enum pipe_format format,
50 enum pipe_texture_target target,
51 unsigned sample_count,
52 unsigned storage_sample_count,
53 unsigned bindings)
54 {
55 if (sample_count > 8)
56 return false;
57 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
58 return false;
59 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128)
60 return false;
61
62 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
63 return false;
64
65 /* Short-circuit the rest of the logic -- this is used by the gallium frontend
66 * to determine valid MS levels in a no-attachments scenario.
67 */
68 if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
69 return true;
70
71 switch (format) {
72 case PIPE_FORMAT_Z16_UNORM:
73 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS)
74 return false;
75 break;
76 default:
77 break;
78 }
79
80 if (bindings & PIPE_BIND_LINEAR)
81 if (util_format_is_depth_or_stencil(format) ||
82 (target != PIPE_TEXTURE_1D &&
83 target != PIPE_TEXTURE_2D &&
84 target != PIPE_TEXTURE_RECT) ||
85 sample_count > 1)
86 return false;
87
88 /* shared is always supported */
89 bindings &= ~(PIPE_BIND_LINEAR |
90 PIPE_BIND_SHARED);
91
92 if (bindings & PIPE_BIND_INDEX_BUFFER) {
93 if (format != PIPE_FORMAT_R8_UINT &&
94 format != PIPE_FORMAT_R16_UINT &&
95 format != PIPE_FORMAT_R32_UINT)
96 return false;
97 bindings &= ~PIPE_BIND_INDEX_BUFFER;
98 }
99
100 return (( nv50_format_table[format].usage |
101 nv50_vertex_format[format].usage) & bindings) == bindings;
102 }
103
104 static int
nv50_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)105 nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
106 {
107 struct nouveau_screen *screen = nouveau_screen(pscreen);
108 const uint16_t class_3d = screen->class_3d;
109 struct nouveau_device *dev = screen->device;
110
111 switch (param) {
112 /* non-boolean caps */
113 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
114 return 8192;
115 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
116 return 12;
117 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
118 return 14;
119 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
120 return 512;
121 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
122 case PIPE_CAP_MIN_TEXEL_OFFSET:
123 return -8;
124 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
125 case PIPE_CAP_MAX_TEXEL_OFFSET:
126 return 7;
127 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
128 return 128 * 1024 * 1024;
129 case PIPE_CAP_GLSL_FEATURE_LEVEL:
130 return 330;
131 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
132 return 330;
133 case PIPE_CAP_ESSL_FEATURE_LEVEL:
134 return class_3d >= NVA3_3D_CLASS ? 310 : 300;
135 case PIPE_CAP_MAX_RENDER_TARGETS:
136 return 8;
137 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
138 return 1;
139 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
140 return NV50_MAX_GLOBALS - 1;
141 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
142 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
143 return 8;
144 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
145 return 4;
146 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
147 return 64;
148 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
149 return 4;
150 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
151 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
152 return 1024;
153 case PIPE_CAP_MAX_VERTEX_STREAMS:
154 return 1;
155 case PIPE_CAP_MAX_GS_INVOCATIONS:
156 return 0;
157 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
158 return 1 << 27;
159 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
160 return 2048;
161 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
162 return 2047;
163 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
164 return 256;
165 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
166 return 16; /* 256 for binding as RT, but that's not possible in GL */
167 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
168 return 256; /* the access limit is aligned to 256 */
169 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
170 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
171 case PIPE_CAP_MAX_VIEWPORTS:
172 return NV50_MAX_VIEWPORTS;
173 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
174 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
175 case PIPE_CAP_ENDIANNESS:
176 return PIPE_ENDIAN_LITTLE;
177 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
178 return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
179 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
180 return NV50_MAX_WINDOW_RECTANGLES;
181 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
182 return 16 * 1024 * 1024;
183 case PIPE_CAP_MAX_VARYINGS:
184 return 15;
185 case PIPE_CAP_MAX_VERTEX_BUFFERS:
186 return 16;
187 case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
188 return 512 * 1024; /* TODO: Investigate tuning this */
189 case PIPE_CAP_MAX_TEXTURE_MB:
190 return 0; /* TODO: use 1/2 of VRAM for this? */
191
192 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
193 case PIPE_CAP_SUPPORTED_PRIM_MODES:
194 return BITFIELD_MASK(MESA_PRIM_COUNT);
195
196 /* supported caps */
197 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
198 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
199 case PIPE_CAP_TEXTURE_SWIZZLE:
200 case PIPE_CAP_NPOT_TEXTURES:
201 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
202 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
203 case PIPE_CAP_ANISOTROPIC_FILTER:
204 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
205 case PIPE_CAP_DEPTH_CLIP_DISABLE:
206 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
207 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
208 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
209 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
210 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
211 case PIPE_CAP_QUERY_TIMESTAMP:
212 case PIPE_CAP_QUERY_TIME_ELAPSED:
213 case PIPE_CAP_OCCLUSION_QUERY:
214 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
215 case PIPE_CAP_INDEP_BLEND_ENABLE:
216 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
217 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
218 case PIPE_CAP_PRIMITIVE_RESTART:
219 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
220 case PIPE_CAP_VS_INSTANCEID:
221 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
222 case PIPE_CAP_CONDITIONAL_RENDER:
223 case PIPE_CAP_TEXTURE_BARRIER:
224 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
225 case PIPE_CAP_START_INSTANCE:
226 case PIPE_CAP_USER_VERTEX_BUFFERS:
227 case PIPE_CAP_TEXTURE_MULTISAMPLE:
228 case PIPE_CAP_FS_FINE_DERIVATIVE:
229 case PIPE_CAP_SAMPLER_VIEW_TARGET:
230 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
231 case PIPE_CAP_CLIP_HALFZ:
232 case PIPE_CAP_MEMOBJ:
233 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
234 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
235 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
236 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
237 case PIPE_CAP_DEPTH_BOUNDS_TEST:
238 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
239 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
240 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
241 case PIPE_CAP_INVALIDATE_BUFFER:
242 case PIPE_CAP_STRING_MARKER:
243 case PIPE_CAP_CULL_DISTANCE:
244 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
245 case PIPE_CAP_LEGACY_MATH_RULES:
246 case PIPE_CAP_TGSI_TEX_TXF_LZ:
247 case PIPE_CAP_SHADER_CLOCK:
248 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
249 case PIPE_CAP_TGSI_DIV:
250 case PIPE_CAP_CLEAR_SCISSORED:
251 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
252 case PIPE_CAP_COMPUTE:
253 case PIPE_CAP_QUERY_MEMORY_INFO:
254 return 1;
255
256 case PIPE_CAP_ALPHA_TEST:
257 /* nvc0 has fixed function alpha test support, but nv50 doesn't. If we
258 * don't have it, then the frontend will lower it for us.
259 */
260 return class_3d >= NVC0_3D_CLASS;
261
262 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
263 return PIPE_TEXTURE_TRANSFER_BLIT;
264 case PIPE_CAP_SEAMLESS_CUBE_MAP:
265 return 1; /* class_3d >= NVA0_3D_CLASS; */
266 /* supported on nva0+ */
267 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
268 return class_3d >= NVA0_3D_CLASS;
269 /* supported on nva3+ */
270 case PIPE_CAP_CUBE_MAP_ARRAY:
271 case PIPE_CAP_INDEP_BLEND_FUNC:
272 case PIPE_CAP_TEXTURE_QUERY_LOD:
273 case PIPE_CAP_SAMPLE_SHADING:
274 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
275 return class_3d >= NVA3_3D_CLASS;
276
277 case PIPE_CAP_PCI_GROUP:
278 case PIPE_CAP_PCI_BUS:
279 case PIPE_CAP_PCI_DEVICE:
280 case PIPE_CAP_PCI_FUNCTION:
281 return 0;
282
283 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
284 case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
285 case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE: /* when we fix MT stuff */
286 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
287 case PIPE_CAP_HARDWARE_GL_SELECT:
288 return 0;
289
290 case PIPE_CAP_VENDOR_ID:
291 return 0x10de;
292 case PIPE_CAP_DEVICE_ID: {
293 uint64_t device_id;
294 if (nouveau_getparam(dev, NOUVEAU_GETPARAM_PCI_DEVICE, &device_id)) {
295 NOUVEAU_ERR("NOUVEAU_GETPARAM_PCI_DEVICE failed.\n");
296 return -1;
297 }
298 return device_id;
299 }
300 case PIPE_CAP_ACCELERATED:
301 return 1;
302 case PIPE_CAP_VIDEO_MEMORY:
303 return dev->vram_size >> 20;
304 case PIPE_CAP_UMA:
305 return nouveau_screen(pscreen)->is_uma;
306
307 default:
308 return u_pipe_screen_get_param_defaults(pscreen, param);
309 }
310 }
311
312 static int
nv50_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)313 nv50_screen_get_shader_param(struct pipe_screen *pscreen,
314 enum pipe_shader_type shader,
315 enum pipe_shader_cap param)
316 {
317 switch (shader) {
318 case PIPE_SHADER_VERTEX:
319 case PIPE_SHADER_GEOMETRY:
320 case PIPE_SHADER_FRAGMENT:
321 case PIPE_SHADER_COMPUTE:
322 break;
323 default:
324 return 0;
325 }
326
327 switch (param) {
328 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
329 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
330 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
331 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
332 return 16384;
333 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
334 return 4;
335 case PIPE_SHADER_CAP_MAX_INPUTS:
336 if (shader == PIPE_SHADER_VERTEX)
337 return 32;
338 return 15;
339 case PIPE_SHADER_CAP_MAX_OUTPUTS:
340 return 16;
341 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
342 return 65536;
343 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
344 return NV50_MAX_PIPE_CONSTBUFS;
345 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
346 return shader != PIPE_SHADER_FRAGMENT;
347 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
348 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
349 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
350 return 1;
351 case PIPE_SHADER_CAP_MAX_TEMPS:
352 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
353 case PIPE_SHADER_CAP_CONT_SUPPORTED:
354 return 1;
355 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
356 return 1;
357 case PIPE_SHADER_CAP_INT64_ATOMICS:
358 case PIPE_SHADER_CAP_FP16:
359 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
360 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
361 case PIPE_SHADER_CAP_INT16:
362 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
363 case PIPE_SHADER_CAP_SUBROUTINES:
364 return 0; /* please inline, or provide function declarations */
365 case PIPE_SHADER_CAP_INTEGERS:
366 return 1;
367 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
368 /* The chip could handle more sampler views than samplers */
369 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
370 return MIN2(16, PIPE_MAX_SAMPLERS);
371 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
372 return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
373 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
374 return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
375 case PIPE_SHADER_CAP_SUPPORTED_IRS:
376 return 1 << PIPE_SHADER_IR_NIR;
377 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
378 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
379 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
380 return 0;
381 default:
382 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
383 return 0;
384 }
385 }
386
387 static float
nv50_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)388 nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
389 {
390 switch (param) {
391 case PIPE_CAPF_MIN_LINE_WIDTH:
392 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
393 case PIPE_CAPF_MIN_POINT_SIZE:
394 case PIPE_CAPF_MIN_POINT_SIZE_AA:
395 return 1;
396 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
397 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
398 return 0.1;
399 case PIPE_CAPF_MAX_LINE_WIDTH:
400 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
401 return 10.0f;
402 case PIPE_CAPF_MAX_POINT_SIZE:
403 case PIPE_CAPF_MAX_POINT_SIZE_AA:
404 return 64.0f;
405 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
406 return 16.0f;
407 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
408 return 15.0f;
409 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
410 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
411 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
412 return 0.0f;
413 }
414
415 NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
416 return 0.0f;
417 }
418
419 static int
nv50_screen_get_compute_param(struct pipe_screen * pscreen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * data)420 nv50_screen_get_compute_param(struct pipe_screen *pscreen,
421 enum pipe_shader_ir ir_type,
422 enum pipe_compute_cap param, void *data)
423 {
424 struct nv50_screen *screen = nv50_screen(pscreen);
425 struct nouveau_device *dev = screen->base.device;
426
427 #define RET(x) do { \
428 if (data) \
429 memcpy(data, x, sizeof(x)); \
430 return sizeof(x); \
431 } while (0)
432
433 switch (param) {
434 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
435 RET((uint64_t []) { 3 });
436 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
437 RET(((uint64_t []) { 65535, 65535, 65535 }));
438 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
439 RET(((uint64_t []) { 512, 512, 64 }));
440 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
441 RET((uint64_t []) { 512 });
442 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
443 RET((uint64_t []) { nouveau_device_get_global_mem_size(dev) });
444 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
445 RET((uint64_t []) { 16 << 10 });
446 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
447 RET((uint64_t []) { 16 << 10 });
448 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
449 RET((uint64_t []) { 4096 });
450 case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
451 RET((uint32_t []) { 32 });
452 case PIPE_COMPUTE_CAP_MAX_SUBGROUPS:
453 RET((uint32_t []) { 0 });
454 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
455 RET((uint64_t []) { nouveau_device_get_global_mem_size(dev) });
456 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
457 RET((uint32_t []) { 0 });
458 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
459 RET((uint32_t []) { screen->mp_count });
460 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
461 RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
462 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
463 RET((uint32_t []) { 32 });
464 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
465 RET((uint64_t []) { 0 });
466 default:
467 return 0;
468 }
469
470 #undef RET
471 }
472
473 static void
nv50_screen_destroy(struct pipe_screen * pscreen)474 nv50_screen_destroy(struct pipe_screen *pscreen)
475 {
476 struct nv50_screen *screen = nv50_screen(pscreen);
477
478 if (!nouveau_drm_screen_unref(&screen->base))
479 return;
480
481 if (screen->blitter)
482 nv50_blitter_destroy(screen);
483 if (screen->pm.prog) {
484 screen->pm.prog->code = NULL; /* hardcoded, don't FREE */
485 nv50_program_destroy(NULL, screen->pm.prog);
486 FREE(screen->pm.prog);
487 }
488
489 nouveau_bo_ref(NULL, &screen->code);
490 nouveau_bo_ref(NULL, &screen->tls_bo);
491 nouveau_bo_ref(NULL, &screen->stack_bo);
492 nouveau_bo_ref(NULL, &screen->txc);
493 nouveau_bo_ref(NULL, &screen->uniforms);
494 nouveau_bo_ref(NULL, &screen->fence.bo);
495
496 nouveau_heap_destroy(&screen->vp_code_heap);
497 nouveau_heap_destroy(&screen->gp_code_heap);
498 nouveau_heap_destroy(&screen->fp_code_heap);
499
500 FREE(screen->tic.entries);
501
502 nouveau_object_del(&screen->tesla);
503 nouveau_object_del(&screen->eng2d);
504 nouveau_object_del(&screen->m2mf);
505 nouveau_object_del(&screen->compute);
506 nouveau_object_del(&screen->sync);
507
508 nouveau_screen_fini(&screen->base);
509 simple_mtx_destroy(&screen->state_lock);
510
511 FREE(screen);
512 }
513
514 static void
nv50_screen_fence_emit(struct pipe_context * pcontext,u32 * sequence,struct nouveau_bo * wait)515 nv50_screen_fence_emit(struct pipe_context *pcontext, u32 *sequence,
516 struct nouveau_bo *wait)
517 {
518 struct nv50_context *nv50 = nv50_context(pcontext);
519 struct nv50_screen *screen = nv50->screen;
520 struct nouveau_pushbuf *push = nv50->base.pushbuf;
521 struct nouveau_pushbuf_refn ref = { wait, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR };
522
523 /* we need to do it after possible flush in MARK_RING */
524 *sequence = ++screen->base.fence.sequence;
525
526 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 5);
527 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
528 PUSH_DATAh(push, screen->fence.bo->offset);
529 PUSH_DATA (push, screen->fence.bo->offset);
530 PUSH_DATA (push, *sequence);
531 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
532 NV50_3D_QUERY_GET_UNK4 |
533 NV50_3D_QUERY_GET_UNIT_CROP |
534 NV50_3D_QUERY_GET_TYPE_QUERY |
535 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
536 NV50_3D_QUERY_GET_SHORT);
537
538 nouveau_pushbuf_refn(push, &ref, 1);
539 }
540
541 static u32
nv50_screen_fence_update(struct pipe_screen * pscreen)542 nv50_screen_fence_update(struct pipe_screen *pscreen)
543 {
544 return nv50_screen(pscreen)->fence.map[0];
545 }
546
547 static void
nv50_screen_init_hwctx(struct nv50_screen * screen)548 nv50_screen_init_hwctx(struct nv50_screen *screen)
549 {
550 struct nouveau_pushbuf *push = screen->base.pushbuf;
551 struct nv04_fifo *fifo;
552 unsigned i;
553
554 fifo = (struct nv04_fifo *)screen->base.channel->data;
555
556 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1);
557 PUSH_DATA (push, screen->m2mf->handle);
558 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3);
559 PUSH_DATA (push, screen->sync->handle);
560 PUSH_DATA (push, fifo->vram);
561 PUSH_DATA (push, fifo->vram);
562
563 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1);
564 PUSH_DATA (push, screen->eng2d->handle);
565 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4);
566 PUSH_DATA (push, screen->sync->handle);
567 PUSH_DATA (push, fifo->vram);
568 PUSH_DATA (push, fifo->vram);
569 PUSH_DATA (push, fifo->vram);
570 BEGIN_NV04(push, NV50_2D(OPERATION), 1);
571 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY);
572 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1);
573 PUSH_DATA (push, 0);
574 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1);
575 PUSH_DATA (push, 0);
576 BEGIN_NV04(push, NV50_2D(SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP), 1);
577 PUSH_DATA (push, 1);
578 BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
579 PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
580
581 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
582 PUSH_DATA (push, screen->tesla->handle);
583
584 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
585 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS);
586
587 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
588 PUSH_DATA (push, screen->sync->handle);
589 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
590 for (i = 0; i < 11; ++i)
591 PUSH_DATA(push, fifo->vram);
592 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
593 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i)
594 PUSH_DATA(push, fifo->vram);
595
596 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
597 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED);
598 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
599 PUSH_DATA (push, 0xf);
600
601 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", true)) {
602 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
603 PUSH_DATA (push, 0x18);
604 }
605
606 BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
607 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
608
609 BEGIN_NV04(push, NV50_3D(RT_COMP_ENABLE(0)), 8);
610 for (i = 0; i < 8; ++i)
611 PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
612
613 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
614 PUSH_DATA (push, 1);
615
616 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1);
617 PUSH_DATA (push, 0);
618 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1);
619 PUSH_DATA (push, 0);
620 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
621 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1);
622 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1);
623 PUSH_DATA (push, 0);
624 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_WITH_DRAW_ARRAYS), 1);
625 PUSH_DATA (push, 1);
626 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1);
627 PUSH_DATA (push, 1);
628
629 if (screen->tesla->oclass >= NVA0_3D_CLASS) {
630 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1);
631 PUSH_DATA (push, 0);
632 }
633
634 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1);
635 PUSH_DATA (push, 0);
636 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2);
637 PUSH_DATA (push, 0);
638 PUSH_DATA (push, 0);
639 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1);
640 PUSH_DATA (push, 0x3f);
641
642 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
643 PUSH_DATAh(push, screen->code->offset + (NV50_SHADER_STAGE_VERTEX << NV50_CODE_BO_SIZE_LOG2));
644 PUSH_DATA (push, screen->code->offset + (NV50_SHADER_STAGE_VERTEX << NV50_CODE_BO_SIZE_LOG2));
645
646 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
647 PUSH_DATAh(push, screen->code->offset + (NV50_SHADER_STAGE_FRAGMENT << NV50_CODE_BO_SIZE_LOG2));
648 PUSH_DATA (push, screen->code->offset + (NV50_SHADER_STAGE_FRAGMENT << NV50_CODE_BO_SIZE_LOG2));
649
650 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
651 PUSH_DATAh(push, screen->code->offset + (NV50_SHADER_STAGE_GEOMETRY << NV50_CODE_BO_SIZE_LOG2));
652 PUSH_DATA (push, screen->code->offset + (NV50_SHADER_STAGE_GEOMETRY << NV50_CODE_BO_SIZE_LOG2));
653
654 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
655 PUSH_DATAh(push, screen->tls_bo->offset);
656 PUSH_DATA (push, screen->tls_bo->offset);
657 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
658
659 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3);
660 PUSH_DATAh(push, screen->stack_bo->offset);
661 PUSH_DATA (push, screen->stack_bo->offset);
662 PUSH_DATA (push, 4);
663
664 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
665 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16));
666 PUSH_DATA (push, screen->uniforms->offset + (0 << 16));
667 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000);
668
669 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
670 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16));
671 PUSH_DATA (push, screen->uniforms->offset + (1 << 16));
672 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000);
673
674 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
675 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16));
676 PUSH_DATA (push, screen->uniforms->offset + (2 << 16));
677 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000);
678
679 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
680 PUSH_DATAh(push, screen->uniforms->offset + (4 << 16));
681 PUSH_DATA (push, screen->uniforms->offset + (4 << 16));
682 PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
683
684 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
685 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
686 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
687 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
688
689 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
690 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
691 PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
692 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
693 PUSH_DATAf(push, 0.0f);
694 PUSH_DATAf(push, 0.0f);
695 PUSH_DATAf(push, 0.0f);
696 PUSH_DATAf(push, 0.0f);
697 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
698 PUSH_DATAh(push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
699 PUSH_DATA (push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
700
701 /* set the membar offset */
702 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
703 PUSH_DATA (push, (NV50_CB_AUX_MEMBAR_OFFSET << (8 - 2)) | NV50_CB_AUX);
704 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 1);
705 PUSH_DATA (push, screen->uniforms->offset + (4 << 16) + NV50_CB_AUX_MEMBAR_OFFSET);
706
707 nv50_upload_ms_info(push);
708
709 /* max TIC (bits 4:8) & TSC bindings, per program type */
710 for (i = 0; i < NV50_MAX_3D_SHADER_STAGES; ++i) {
711 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1);
712 PUSH_DATA (push, 0x54);
713 }
714
715 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
716 PUSH_DATAh(push, screen->txc->offset);
717 PUSH_DATA (push, screen->txc->offset);
718 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
719
720 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3);
721 PUSH_DATAh(push, screen->txc->offset + 65536);
722 PUSH_DATA (push, screen->txc->offset + 65536);
723 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
724
725 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1);
726 PUSH_DATA (push, 0);
727
728 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1);
729 PUSH_DATA (push, 0);
730 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1);
731 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY);
732 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2);
733 for (i = 0; i < 8 * 2; ++i)
734 PUSH_DATA(push, 0);
735 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1);
736 PUSH_DATA (push, 0);
737
738 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
739 PUSH_DATA (push, 1);
740 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
741 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
742 PUSH_DATAf(push, 0.0f);
743 PUSH_DATAf(push, 1.0f);
744 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
745 PUSH_DATA (push, 8192 << 16);
746 PUSH_DATA (push, 8192 << 16);
747 }
748
749 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
750 #ifdef NV50_SCISSORS_CLIPPING
751 PUSH_DATA (push, 0x0000);
752 #else
753 PUSH_DATA (push, 0x1080);
754 #endif
755
756 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1);
757 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT);
758
759 /* We use scissors instead of exact view volume clipping,
760 * so they're always enabled.
761 */
762 for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
763 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
764 PUSH_DATA (push, 1);
765 PUSH_DATA (push, 8192 << 16);
766 PUSH_DATA (push, 8192 << 16);
767 }
768
769 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
770 PUSH_DATA (push, 1);
771 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1);
772 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL);
773 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1);
774 PUSH_DATA (push, 0x11111111);
775 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
776 PUSH_DATA (push, 1);
777
778 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1);
779 PUSH_DATA (push, 0);
780 if (screen->base.class_3d >= NV84_3D_CLASS) {
781 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1);
782 PUSH_DATA (push, 0);
783 }
784
785 BEGIN_NV04(push, NV50_3D(UNK0FDC), 1);
786 PUSH_DATA (push, 1);
787 BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
788 PUSH_DATA (push, 1);
789 }
790
nv50_tls_alloc(struct nv50_screen * screen,unsigned tls_space,uint64_t * tls_size)791 static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
792 uint64_t *tls_size)
793 {
794 struct nouveau_device *dev = screen->base.device;
795 int ret;
796
797 assert(tls_space % ONE_TEMP_SIZE == 0);
798 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
799 ONE_TEMP_SIZE;
800 if (nouveau_mesa_debug)
801 debug_printf("allocating space for %u temps\n",
802 util_next_power_of_two(tls_space / ONE_TEMP_SIZE));
803 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) *
804 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP;
805
806 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
807 *tls_size, NULL, &screen->tls_bo);
808 if (ret) {
809 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret);
810 return ret;
811 }
812
813 return 0;
814 }
815
nv50_tls_realloc(struct nv50_screen * screen,unsigned tls_space)816 int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
817 {
818 struct nouveau_pushbuf *push = screen->base.pushbuf;
819 int ret;
820 uint64_t tls_size;
821
822 if (tls_space < screen->cur_tls_space)
823 return 0;
824 if (tls_space > screen->max_tls_space) {
825 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC /
826 * LOCAL_WARPS_NO_CLAMP) */
827 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n",
828 (unsigned)(tls_space / ONE_TEMP_SIZE),
829 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE));
830 return -ENOMEM;
831 }
832
833 nouveau_bo_ref(NULL, &screen->tls_bo);
834 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
835 if (ret)
836 return ret;
837
838 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
839 PUSH_DATAh(push, screen->tls_bo->offset);
840 PUSH_DATA (push, screen->tls_bo->offset);
841 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8));
842
843 return 1;
844 }
845
846 static const void *
nv50_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)847 nv50_screen_get_compiler_options(struct pipe_screen *pscreen,
848 enum pipe_shader_ir ir,
849 enum pipe_shader_type shader)
850 {
851 if (ir == PIPE_SHADER_IR_NIR)
852 return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader);
853 return NULL;
854 }
855
856 struct nouveau_screen *
nv50_screen_create(struct nouveau_device * dev)857 nv50_screen_create(struct nouveau_device *dev)
858 {
859 struct nv50_screen *screen;
860 struct pipe_screen *pscreen;
861 struct nouveau_object *chan;
862 uint64_t value;
863 uint32_t tesla_class;
864 unsigned stack_size;
865 int ret;
866
867 screen = CALLOC_STRUCT(nv50_screen);
868 if (!screen)
869 return NULL;
870 pscreen = &screen->base.base;
871 pscreen->destroy = nv50_screen_destroy;
872
873 simple_mtx_init(&screen->state_lock, mtx_plain);
874 ret = nouveau_screen_init(&screen->base, dev);
875 if (ret) {
876 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
877 goto fail;
878 }
879
880 /* TODO: Prevent FIFO prefetch before transfer of index buffers and
881 * admit them to VRAM.
882 */
883 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
884 PIPE_BIND_VERTEX_BUFFER;
885 screen->base.sysmem_bindings |=
886 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
887
888 screen->base.pushbuf->rsvd_kick = 5;
889
890 chan = screen->base.channel;
891
892 pscreen->context_create = nv50_create;
893 pscreen->is_format_supported = nv50_screen_is_format_supported;
894 pscreen->get_param = nv50_screen_get_param;
895 pscreen->get_shader_param = nv50_screen_get_shader_param;
896 pscreen->get_paramf = nv50_screen_get_paramf;
897 pscreen->get_compute_param = nv50_screen_get_compute_param;
898 pscreen->get_driver_query_info = nv50_screen_get_driver_query_info;
899 pscreen->get_driver_query_group_info = nv50_screen_get_driver_query_group_info;
900
901 /* nir stuff */
902 pscreen->get_compiler_options = nv50_screen_get_compiler_options;
903
904 nv50_screen_init_resource_functions(pscreen);
905
906 if (screen->base.device->chipset < 0x84 ||
907 debug_get_bool_option("NOUVEAU_PMPEG", false)) {
908 /* PMPEG */
909 nouveau_screen_init_vdec(&screen->base);
910 } else if (screen->base.device->chipset < 0x98 ||
911 screen->base.device->chipset == 0xa0) {
912 /* VP2 */
913 screen->base.base.get_video_param = nv84_screen_get_video_param;
914 screen->base.base.is_video_format_supported = nv84_screen_video_supported;
915 } else {
916 /* VP3/4 */
917 screen->base.base.get_video_param = nouveau_vp3_screen_get_video_param;
918 screen->base.base.is_video_format_supported = nouveau_vp3_screen_video_supported;
919 }
920
921 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096,
922 NULL, &screen->fence.bo);
923 if (ret) {
924 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret);
925 goto fail;
926 }
927
928 BO_MAP(&screen->base, screen->fence.bo, 0, NULL);
929 screen->fence.map = screen->fence.bo->map;
930 screen->base.fence.emit = nv50_screen_fence_emit;
931 screen->base.fence.update = nv50_screen_fence_update;
932
933 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS,
934 &(struct nv04_notify){ .length = 32 },
935 sizeof(struct nv04_notify), &screen->sync);
936 if (ret) {
937 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret);
938 goto fail;
939 }
940
941 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS,
942 NULL, 0, &screen->m2mf);
943 if (ret) {
944 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret);
945 goto fail;
946 }
947
948 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS,
949 NULL, 0, &screen->eng2d);
950 if (ret) {
951 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret);
952 goto fail;
953 }
954
955 switch (dev->chipset & 0xf0) {
956 case 0x50:
957 tesla_class = NV50_3D_CLASS;
958 break;
959 case 0x80:
960 case 0x90:
961 tesla_class = NV84_3D_CLASS;
962 break;
963 case 0xa0:
964 switch (dev->chipset) {
965 case 0xa0:
966 case 0xaa:
967 case 0xac:
968 tesla_class = NVA0_3D_CLASS;
969 break;
970 case 0xaf:
971 tesla_class = NVAF_3D_CLASS;
972 break;
973 default:
974 tesla_class = NVA3_3D_CLASS;
975 break;
976 }
977 break;
978 default:
979 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset);
980 goto fail;
981 }
982 screen->base.class_3d = tesla_class;
983
984 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class,
985 NULL, 0, &screen->tesla);
986 if (ret) {
987 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret);
988 goto fail;
989 }
990
991 /* This over-allocates by a page. The GP, which would execute at the end of
992 * the last page, would trigger faults. The going theory is that it
993 * prefetches up to a certain amount.
994 */
995 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
996 (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
997 NULL, &screen->code);
998 if (ret) {
999 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
1000 goto fail;
1001 }
1002
1003 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1004 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1005 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2);
1006
1007 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
1008
1009 screen->TPs = util_bitcount(value & 0xffff);
1010 screen->MPsInTP = util_bitcount(value & 0x0f000000);
1011
1012 screen->mp_count = screen->TPs * screen->MPsInTP;
1013
1014 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP *
1015 STACK_WARPS_ALLOC * 64 * 8;
1016
1017 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL,
1018 &screen->stack_bo);
1019 if (ret) {
1020 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret);
1021 goto fail;
1022 }
1023
1024 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) *
1025 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP *
1026 ONE_TEMP_SIZE;
1027 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE;
1028 screen->max_tls_space /= 2; /* half of vram */
1029
1030 /* hw can address max 64 KiB */
1031 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10);
1032
1033 uint64_t tls_size;
1034 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE;
1035 ret = nv50_tls_alloc(screen, tls_space, &tls_size);
1036 if (ret)
1037 goto fail;
1038
1039 if (nouveau_mesa_debug)
1040 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n",
1041 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10);
1042
1043 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 5 << 16, NULL,
1044 &screen->uniforms);
1045 if (ret) {
1046 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret);
1047 goto fail;
1048 }
1049
1050 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL,
1051 &screen->txc);
1052 if (ret) {
1053 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret);
1054 goto fail;
1055 }
1056
1057 screen->tic.entries = CALLOC(4096, sizeof(void *));
1058 screen->tsc.entries = screen->tic.entries + 2048;
1059
1060 if (!nv50_blitter_create(screen))
1061 goto fail;
1062
1063 nv50_screen_init_hwctx(screen);
1064
1065 ret = nv50_screen_compute_setup(screen, screen->base.pushbuf);
1066 if (ret) {
1067 NOUVEAU_ERR("Failed to init compute context: %d\n", ret);
1068 goto fail;
1069 }
1070
1071 // submit all initial state
1072 PUSH_KICK(screen->base.pushbuf);
1073
1074 return &screen->base;
1075
1076 fail:
1077 screen->base.base.context_create = NULL;
1078 return &screen->base;
1079 }
1080
1081 int
nv50_screen_tic_alloc(struct nv50_screen * screen,void * entry)1082 nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry)
1083 {
1084 int i = screen->tic.next;
1085
1086 while (screen->tic.lock[i / 32] & (1 << (i % 32)))
1087 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1088
1089 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1);
1090
1091 if (screen->tic.entries[i])
1092 nv50_tic_entry(screen->tic.entries[i])->id = -1;
1093
1094 screen->tic.entries[i] = entry;
1095 return i;
1096 }
1097
1098 int
nv50_screen_tsc_alloc(struct nv50_screen * screen,void * entry)1099 nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry)
1100 {
1101 int i = screen->tsc.next;
1102
1103 while (screen->tsc.lock[i / 32] & (1 << (i % 32)))
1104 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1105
1106 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1);
1107
1108 if (screen->tsc.entries[i])
1109 nv50_tsc_entry(screen->tsc.entries[i])->id = -1;
1110
1111 screen->tsc.entries[i] = entry;
1112 return i;
1113 }
1114