1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #include "draw/draw_context.h"
24
25 #include "util/u_memory.h"
26 #include "util/u_sampler.h"
27 #include "util/u_upload_mgr.h"
28 #include "util/u_debug_cb.h"
29 #include "util/os_time.h"
30 #include "vl/vl_decoder.h"
31 #include "vl/vl_video_buffer.h"
32
33 #include "r300_cb.h"
34 #include "r300_context.h"
35 #include "r300_emit.h"
36 #include "r300_screen.h"
37 #include "r300_screen_buffer.h"
38 #include "compiler/radeon_regalloc.h"
39
40 #include <inttypes.h>
41
r300_release_referenced_objects(struct r300_context * r300)42 static void r300_release_referenced_objects(struct r300_context *r300)
43 {
44 struct pipe_framebuffer_state *fb =
45 (struct pipe_framebuffer_state*)r300->fb_state.state;
46 struct r300_textures_state *textures =
47 (struct r300_textures_state*)r300->textures_state.state;
48 unsigned i;
49
50 /* Framebuffer state. */
51 util_unreference_framebuffer_state(fb);
52
53 /* Textures. */
54 for (i = 0; i < textures->sampler_view_count; i++)
55 pipe_sampler_view_reference(
56 (struct pipe_sampler_view**)&textures->sampler_views[i], NULL);
57
58 /* The special dummy texture for texkill. */
59 if (r300->texkill_sampler) {
60 pipe_sampler_view_reference(
61 (struct pipe_sampler_view**)&r300->texkill_sampler,
62 NULL);
63 }
64
65 /* Manually-created vertex buffers. */
66 pipe_vertex_buffer_unreference(&r300->dummy_vb);
67 radeon_bo_reference(r300->rws, &r300->vbo, NULL);
68
69 r300->context.delete_depth_stencil_alpha_state(&r300->context,
70 r300->dsa_decompress_zmask);
71 }
72
r300_destroy_context(struct pipe_context * context)73 static void r300_destroy_context(struct pipe_context* context)
74 {
75 struct r300_context* r300 = r300_context(context);
76
77 if (r300->cs.priv && r300->hyperz_enabled) {
78 r300->rws->cs_request_feature(&r300->cs, RADEON_FID_R300_HYPERZ_ACCESS, false);
79 }
80 if (r300->cs.priv && r300->cmask_access) {
81 r300->rws->cs_request_feature(&r300->cs, RADEON_FID_R300_CMASK_ACCESS, false);
82 }
83
84 if (r300->blitter)
85 util_blitter_destroy(r300->blitter);
86 if (r300->draw)
87 draw_destroy(r300->draw);
88
89 for (unsigned i = 0; i < r300->nr_vertex_buffers; i++)
90 pipe_vertex_buffer_unreference(&r300->vertex_buffer[i]);
91
92 if (r300->uploader)
93 u_upload_destroy(r300->uploader);
94 if (r300->context.stream_uploader)
95 u_upload_destroy(r300->context.stream_uploader);
96 if (r300->context.const_uploader)
97 u_upload_destroy(r300->context.const_uploader);
98
99 /* XXX: This function assumes r300->query_list was initialized */
100 r300_release_referenced_objects(r300);
101
102 r300->rws->cs_destroy(&r300->cs);
103 if (r300->ctx)
104 r300->rws->ctx_destroy(r300->ctx);
105
106 rc_destroy_regalloc_state(&r300->fs_regalloc_state);
107 rc_destroy_regalloc_state(&r300->vs_regalloc_state);
108
109 /* XXX: No way to tell if this was initialized or not? */
110 slab_destroy_child(&r300->pool_transfers);
111
112 /* Free the structs allocated in r300_setup_atoms() */
113 if (r300->aa_state.state) {
114 FREE(r300->aa_state.state);
115 FREE(r300->blend_color_state.state);
116 FREE(r300->clip_state.state);
117 FREE(r300->fb_state.state);
118 FREE(r300->gpu_flush.state);
119 FREE(r300->hyperz_state.state);
120 FREE(r300->invariant_state.state);
121 FREE(r300->rs_block_state.state);
122 FREE(r300->sample_mask.state);
123 FREE(r300->scissor_state.state);
124 FREE(r300->textures_state.state);
125 FREE(r300->vap_invariant_state.state);
126 FREE(r300->viewport_state.state);
127 FREE(r300->ztop_state.state);
128 FREE(r300->fs_constants.state);
129 FREE(r300->vs_constants.state);
130 if (!r300->screen->caps.has_tcl) {
131 FREE(r300->vertex_stream_state.state);
132 }
133 }
134
135 FREE(r300->stencilref_fallback);
136
137 FREE(r300);
138 }
139
r300_flush_callback(void * data,unsigned flags,struct pipe_fence_handle ** fence)140 static void r300_flush_callback(void *data, unsigned flags,
141 struct pipe_fence_handle **fence)
142 {
143 struct r300_context* const cs_context_copy = data;
144
145 r300_flush(&cs_context_copy->context, flags, fence);
146 }
147
148 #define R300_INIT_ATOM(atomname, atomsize) \
149 do { \
150 r300->atomname.name = #atomname; \
151 r300->atomname.state = NULL; \
152 r300->atomname.size = atomsize; \
153 r300->atomname.emit = r300_emit_##atomname; \
154 r300->atomname.dirty = false; \
155 } while (0)
156
157 #define R300_ALLOC_ATOM(atomname, statetype) \
158 do { \
159 r300->atomname.state = CALLOC_STRUCT(statetype); \
160 if (r300->atomname.state == NULL) \
161 return false; \
162 } while (0)
163
r300_setup_atoms(struct r300_context * r300)164 static bool r300_setup_atoms(struct r300_context* r300)
165 {
166 bool is_rv350 = r300->screen->caps.is_rv350;
167 bool is_r500 = r300->screen->caps.is_r500;
168 bool has_tcl = r300->screen->caps.has_tcl;
169
170 /* Create the actual atom list.
171 *
172 * Some atoms never change size, others change every emit - those have
173 * the size of 0 here.
174 *
175 * NOTE: The framebuffer state is split into these atoms:
176 * - gpu_flush (unpipelined regs)
177 * - aa_state (unpipelined regs)
178 * - fb_state (unpipelined regs)
179 * - hyperz_state (unpipelined regs followed by pipelined ones)
180 * - fb_state_pipelined (pipelined regs)
181 * The motivation behind this is to be able to emit a strict
182 * subset of the regs, and to have reasonable register ordering. */
183 /* SC, GB (unpipelined), RB3D (unpipelined), ZB (unpipelined). */
184 R300_INIT_ATOM(gpu_flush, 9);
185 R300_INIT_ATOM(aa_state, 4);
186 R300_INIT_ATOM(fb_state, 0);
187 R300_INIT_ATOM(hyperz_state, is_r500 || is_rv350 ? 10 : 8);
188 /* ZB (unpipelined), SC. */
189 R300_INIT_ATOM(ztop_state, 2);
190 /* ZB, FG. */
191 R300_INIT_ATOM(dsa_state, is_r500 ? 10 : 6);
192 /* RB3D. */
193 R300_INIT_ATOM(blend_state, 8);
194 R300_INIT_ATOM(blend_color_state, is_r500 ? 3 : 2);
195 /* SC. */
196 R300_INIT_ATOM(sample_mask, 2);
197 R300_INIT_ATOM(scissor_state, 3);
198 /* GB, FG, GA, SU, SC, RB3D. */
199 R300_INIT_ATOM(invariant_state, 14 + (is_rv350 ? 4 : 0) + (is_r500 ? 4 : 0));
200 /* VAP. */
201 R300_INIT_ATOM(viewport_state, 9);
202 R300_INIT_ATOM(pvs_flush, 2);
203 R300_INIT_ATOM(vap_invariant_state, is_r500 || !has_tcl ? 11 : 9);
204 R300_INIT_ATOM(vertex_stream_state, 0);
205 R300_INIT_ATOM(vs_state, 0);
206 R300_INIT_ATOM(vs_constants, 0);
207 R300_INIT_ATOM(clip_state, has_tcl ? 3 + (6 * 4) : 0);
208 /* VAP, RS, GA, GB, SU, SC. */
209 R300_INIT_ATOM(rs_block_state, 0);
210 R300_INIT_ATOM(rs_state, 0);
211 /* SC, US. */
212 R300_INIT_ATOM(fb_state_pipelined, 8);
213 /* US. */
214 R300_INIT_ATOM(fs, 0);
215 R300_INIT_ATOM(fs_rc_constant_state, 0);
216 R300_INIT_ATOM(fs_constants, 0);
217 /* TX. */
218 R300_INIT_ATOM(texture_cache_inval, 2);
219 R300_INIT_ATOM(textures_state, 0);
220 /* Clear commands */
221 R300_INIT_ATOM(hiz_clear, r300->screen->caps.hiz_ram > 0 ? 4 : 0);
222 R300_INIT_ATOM(zmask_clear, r300->screen->caps.zmask_ram > 0 ? 4 : 0);
223 R300_INIT_ATOM(cmask_clear, 4);
224 /* ZB (unpipelined), SU. */
225 R300_INIT_ATOM(query_start, 4);
226
227 /* Replace emission functions for r500. */
228 if (is_r500) {
229 r300->fs.emit = r500_emit_fs;
230 r300->fs_rc_constant_state.emit = r500_emit_fs_rc_constant_state;
231 r300->fs_constants.emit = r500_emit_fs_constants;
232 }
233
234 /* Some non-CSO atoms need explicit space to store the state locally. */
235 R300_ALLOC_ATOM(aa_state, r300_aa_state);
236 R300_ALLOC_ATOM(blend_color_state, r300_blend_color_state);
237 R300_ALLOC_ATOM(clip_state, r300_clip_state);
238 R300_ALLOC_ATOM(hyperz_state, r300_hyperz_state);
239 R300_ALLOC_ATOM(invariant_state, r300_invariant_state);
240 R300_ALLOC_ATOM(textures_state, r300_textures_state);
241 R300_ALLOC_ATOM(vap_invariant_state, r300_vap_invariant_state);
242 R300_ALLOC_ATOM(viewport_state, r300_viewport_state);
243 R300_ALLOC_ATOM(ztop_state, r300_ztop_state);
244 R300_ALLOC_ATOM(fb_state, pipe_framebuffer_state);
245 R300_ALLOC_ATOM(gpu_flush, pipe_framebuffer_state);
246 r300->sample_mask.state = malloc(4);
247 R300_ALLOC_ATOM(scissor_state, pipe_scissor_state);
248 R300_ALLOC_ATOM(rs_block_state, r300_rs_block);
249 R300_ALLOC_ATOM(fs_constants, r300_constant_buffer);
250 R300_ALLOC_ATOM(vs_constants, r300_constant_buffer);
251 if (!r300->screen->caps.has_tcl) {
252 R300_ALLOC_ATOM(vertex_stream_state, r300_vertex_stream_state);
253 }
254
255 /* Some non-CSO atoms don't use the state pointer. */
256 r300->fb_state_pipelined.allow_null_state = true;
257 r300->fs_rc_constant_state.allow_null_state = true;
258 r300->pvs_flush.allow_null_state = true;
259 r300->query_start.allow_null_state = true;
260 r300->texture_cache_inval.allow_null_state = true;
261
262 /* Some states must be marked as dirty here to properly set up
263 * hardware in the first command stream. */
264 r300_mark_atom_dirty(r300, &r300->invariant_state);
265 r300_mark_atom_dirty(r300, &r300->pvs_flush);
266 r300_mark_atom_dirty(r300, &r300->vap_invariant_state);
267 r300_mark_atom_dirty(r300, &r300->texture_cache_inval);
268 r300_mark_atom_dirty(r300, &r300->textures_state);
269
270 return true;
271 }
272
273 /* Not every gallium frontend calls every driver function before the first draw
274 * call and we must initialize the command buffers somehow. */
r300_init_states(struct pipe_context * pipe)275 static void r300_init_states(struct pipe_context *pipe)
276 {
277 struct r300_context *r300 = r300_context(pipe);
278 struct pipe_blend_color bc = {{0}};
279 struct pipe_clip_state cs = {{{0}}};
280 struct pipe_scissor_state ss = {0};
281 struct r300_gpu_flush *gpuflush =
282 (struct r300_gpu_flush*)r300->gpu_flush.state;
283 struct r300_vap_invariant_state *vap_invariant =
284 (struct r300_vap_invariant_state*)r300->vap_invariant_state.state;
285 struct r300_invariant_state *invariant =
286 (struct r300_invariant_state*)r300->invariant_state.state;
287
288 CB_LOCALS;
289
290 pipe->set_blend_color(pipe, &bc);
291 pipe->set_clip_state(pipe, &cs);
292 pipe->set_scissor_states(pipe, 0, 1, &ss);
293 pipe->set_sample_mask(pipe, ~0);
294
295 /* Initialize the GPU flush. */
296 {
297 BEGIN_CB(gpuflush->cb_flush_clean, 6);
298
299 /* Flush and free renderbuffer caches. */
300 OUT_CB_REG(R300_RB3D_DSTCACHE_CTLSTAT,
301 R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
302 R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
303 OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
304 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
305 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
306
307 /* Wait until the GPU is idle.
308 * This fixes random pixels sometimes appearing probably caused
309 * by incomplete rendering. */
310 OUT_CB_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
311 END_CB;
312 }
313
314 /* Initialize the VAP invariant state. */
315 {
316 BEGIN_CB(vap_invariant->cb, r300->vap_invariant_state.size);
317 OUT_CB_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
318 OUT_CB_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
319 OUT_CB_32F(1.0);
320 OUT_CB_32F(1.0);
321 OUT_CB_32F(1.0);
322 OUT_CB_32F(1.0);
323 OUT_CB_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO);
324
325 if (r300->screen->caps.is_r500) {
326 OUT_CB_REG(R500_VAP_TEX_TO_COLOR_CNTL, 0);
327 } else if (!r300->screen->caps.has_tcl) {
328 /* RSxxx:
329 * Static VAP setup since r300_emit_vs_state() is never called.
330 */
331 OUT_CB_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(10) |
332 R300_PVS_NUM_CNTLRS(5) |
333 R300_PVS_NUM_FPUS(2) |
334 R300_PVS_VF_MAX_VTX_NUM(5));
335 }
336 END_CB;
337 }
338
339 /* Initialize the invariant state. */
340 {
341 BEGIN_CB(invariant->cb, r300->invariant_state.size);
342 OUT_CB_REG(R300_GB_SELECT, 0);
343 OUT_CB_REG(R300_FG_FOG_BLEND, 0);
344 OUT_CB_REG(R300_GA_OFFSET, 0);
345 OUT_CB_REG(R300_SU_TEX_WRAP, 0);
346 OUT_CB_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
347 OUT_CB_REG(R300_SU_DEPTH_OFFSET, 0);
348 OUT_CB_REG(R300_SC_EDGERULE, 0x2DA49525);
349
350 if (r300->screen->caps.is_rv350) {
351 OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
352 OUT_CB_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE);
353 }
354
355 if (r300->screen->caps.is_r500) {
356 OUT_CB_REG(R500_GA_COLOR_CONTROL_PS3, 0);
357 OUT_CB_REG(R500_SU_TEX_WRAP_PS3, 0);
358 }
359 END_CB;
360 }
361
362 /* Initialize the hyperz state. */
363 {
364 struct r300_hyperz_state *hyperz =
365 (struct r300_hyperz_state*)r300->hyperz_state.state;
366 BEGIN_CB(&hyperz->cb_flush_begin, r300->hyperz_state.size);
367 OUT_CB_REG(R300_ZB_ZCACHE_CTLSTAT,
368 R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
369 OUT_CB_REG(R300_ZB_BW_CNTL, 0);
370 OUT_CB_REG(R300_ZB_DEPTHCLEARVALUE, 0);
371 OUT_CB_REG(R300_SC_HYPERZ, R300_SC_HYPERZ_ADJ_2);
372
373 if (r300->screen->caps.is_r500 || r300->screen->caps.is_rv350) {
374 OUT_CB_REG(R300_GB_Z_PEQ_CONFIG, 0);
375 }
376 END_CB;
377 }
378 }
379
r300_create_context(struct pipe_screen * screen,void * priv,unsigned flags)380 struct pipe_context* r300_create_context(struct pipe_screen* screen,
381 void *priv, unsigned flags)
382 {
383 struct r300_context* r300 = CALLOC_STRUCT(r300_context);
384 struct r300_screen* r300screen = r300_screen(screen);
385 struct radeon_winsys *rws = r300screen->rws;
386
387 if (!r300)
388 return NULL;
389
390 r300->rws = rws;
391 r300->screen = r300screen;
392
393 r300->context.screen = screen;
394 r300->context.priv = priv;
395 r300->context.set_debug_callback = u_default_set_debug_callback;
396
397 r300->context.destroy = r300_destroy_context;
398
399 slab_create_child(&r300->pool_transfers, &r300screen->pool_transfers);
400
401 r300->ctx = rws->ctx_create(rws, RADEON_CTX_PRIORITY_MEDIUM, false);
402 if (!r300->ctx)
403 goto fail;
404
405
406 if (!rws->cs_create(&r300->cs, r300->ctx, AMD_IP_GFX, r300_flush_callback, r300))
407 goto fail;
408
409 if (!r300screen->caps.has_tcl) {
410 /* Create a Draw. This is used for SW TCL. */
411 r300->draw = draw_create(&r300->context);
412 if (r300->draw == NULL)
413 goto fail;
414 /* Enable our renderer. */
415 draw_set_rasterize_stage(r300->draw, r300_draw_stage(r300));
416 /* Disable converting points/lines to triangles. */
417 draw_wide_line_threshold(r300->draw, 10000000.f);
418 draw_wide_point_threshold(r300->draw, 10000000.f);
419 draw_wide_point_sprites(r300->draw, false);
420 draw_enable_line_stipple(r300->draw, true);
421 draw_enable_point_sprites(r300->draw, false);
422 }
423
424 if (!r300_setup_atoms(r300))
425 goto fail;
426
427 r300_init_blit_functions(r300);
428 r300_init_flush_functions(r300);
429 r300_init_query_functions(r300);
430 r300_init_state_functions(r300);
431 r300_init_resource_functions(r300);
432 r300_init_render_functions(r300);
433 r300_init_states(&r300->context);
434
435 r300->context.create_video_codec = vl_create_decoder;
436 r300->context.create_video_buffer = vl_video_buffer_create;
437
438 r300->uploader = u_upload_create(&r300->context, 128 * 1024,
439 PIPE_BIND_CUSTOM, PIPE_USAGE_STREAM, 0);
440 r300->context.stream_uploader = u_upload_create(&r300->context, 1024 * 1024,
441 0, PIPE_USAGE_STREAM, 0);
442 r300->context.const_uploader = u_upload_create(&r300->context, 1024 * 1024,
443 PIPE_BIND_CONSTANT_BUFFER,
444 PIPE_USAGE_STREAM, 0);
445
446 r300->blitter = util_blitter_create(&r300->context);
447 if (r300->blitter == NULL)
448 goto fail;
449 r300->blitter->draw_rectangle = r300_blitter_draw_rectangle;
450
451 /* The KIL opcode needs the first texture unit to be enabled
452 * on r3xx-r4xx. In order to calm down the CS checker, we bind this
453 * dummy texture there. */
454 if (!r300->screen->caps.is_r500) {
455 struct pipe_resource *tex;
456 struct pipe_resource rtempl = {0};
457 struct pipe_sampler_view vtempl = {0};
458
459 rtempl.target = PIPE_TEXTURE_2D;
460 rtempl.format = PIPE_FORMAT_I8_UNORM;
461 rtempl.usage = PIPE_USAGE_IMMUTABLE;
462 rtempl.width0 = 1;
463 rtempl.height0 = 1;
464 rtempl.depth0 = 1;
465 tex = screen->resource_create(screen, &rtempl);
466
467 u_sampler_view_default_template(&vtempl, tex, tex->format);
468
469 r300->texkill_sampler = (struct r300_sampler_view*)
470 r300->context.create_sampler_view(&r300->context, tex, &vtempl);
471
472 pipe_resource_reference(&tex, NULL);
473 }
474
475 if (r300screen->caps.has_tcl) {
476 struct pipe_resource vb;
477 memset(&vb, 0, sizeof(vb));
478 vb.target = PIPE_BUFFER;
479 vb.format = PIPE_FORMAT_R8_UNORM;
480 vb.usage = PIPE_USAGE_DEFAULT;
481 vb.width0 = sizeof(float) * 16;
482 vb.height0 = 1;
483 vb.depth0 = 1;
484
485 r300->dummy_vb.buffer.resource = screen->resource_create(screen, &vb);
486 util_set_vertex_buffers(&r300->context, 1, false, &r300->dummy_vb);
487 }
488
489 {
490 struct pipe_depth_stencil_alpha_state dsa;
491 memset(&dsa, 0, sizeof(dsa));
492 dsa.depth_writemask = 1;
493
494 r300->dsa_decompress_zmask =
495 r300->context.create_depth_stencil_alpha_state(&r300->context,
496 &dsa);
497 }
498
499 r300->hyperz_time_of_last_flush = os_time_get();
500
501 /* Register allocator state */
502 rc_init_regalloc_state(&r300->fs_regalloc_state, RC_FRAGMENT_PROGRAM);
503 rc_init_regalloc_state(&r300->vs_regalloc_state, RC_VERTEX_PROGRAM);
504
505 /* Print driver info. */
506 #ifdef DEBUG
507 {
508 #else
509 if (DBG_ON(r300, DBG_INFO)) {
510 #endif
511 fprintf(stderr,
512 "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
513 "r300: GART size: %u MB, VRAM size: %u MB\n"
514 "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
515 r300->screen->info.drm_major,
516 r300->screen->info.drm_minor,
517 r300->screen->info.drm_patchlevel,
518 screen->get_name(screen),
519 r300->screen->info.pci_id,
520 r300->screen->info.r300_num_gb_pipes,
521 r300->screen->info.r300_num_z_pipes,
522 r300->screen->info.gart_size_kb >> 10,
523 r300->screen->info.vram_size_kb >> 10,
524 "YES", /* XXX really? */
525 r300->screen->caps.zmask_ram ? "YES" : "NO",
526 r300->screen->caps.hiz_ram ? "YES" : "NO");
527 }
528
529 return &r300->context;
530
531 fail:
532 r300_destroy_context(&r300->context);
533 return NULL;
534 }
535