1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "r600_pipe_common.h"
30 #include "r600_cs.h"
31 #include "r600_public.h"
32 #include "pipe/p_defines.h"
33
34 #include "util/u_suballoc.h"
35 #include "util/list.h"
36 #include "util/u_transfer.h"
37 #include "util/u_memory.h"
38
39 #include "tgsi/tgsi_scan.h"
40
41 #define R600_NUM_ATOMS 56
42
43 #define R600_MAX_IMAGES 8
44 /*
45 * ranges reserved for images on evergreen
46 * first set for the immediate buffers,
47 * second for the actual resources for RESQ.
48 */
49 #define R600_IMAGE_IMMED_RESOURCE_OFFSET 160
50 #define R600_IMAGE_REAL_RESOURCE_OFFSET 168
51
52 /* read caches */
53 #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
54 #define R600_CONTEXT_INV_TEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 1)
55 #define R600_CONTEXT_INV_CONST_CACHE (R600_CONTEXT_PRIVATE_FLAG << 2)
56 /* read-write caches */
57 #define R600_CONTEXT_FLUSH_AND_INV (R600_CONTEXT_PRIVATE_FLAG << 3)
58 #define R600_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
59 #define R600_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
60 #define R600_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
61 #define R600_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
62 /* engine synchronization */
63 #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
64 #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9)
65 #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10)
66 #define R600_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
67
68 /* the number of CS dwords for flushing and drawing */
69 #define R600_MAX_FLUSH_CS_DWORDS 18
70 #define R600_MAX_DRAW_CS_DWORDS 58
71 #define R600_MAX_PFP_SYNC_ME_DWORDS 16
72
73 #define EG_MAX_ATOMIC_BUFFERS 8
74
75 #define R600_MAX_USER_CONST_BUFFERS 15
76 #define R600_MAX_DRIVER_CONST_BUFFERS 3
77 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
78
79 /* start driver buffers after user buffers */
80 #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
81 #define R600_UCP_SIZE (4*4*8)
82 #define R600_CS_BLOCK_GRID_SIZE (8 * 4)
83 #define R600_TCS_DEFAULT_LEVELS_SIZE (6 * 4)
84 #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE)
85
86 /*
87 * We only access this buffer through vtx clauses hence it's fine to exist
88 * at index beyond 15.
89 */
90 #define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
91 /*
92 * Note GS doesn't use a constant buffer binding, just a resource index,
93 * so it's fine to have it exist at index beyond 15. I.e. it's not actually
94 * a const buffer, just a buffer resource.
95 */
96 #define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
97 /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit
98 * of 16 const buffers.
99 * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id.
100 *
101 * In order to support d3d 11 mandated minimum of 15 user const buffers
102 * we'd have to squash all use cases into one driver buffer.
103 */
104 #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4]))
105
106 /* HW stages */
107 #define R600_HW_STAGE_PS 0
108 #define R600_HW_STAGE_VS 1
109 #define R600_HW_STAGE_GS 2
110 #define R600_HW_STAGE_ES 3
111 #define EG_HW_STAGE_LS 4
112 #define EG_HW_STAGE_HS 5
113
114 #define R600_NUM_HW_STAGES 4
115 #define EG_NUM_HW_STAGES 6
116
117 struct r600_context;
118 struct r600_bytecode;
119 union r600_shader_key;
120
121 /* This is an atom containing GPU commands that never change.
122 * This is supposed to be copied directly into the CS. */
123 struct r600_command_buffer {
124 uint32_t *buf;
125 unsigned num_dw;
126 unsigned max_num_dw;
127 unsigned pkt_flags;
128 };
129
130 struct r600_db_state {
131 struct r600_atom atom;
132 struct r600_surface *rsurf;
133 };
134
135 struct r600_db_misc_state {
136 struct r600_atom atom;
137 bool occlusion_queries_disabled;
138 bool flush_depthstencil_through_cb;
139 bool flush_depth_inplace;
140 bool flush_stencil_inplace;
141 bool copy_depth, copy_stencil;
142 unsigned copy_sample;
143 unsigned log_samples;
144 unsigned db_shader_control;
145 bool htile_clear;
146 uint8_t ps_conservative_z;
147 };
148
149 struct r600_cb_misc_state {
150 struct r600_atom atom;
151 unsigned cb_color_control; /* this comes from blend state */
152 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
153 unsigned nr_cbufs;
154 unsigned bound_cbufs_target_mask;
155 unsigned nr_ps_color_outputs;
156 unsigned ps_color_export_mask;
157 unsigned image_rat_enabled_mask;
158 unsigned buffer_rat_enabled_mask;
159 bool multiwrite;
160 bool dual_src_blend;
161 };
162
163 struct r600_clip_misc_state {
164 struct r600_atom atom;
165 unsigned pa_cl_clip_cntl; /* from rasterizer */
166 unsigned pa_cl_vs_out_cntl; /* from vertex shader */
167 unsigned clip_plane_enable; /* from rasterizer */
168 unsigned cc_dist_mask; /* from vertex shader */
169 unsigned clip_dist_write; /* from vertex shader */
170 unsigned cull_dist_write; /* from vertex shader */
171 bool clip_disable; /* from vertex shader */
172 bool vs_out_viewport; /* from vertex shader */
173 };
174
175 struct r600_alphatest_state {
176 struct r600_atom atom;
177 unsigned sx_alpha_test_control; /* this comes from dsa state */
178 unsigned sx_alpha_ref; /* this comes from dsa state */
179 bool bypass;
180 bool cb0_export_16bpc; /* from set_framebuffer_state */
181 };
182
183 struct r600_vgt_state {
184 struct r600_atom atom;
185 uint32_t vgt_multi_prim_ib_reset_en;
186 uint32_t vgt_multi_prim_ib_reset_indx;
187 uint32_t vgt_indx_offset;
188 bool last_draw_was_indirect;
189 };
190
191 struct r600_blend_color {
192 struct r600_atom atom;
193 struct pipe_blend_color state;
194 };
195
196 struct r600_clip_state {
197 struct r600_atom atom;
198 struct pipe_clip_state state;
199 };
200
201 struct r600_cs_shader_state {
202 struct r600_atom atom;
203 unsigned kernel_index;
204 unsigned pc;
205 struct r600_pipe_compute *shader;
206 };
207
208 struct r600_framebuffer {
209 struct r600_atom atom;
210 struct pipe_framebuffer_state state;
211 unsigned compressed_cb_mask;
212 unsigned nr_samples;
213 bool export_16bpc;
214 bool cb0_is_integer;
215 bool is_msaa_resolve;
216 bool dual_src_blend;
217 bool do_update_surf_dirtiness;
218 };
219
220 struct r600_sample_mask {
221 struct r600_atom atom;
222 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
223 };
224
225 struct r600_config_state {
226 struct r600_atom atom;
227 unsigned sq_gpr_resource_mgmt_1;
228 unsigned sq_gpr_resource_mgmt_2;
229 unsigned sq_gpr_resource_mgmt_3;
230 bool dyn_gpr_enabled;
231 };
232
233 struct r600_stencil_ref
234 {
235 uint8_t ref_value[2];
236 uint8_t valuemask[2];
237 uint8_t writemask[2];
238 };
239
240 struct r600_stencil_ref_state {
241 struct r600_atom atom;
242 struct r600_stencil_ref state;
243 struct pipe_stencil_ref pipe_state;
244 };
245
246 struct r600_shader_stages_state {
247 struct r600_atom atom;
248 unsigned geom_enable;
249 };
250
251 struct r600_gs_rings_state {
252 struct r600_atom atom;
253 unsigned enable;
254 struct pipe_constant_buffer esgs_ring;
255 struct pipe_constant_buffer gsvs_ring;
256 };
257
258 /* This must start from 16. */
259 /* features */
260 #define DBG_NO_CP_DMA (1 << 30)
261
262 struct r600_screen {
263 struct r600_common_screen b;
264 bool has_msaa;
265 bool has_compressed_msaa_texturing;
266 bool has_atomics;
267
268 /*for compute global memory binding, we allocate stuff here, instead of
269 * buffers.
270 * XXX: Not sure if this is the best place for global_pool. Also,
271 * it's not thread safe, so it won't work with multiple contexts. */
272 struct compute_memory_pool *global_pool;
273 };
274
275 struct r600_pipe_sampler_view {
276 struct pipe_sampler_view base;
277 struct list_head list;
278 struct r600_resource *tex_resource;
279 uint32_t tex_resource_words[8];
280 bool skip_mip_address_reloc;
281 bool is_stencil_sampler;
282 };
283
284 struct r600_rasterizer_state {
285 struct r600_command_buffer buffer;
286 bool flatshade;
287 bool two_side;
288 unsigned sprite_coord_enable;
289 unsigned clip_plane_enable;
290 unsigned pa_sc_line_stipple;
291 unsigned pa_cl_clip_cntl;
292 unsigned pa_su_sc_mode_cntl;
293 float offset_units;
294 float offset_scale;
295 bool offset_enable;
296 bool offset_units_unscaled;
297 bool scissor_enable;
298 bool multisample_enable;
299 bool clip_halfz;
300 bool rasterizer_discard;
301 };
302
303 struct r600_poly_offset_state {
304 struct r600_atom atom;
305 enum pipe_format zs_format;
306 float offset_units;
307 float offset_scale;
308 bool offset_units_unscaled;
309 };
310
311 struct r600_blend_state {
312 struct r600_command_buffer buffer;
313 struct r600_command_buffer buffer_no_blend;
314 unsigned cb_target_mask;
315 unsigned cb_color_control;
316 unsigned cb_color_control_no_blend;
317 bool dual_src_blend;
318 bool alpha_to_one;
319 };
320
321 struct r600_dsa_state {
322 struct r600_command_buffer buffer;
323 unsigned alpha_ref;
324 uint8_t valuemask[2];
325 uint8_t writemask[2];
326 unsigned zwritemask;
327 unsigned sx_alpha_test_control;
328 };
329
330 struct r600_pipe_shader;
331
332 struct r600_pipe_shader_selector {
333 struct r600_pipe_shader *current;
334
335 struct tgsi_token *tokens;
336 struct nir_shader *nir;
337
338 size_t nir_blob_size;
339 void *nir_blob;
340
341 struct pipe_stream_output_info so;
342 struct tgsi_shader_info info;
343
344 unsigned num_shaders;
345
346 enum pipe_shader_type type;
347 enum pipe_shader_ir ir_type;
348
349 /* geometry shader properties */
350 enum mesa_prim gs_output_prim;
351 unsigned gs_max_out_vertices;
352 unsigned gs_num_invocations;
353
354 /* TCS/VS */
355 uint64_t lds_patch_outputs_written_mask;
356 uint64_t lds_outputs_written_mask;
357 };
358
359 struct r600_pipe_sampler_state {
360 uint32_t tex_sampler_words[3];
361 union pipe_color_union border_color;
362 bool border_color_use;
363 bool seamless_cube_map;
364 };
365
366 /* needed for blitter save */
367 #define NUM_TEX_UNITS 16
368
369 struct r600_seamless_cube_map {
370 struct r600_atom atom;
371 bool enabled;
372 };
373
374 struct r600_samplerview_state {
375 struct r600_atom atom;
376 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
377 uint32_t enabled_mask;
378 uint32_t dirty_mask;
379 uint32_t compressed_depthtex_mask; /* which textures are depth */
380 uint32_t compressed_colortex_mask;
381 bool dirty_buffer_constants;
382 };
383
384 struct r600_sampler_states {
385 struct r600_atom atom;
386 struct r600_pipe_sampler_state *states[NUM_TEX_UNITS];
387 uint32_t enabled_mask;
388 uint32_t dirty_mask;
389 uint32_t has_bordercolor_mask; /* which states contain the border color */
390 };
391
392 struct r600_textures_info {
393 struct r600_samplerview_state views;
394 struct r600_sampler_states states;
395 bool is_array_sampler[NUM_TEX_UNITS];
396 };
397
398 struct r600_shader_driver_constants_info {
399 /* currently 128 bytes for UCP/samplepos + sampler buffer constants */
400 uint32_t *constants;
401 uint32_t alloc_size;
402 bool texture_const_dirty;
403 bool vs_ucp_dirty;
404 bool ps_sample_pos_dirty;
405 bool cs_block_grid_size_dirty;
406 bool tcs_default_levels_dirty;
407 };
408
409 struct r600_constbuf_state
410 {
411 struct r600_atom atom;
412 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
413 uint32_t enabled_mask;
414 uint32_t dirty_mask;
415 };
416
417 struct r600_vertexbuf_state
418 {
419 struct r600_atom atom;
420 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
421 uint32_t enabled_mask; /* non-NULL buffers */
422 uint32_t dirty_mask;
423 };
424
425 /* CSO (constant state object, in other words, immutable state). */
426 struct r600_cso_state
427 {
428 struct r600_atom atom;
429 void *cso; /* e.g. r600_blend_state */
430 struct r600_command_buffer *cb;
431 };
432
433 struct r600_fetch_shader {
434 struct r600_resource *buffer;
435 unsigned offset;
436 uint32_t buffer_mask;
437 unsigned strides[PIPE_MAX_ATTRIBS];
438 };
439
440 struct r600_shader_state {
441 struct r600_atom atom;
442 struct r600_pipe_shader *shader;
443 };
444
445 struct r600_atomic_buffer_state {
446 struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS];
447 };
448
449 struct r600_image_view {
450 struct pipe_image_view base;
451 uint32_t cb_color_base;
452 uint32_t cb_color_pitch;
453 uint32_t cb_color_slice;
454 uint32_t cb_color_view;
455 uint32_t cb_color_info;
456 uint32_t cb_color_attrib;
457 uint32_t cb_color_dim;
458 uint32_t cb_color_fmask;
459 uint32_t cb_color_fmask_slice;
460 uint32_t immed_resource_words[8];
461 uint32_t resource_words[8];
462 bool skip_mip_address_reloc;
463 uint32_t buf_size;
464 };
465
466 struct r600_image_state {
467 struct r600_atom atom;
468 uint32_t enabled_mask;
469 uint32_t dirty_mask;
470 uint32_t compressed_depthtex_mask;
471 uint32_t compressed_colortex_mask;
472 bool dirty_buffer_constants;
473 struct r600_image_view views[R600_MAX_IMAGES];
474 };
475
476 /* Used to spill shader temps */
477 struct r600_scratch_buffer {
478 struct r600_resource *buffer;
479 bool dirty;
480 unsigned size;
481 unsigned item_size;
482 };
483
484 struct r600_context {
485 struct r600_common_context b;
486 struct r600_screen *screen;
487 struct blitter_context *blitter;
488 struct u_suballocator allocator_fetch_shader;
489
490 /* Hardware info. */
491 bool has_vertex_cache;
492 unsigned default_gprs[EG_NUM_HW_STAGES];
493 unsigned current_gprs[EG_NUM_HW_STAGES];
494 unsigned r6xx_num_clause_temp_gprs;
495
496 /* Miscellaneous state objects. */
497 void *custom_dsa_flush;
498 void *custom_blend_resolve;
499 void *custom_blend_decompress;
500 void *custom_blend_fastclear;
501 /* With rasterizer discard, there doesn't have to be a pixel shader.
502 * In that case, we bind this one: */
503 void *dummy_pixel_shader;
504 /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware
505 * bug where valid CMASK and FMASK are required to be present to avoid
506 * a hardlock in certain operations but aren't actually used
507 * for anything useful. */
508 struct r600_resource *dummy_fmask;
509 struct r600_resource *dummy_cmask;
510
511 /* State binding slots are here. */
512 struct r600_atom *atoms[R600_NUM_ATOMS];
513 /* Dirty atom bitmask for fast tests */
514 uint64_t dirty_atoms;
515 /* States for CS initialization. */
516 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
517 /** Compute specific registers initializations. The start_cs_cmd atom
518 * must be emitted before start_compute_cs_cmd. */
519 struct r600_command_buffer start_compute_cs_cmd;
520 /* Register states. */
521 struct r600_alphatest_state alphatest_state;
522 struct r600_cso_state blend_state;
523 struct r600_blend_color blend_color;
524 struct r600_cb_misc_state cb_misc_state;
525 struct r600_clip_misc_state clip_misc_state;
526 struct r600_clip_state clip_state;
527 struct r600_db_misc_state db_misc_state;
528 struct r600_db_state db_state;
529 struct r600_cso_state dsa_state;
530 struct r600_framebuffer framebuffer;
531 struct r600_poly_offset_state poly_offset_state;
532 struct r600_cso_state rasterizer_state;
533 struct r600_sample_mask sample_mask;
534 struct r600_seamless_cube_map seamless_cube_map;
535 struct r600_config_state config_state;
536 struct r600_stencil_ref_state stencil_ref;
537 struct r600_vgt_state vgt_state;
538 struct r600_atomic_buffer_state atomic_buffer_state;
539 /* only have images on fragment shader */
540 struct r600_image_state fragment_images;
541 struct r600_image_state compute_images;
542 struct r600_image_state fragment_buffers;
543 struct r600_image_state compute_buffers;
544 /* Shaders and shader resources. */
545 struct r600_cso_state vertex_fetch_shader;
546 struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES];
547 struct r600_cs_shader_state cs_shader_state;
548 struct r600_shader_stages_state shader_stages;
549 struct r600_gs_rings_state gs_rings;
550 struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
551 struct r600_textures_info samplers[PIPE_SHADER_TYPES];
552
553 struct r600_shader_driver_constants_info driver_consts[PIPE_SHADER_TYPES];
554
555 /** Vertex buffers for fetch shaders */
556 struct r600_vertexbuf_state vertex_buffer_state;
557 /** Vertex buffers for compute shaders */
558 struct r600_vertexbuf_state cs_vertex_buffer_state;
559
560 /* Additional context states. */
561 unsigned compute_cb_target_mask;
562 struct r600_pipe_shader_selector *ps_shader;
563 struct r600_pipe_shader_selector *vs_shader;
564 struct r600_pipe_shader_selector *gs_shader;
565
566 struct r600_pipe_shader_selector *tcs_shader;
567 struct r600_pipe_shader_selector *tes_shader;
568
569 struct r600_pipe_shader_selector *fixed_func_tcs_shader;
570
571 struct r600_rasterizer_state *rasterizer;
572 bool alpha_to_one;
573 bool force_blend_disable;
574 bool gs_tri_strip_adj_fix;
575 bool dual_src_blend;
576 unsigned zwritemask;
577 unsigned ps_iter_samples;
578
579 /* The list of all texture buffer objects in this context.
580 * This list is walked when a buffer is invalidated/reallocated and
581 * the GPU addresses are updated. */
582 struct list_head texture_buffers;
583
584 /* Last draw state (-1 = unset). */
585 enum mesa_prim last_primitive_type; /* Last primitive type used in draw_vbo. */
586 enum mesa_prim current_rast_prim; /* primitive type after TES, GS */
587 enum mesa_prim last_rast_prim;
588 unsigned last_start_instance;
589
590 struct r600_isa *isa;
591 float sample_positions[4 * 16];
592 float tess_state[8];
593 uint32_t cs_block_grid_sizes[8]; /* 3 for grid + 1 pad, 3 for block + 1 pad*/
594 struct r600_pipe_shader_selector *last_ls;
595 struct r600_pipe_shader_selector *last_tcs;
596 unsigned last_num_tcs_input_cp;
597 unsigned lds_alloc;
598
599 struct r600_scratch_buffer scratch_buffers[MAX2(R600_NUM_HW_STAGES, EG_NUM_HW_STAGES)];
600
601 /* Debug state. */
602 bool is_debug;
603 struct radeon_saved_cs last_gfx;
604 struct r600_resource *last_trace_buf;
605 struct r600_resource *trace_buf;
606 unsigned trace_id;
607
608 uint8_t patch_vertices;
609 bool cmd_buf_is_compute;
610 struct pipe_resource *append_fence;
611 uint32_t append_fence_id;
612 };
613
r600_emit_command_buffer(struct radeon_cmdbuf * cs,struct r600_command_buffer * cb)614 static inline void r600_emit_command_buffer(struct radeon_cmdbuf *cs,
615 struct r600_command_buffer *cb)
616 {
617 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw);
618 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw);
619 cs->current.cdw += cb->num_dw;
620 }
621
r600_set_atom_dirty(struct r600_context * rctx,struct r600_atom * atom,bool dirty)622 static inline void r600_set_atom_dirty(struct r600_context *rctx,
623 struct r600_atom *atom,
624 bool dirty)
625 {
626 uint64_t mask;
627
628 assert(atom->id != 0);
629 assert(atom->id < sizeof(mask) * 8);
630 mask = 1ull << atom->id;
631 if (dirty)
632 rctx->dirty_atoms |= mask;
633 else
634 rctx->dirty_atoms &= ~mask;
635 }
636
r600_mark_atom_dirty(struct r600_context * rctx,struct r600_atom * atom)637 static inline void r600_mark_atom_dirty(struct r600_context *rctx,
638 struct r600_atom *atom)
639 {
640 r600_set_atom_dirty(rctx, atom, true);
641 }
642
r600_emit_atom(struct r600_context * rctx,struct r600_atom * atom)643 static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
644 {
645 atom->emit(&rctx->b, atom);
646 r600_set_atom_dirty(rctx, atom, false);
647 }
648
r600_set_cso_state(struct r600_context * rctx,struct r600_cso_state * state,void * cso)649 static inline void r600_set_cso_state(struct r600_context *rctx,
650 struct r600_cso_state *state, void *cso)
651 {
652 state->cso = cso;
653 r600_set_atom_dirty(rctx, &state->atom, cso != NULL);
654 }
655
r600_set_cso_state_with_cb(struct r600_context * rctx,struct r600_cso_state * state,void * cso,struct r600_command_buffer * cb)656 static inline void r600_set_cso_state_with_cb(struct r600_context *rctx,
657 struct r600_cso_state *state, void *cso,
658 struct r600_command_buffer *cb)
659 {
660 state->cb = cb;
661 state->atom.num_dw = cb ? cb->num_dw : 0;
662 r600_set_cso_state(rctx, state, cso);
663 }
664
665 /* compute_memory_pool.c */
666 struct compute_memory_pool;
667 void compute_memory_pool_delete(struct compute_memory_pool* pool);
668 struct compute_memory_pool* compute_memory_pool_new(
669 struct r600_screen *rscreen);
670
671 /* evergreen_state.c */
672 struct pipe_sampler_view *
673 evergreen_create_sampler_view_custom(struct pipe_context *ctx,
674 struct pipe_resource *texture,
675 const struct pipe_sampler_view *state,
676 unsigned width0, unsigned height0,
677 unsigned force_level);
678 void evergreen_init_common_regs(struct r600_context *ctx,
679 struct r600_command_buffer *cb,
680 enum amd_gfx_level ctx_chip_class,
681 enum radeon_family ctx_family,
682 int ctx_drm_minor);
683 void cayman_init_common_regs(struct r600_command_buffer *cb,
684 enum amd_gfx_level ctx_chip_class,
685 enum radeon_family ctx_family,
686 int ctx_drm_minor);
687
688 void evergreen_init_state_functions(struct r600_context *rctx);
689 void evergreen_init_atom_start_cs(struct r600_context *rctx);
690 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
691 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
692 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
693 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
694 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
695 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
696 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
697 void *evergreen_create_resolve_blend(struct r600_context *rctx);
698 void *evergreen_create_decompress_blend(struct r600_context *rctx);
699 void *evergreen_create_fastclear_blend(struct r600_context *rctx);
700 bool evergreen_is_format_supported(struct pipe_screen *screen,
701 enum pipe_format format,
702 enum pipe_texture_target target,
703 unsigned sample_count,
704 unsigned storage_sample_count,
705 unsigned usage);
706 void evergreen_init_color_surface(struct r600_context *rctx,
707 struct r600_surface *surf);
708 void evergreen_init_color_surface_rat(struct r600_context *rctx,
709 struct r600_surface *surf);
710 void evergreen_update_db_shader_control(struct r600_context * rctx);
711 bool evergreen_adjust_gprs(struct r600_context *rctx);
712 void evergreen_setup_scratch_buffers(struct r600_context *rctx);
713 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
714 unsigned nr_cbufs);
715 /* r600_blit.c */
716 void r600_init_blit_functions(struct r600_context *rctx);
717 void r600_decompress_depth_textures(struct r600_context *rctx,
718 struct r600_samplerview_state *textures);
719 void r600_decompress_depth_images(struct r600_context *rctx,
720 struct r600_image_state *images);
721 void r600_decompress_color_textures(struct r600_context *rctx,
722 struct r600_samplerview_state *textures);
723 void r600_decompress_color_images(struct r600_context *rctx,
724 struct r600_image_state *images);
725 void r600_resource_copy_region(struct pipe_context *ctx,
726 struct pipe_resource *dst,
727 unsigned dst_level,
728 unsigned dstx, unsigned dsty, unsigned dstz,
729 struct pipe_resource *src,
730 unsigned src_level,
731 const struct pipe_box *src_box);
732
733 /* r600_shader.c */
734 int r600_pipe_shader_create(struct pipe_context *ctx,
735 struct r600_pipe_shader *shader,
736 union r600_shader_key key);
737
738 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
739
740 /* r600_state.c */
741 struct pipe_sampler_view *
742 r600_create_sampler_view_custom(struct pipe_context *ctx,
743 struct pipe_resource *texture,
744 const struct pipe_sampler_view *state,
745 unsigned width_first_level, unsigned height_first_level);
746 void r600_init_state_functions(struct r600_context *rctx);
747 void r600_init_atom_start_cs(struct r600_context *rctx);
748 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
749 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
750 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
751 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader);
752 void *r600_create_db_flush_dsa(struct r600_context *rctx);
753 void *r600_create_resolve_blend(struct r600_context *rctx);
754 void *r700_create_resolve_blend(struct r600_context *rctx);
755 void *r600_create_decompress_blend(struct r600_context *rctx);
756 bool r600_adjust_gprs(struct r600_context *rctx);
757 bool r600_is_format_supported(struct pipe_screen *screen,
758 enum pipe_format format,
759 enum pipe_texture_target target,
760 unsigned sample_count,
761 unsigned storage_sample_count,
762 unsigned usage);
763 void r600_update_db_shader_control(struct r600_context * rctx);
764 void r600_setup_scratch_buffers(struct r600_context *rctx);
765
766 /* r600_hw_context.c */
767 void r600_context_gfx_flush(void *context, unsigned flags,
768 struct pipe_fence_handle **fence);
769 void r600_begin_new_cs(struct r600_context *ctx);
770 void r600_flush_emit(struct r600_context *ctx);
771 void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, bool count_draw_in, unsigned num_atomics);
772 void r600_emit_pfp_sync_me(struct r600_context *rctx);
773 void r600_cp_dma_copy_buffer(struct r600_context *rctx,
774 struct pipe_resource *dst, uint64_t dst_offset,
775 struct pipe_resource *src, uint64_t src_offset,
776 unsigned size);
777 void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
778 struct pipe_resource *dst, uint64_t offset,
779 unsigned size, uint32_t clear_value,
780 enum r600_coherency coher);
781 void r600_dma_copy_buffer(struct r600_context *rctx,
782 struct pipe_resource *dst,
783 struct pipe_resource *src,
784 uint64_t dst_offset,
785 uint64_t src_offset,
786 uint64_t size);
787
788 /*
789 * evergreen_hw_context.c
790 */
791 void evergreen_dma_copy_buffer(struct r600_context *rctx,
792 struct pipe_resource *dst,
793 struct pipe_resource *src,
794 uint64_t dst_offset,
795 uint64_t src_offset,
796 uint64_t size);
797 void evergreen_setup_tess_constants(struct r600_context *rctx,
798 const struct pipe_draw_info *info,
799 unsigned *num_patches);
800 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
801 const struct pipe_draw_info *info,
802 unsigned num_patches);
803 void evergreen_set_ls_hs_config(struct r600_context *rctx,
804 struct radeon_cmdbuf *cs,
805 uint32_t ls_hs_config);
806 void evergreen_set_lds_alloc(struct r600_context *rctx,
807 struct radeon_cmdbuf *cs,
808 uint32_t lds_alloc);
809
810 /* r600_state_common.c */
811 void r600_init_common_state_functions(struct r600_context *rctx);
812 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
813 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
814 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom);
815 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom);
816 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom);
817 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
818 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a);
819 void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id);
820 void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
821 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
822 unsigned num_dw);
823 void r600_vertex_buffers_dirty(struct r600_context *rctx);
824 void r600_sampler_views_dirty(struct r600_context *rctx,
825 struct r600_samplerview_state *state);
826 void r600_sampler_states_dirty(struct r600_context *rctx,
827 struct r600_sampler_states *state);
828 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
829 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx);
830 void r600_setup_scratch_area_for_shader(struct r600_context *rctx,
831 struct r600_pipe_shader *shader, struct r600_scratch_buffer *scratch,
832 unsigned ring_base_reg, unsigned item_size_reg, unsigned ring_size_reg);
833 uint32_t r600_translate_stencil_op(int s_op);
834 uint32_t r600_translate_fill(uint32_t func);
835 unsigned r600_tex_wrap(unsigned wrap);
836 unsigned r600_tex_mipfilter(unsigned filter);
837 unsigned r600_tex_compare(unsigned compare);
838 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state);
839 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
840 const unsigned char *swizzle_view,
841 bool vtx);
842 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
843 const unsigned char *swizzle_view,
844 uint32_t *word4_p, uint32_t *yuv_format_p,
845 bool do_endian_swap);
846 uint32_t r600_translate_colorformat(enum amd_gfx_level chip, enum pipe_format format,
847 bool do_endian_swap);
848 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
849
850 /* r600_uvd.c */
851 struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
852 const struct pipe_video_codec *decoder);
853
854 struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe,
855 const struct pipe_video_buffer *tmpl);
856
857 /*
858 * Helpers for building command buffers
859 */
860
861 #define PKT3_SET_CONFIG_REG 0x68
862 #define PKT3_SET_CONTEXT_REG 0x69
863 #define PKT3_SET_CTL_CONST 0x6F
864 #define PKT3_SET_LOOP_CONST 0x6C
865
866 #define R600_CONFIG_REG_OFFSET 0x08000
867 #define R600_CONTEXT_REG_OFFSET 0x28000
868 #define R600_CTL_CONST_OFFSET 0x3CFF0
869 #define R600_LOOP_CONST_OFFSET 0X0003E200
870 #define EG_LOOP_CONST_OFFSET 0x0003A200
871
872 #define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30)
873 #define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16)
874 #define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8)
875 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
876 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
877
878 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
879
880 /*Evergreen Compute packet3*/
881 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
882
r600_store_value(struct r600_command_buffer * cb,unsigned value)883 static inline void r600_store_value(struct r600_command_buffer *cb, unsigned value)
884 {
885 cb->buf[cb->num_dw++] = value;
886 }
887
r600_store_array(struct r600_command_buffer * cb,unsigned num,unsigned * ptr)888 static inline void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr)
889 {
890 assert(cb->num_dw+num <= cb->max_num_dw);
891 memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0]));
892 cb->num_dw += num;
893 }
894
r600_store_config_reg_seq(struct r600_command_buffer * cb,unsigned reg,unsigned num)895 static inline void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
896 {
897 assert(reg < R600_CONTEXT_REG_OFFSET);
898 assert(cb->num_dw+2+num <= cb->max_num_dw);
899 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
900 cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
901 }
902
903 /**
904 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
905 * shaders.
906 */
r600_store_context_reg_seq(struct r600_command_buffer * cb,unsigned reg,unsigned num)907 static inline void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
908 {
909 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
910 assert(cb->num_dw+2+num <= cb->max_num_dw);
911 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
912 cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
913 }
914
915 /**
916 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
917 * shaders.
918 */
r600_store_ctl_const_seq(struct r600_command_buffer * cb,unsigned reg,unsigned num)919 static inline void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
920 {
921 assert(reg >= R600_CTL_CONST_OFFSET);
922 assert(cb->num_dw+2+num <= cb->max_num_dw);
923 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
924 cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
925 }
926
r600_store_loop_const_seq(struct r600_command_buffer * cb,unsigned reg,unsigned num)927 static inline void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
928 {
929 assert(reg >= R600_LOOP_CONST_OFFSET);
930 assert(cb->num_dw+2+num <= cb->max_num_dw);
931 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
932 cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
933 }
934
935 /**
936 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
937 * shaders.
938 */
eg_store_loop_const_seq(struct r600_command_buffer * cb,unsigned reg,unsigned num)939 static inline void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
940 {
941 assert(reg >= EG_LOOP_CONST_OFFSET);
942 assert(cb->num_dw+2+num <= cb->max_num_dw);
943 cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
944 cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
945 }
946
r600_store_config_reg(struct r600_command_buffer * cb,unsigned reg,unsigned value)947 static inline void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
948 {
949 r600_store_config_reg_seq(cb, reg, 1);
950 r600_store_value(cb, value);
951 }
952
r600_store_context_reg(struct r600_command_buffer * cb,unsigned reg,unsigned value)953 static inline void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
954 {
955 r600_store_context_reg_seq(cb, reg, 1);
956 r600_store_value(cb, value);
957 }
958
r600_store_ctl_const(struct r600_command_buffer * cb,unsigned reg,unsigned value)959 static inline void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
960 {
961 r600_store_ctl_const_seq(cb, reg, 1);
962 r600_store_value(cb, value);
963 }
964
r600_store_loop_const(struct r600_command_buffer * cb,unsigned reg,unsigned value)965 static inline void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
966 {
967 r600_store_loop_const_seq(cb, reg, 1);
968 r600_store_value(cb, value);
969 }
970
eg_store_loop_const(struct r600_command_buffer * cb,unsigned reg,unsigned value)971 static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
972 {
973 eg_store_loop_const_seq(cb, reg, 1);
974 r600_store_value(cb, value);
975 }
976
977 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw);
978 void r600_release_command_buffer(struct r600_command_buffer *cb);
979
radeon_compute_set_context_reg_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num)980 static inline void radeon_compute_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
981 {
982 radeon_set_context_reg_seq(cs, reg, num);
983 /* Set the compute bit on the packet header */
984 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
985 }
986
radeon_set_ctl_const_seq(struct radeon_cmdbuf * cs,unsigned reg,unsigned num)987 static inline void radeon_set_ctl_const_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
988 {
989 assert(reg >= R600_CTL_CONST_OFFSET);
990 assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
991 radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0));
992 radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2);
993 }
994
radeon_compute_set_context_reg(struct radeon_cmdbuf * cs,unsigned reg,unsigned value)995 static inline void radeon_compute_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
996 {
997 radeon_compute_set_context_reg_seq(cs, reg, 1);
998 radeon_emit(cs, value);
999 }
1000
radeon_set_context_reg_flag(struct radeon_cmdbuf * cs,unsigned reg,unsigned value,unsigned flag)1001 static inline void radeon_set_context_reg_flag(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned flag)
1002 {
1003 if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) {
1004 radeon_compute_set_context_reg(cs, reg, value);
1005 } else {
1006 radeon_set_context_reg(cs, reg, value);
1007 }
1008 }
1009
radeon_set_ctl_const(struct radeon_cmdbuf * cs,unsigned reg,unsigned value)1010 static inline void radeon_set_ctl_const(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
1011 {
1012 radeon_set_ctl_const_seq(cs, reg, 1);
1013 radeon_emit(cs, value);
1014 }
1015
1016 /*
1017 * common helpers
1018 */
1019
1020 /* 12.4 fixed-point */
r600_pack_float_12p4(float x)1021 static inline unsigned r600_pack_float_12p4(float x)
1022 {
1023 return x <= 0 ? 0 :
1024 x >= 4096 ? 0xffff : x * 16;
1025 }
1026
r600_get_flush_flags(enum r600_coherency coher)1027 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
1028 {
1029 switch (coher) {
1030 default:
1031 case R600_COHERENCY_NONE:
1032 return 0;
1033 case R600_COHERENCY_SHADER:
1034 return R600_CONTEXT_INV_CONST_CACHE |
1035 R600_CONTEXT_INV_VERTEX_CACHE |
1036 R600_CONTEXT_INV_TEX_CACHE |
1037 R600_CONTEXT_STREAMOUT_FLUSH;
1038 case R600_COHERENCY_CB_META:
1039 return R600_CONTEXT_FLUSH_AND_INV_CB |
1040 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1041 }
1042 }
1043
1044 #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0
1045 #define V_028A6C_OUTPRIM_TYPE_LINESTRIP 1
1046 #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2
1047
1048 unsigned r600_conv_prim_to_gs_out(unsigned mode);
1049
1050 void eg_trace_emit(struct r600_context *rctx);
1051 void eg_dump_debug_state(struct pipe_context *ctx, FILE *f,
1052 unsigned flags);
1053
1054 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
1055 const void *tokens,
1056 enum pipe_shader_ir,
1057 unsigned pipe_shader_type);
1058 int r600_shader_select(struct pipe_context *ctx,
1059 struct r600_pipe_shader_selector* sel,
1060 bool *dirty, bool precompile);
1061
1062 void r600_delete_shader_selector(struct pipe_context *ctx,
1063 struct r600_pipe_shader_selector *sel);
1064
1065 struct r600_shader_atomic;
1066 void evergreen_emit_atomic_buffer_setup_count(struct r600_context *rctx,
1067 struct r600_pipe_shader *cs_shader,
1068 struct r600_shader_atomic *combined_atomics,
1069 uint8_t *atomic_used_mask_p);
1070 void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
1071 bool is_compute,
1072 struct r600_shader_atomic *combined_atomics,
1073 uint8_t atomic_used_mask);
1074 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
1075 bool is_compute,
1076 struct r600_shader_atomic *combined_atomics,
1077 uint8_t *atomic_used_mask_p);
1078 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only);
1079
1080 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type);
1081 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only);
1082 #endif
1083