1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "evergreen_compute.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/format/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/os_time.h"
36 #include "util/hex.h"
37 #include "vl/vl_decoder.h"
38 #include "vl/vl_video_buffer.h"
39 #include "radeon_video.h"
40 #include "git_sha1.h"
41
42 #include <inttypes.h>
43 #include <sys/utsname.h>
44 #include <stdlib.h>
45
46 #if LLVM_AVAILABLE
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 struct r600_multi_fence {
51 struct pipe_reference reference;
52 struct pipe_fence_handle *gfx;
53 struct pipe_fence_handle *sdma;
54
55 /* If the context wasn't flushed at fence creation, this is non-NULL. */
56 struct {
57 struct r600_common_context *ctx;
58 unsigned ib_index;
59 } gfx_unflushed;
60 };
61
62 /*
63 * pipe_context
64 */
65
66 /**
67 * Write an EOP event.
68 *
69 * \param event EVENT_TYPE_*
70 * \param event_flags Optional cache flush flags (TC)
71 * \param data_sel 1 = fence, 3 = timestamp
72 * \param buf Buffer
73 * \param va GPU address
74 * \param old_value Previous fence value (for a bug workaround)
75 * \param new_value Fence value to write for this event.
76 */
r600_gfx_write_event_eop(struct r600_common_context * ctx,unsigned event,unsigned event_flags,unsigned data_sel,struct r600_resource * buf,uint64_t va,uint32_t new_fence,unsigned query_type)77 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
78 unsigned event, unsigned event_flags,
79 unsigned data_sel,
80 struct r600_resource *buf, uint64_t va,
81 uint32_t new_fence, unsigned query_type)
82 {
83 struct radeon_cmdbuf *cs = &ctx->gfx.cs;
84 unsigned op = EVENT_TYPE(event) |
85 EVENT_INDEX(5) |
86 event_flags;
87 unsigned sel = EOP_DATA_SEL(data_sel);
88
89 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
90 radeon_emit(cs, op);
91 radeon_emit(cs, va);
92 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
93 radeon_emit(cs, new_fence); /* immediate data */
94 radeon_emit(cs, 0); /* unused */
95
96 if (buf)
97 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE |
98 RADEON_PRIO_QUERY);
99 }
100
r600_gfx_write_fence_dwords(struct r600_common_screen * screen)101 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
102 {
103 unsigned dwords = 6;
104
105 if (!screen->info.r600_has_virtual_memory)
106 dwords += 2;
107
108 return dwords;
109 }
110
r600_gfx_wait_fence(struct r600_common_context * ctx,struct r600_resource * buf,uint64_t va,uint32_t ref,uint32_t mask)111 void r600_gfx_wait_fence(struct r600_common_context *ctx,
112 struct r600_resource *buf,
113 uint64_t va, uint32_t ref, uint32_t mask)
114 {
115 struct radeon_cmdbuf *cs = &ctx->gfx.cs;
116
117 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
118 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
119 radeon_emit(cs, va);
120 radeon_emit(cs, va >> 32);
121 radeon_emit(cs, ref); /* reference value */
122 radeon_emit(cs, mask); /* mask */
123 radeon_emit(cs, 4); /* poll interval */
124
125 if (buf)
126 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ |
127 RADEON_PRIO_QUERY);
128 }
129
r600_draw_rectangle(struct blitter_context * blitter,void * vertex_elements_cso,blitter_get_vs_func get_vs,int x1,int y1,int x2,int y2,float depth,unsigned num_instances,enum blitter_attrib_type type,const union blitter_attrib * attrib)130 void r600_draw_rectangle(struct blitter_context *blitter,
131 void *vertex_elements_cso,
132 blitter_get_vs_func get_vs,
133 int x1, int y1, int x2, int y2,
134 float depth, unsigned num_instances,
135 enum blitter_attrib_type type,
136 const union blitter_attrib *attrib)
137 {
138 struct r600_common_context *rctx =
139 (struct r600_common_context*)util_blitter_get_pipe(blitter);
140 struct pipe_viewport_state viewport;
141 struct pipe_resource *buf = NULL;
142 unsigned offset = 0;
143 float *vb;
144
145 rctx->b.bind_vertex_elements_state(&rctx->b, vertex_elements_cso);
146 rctx->b.bind_vs_state(&rctx->b, get_vs(blitter));
147
148 /* Some operations (like color resolve on r6xx) don't work
149 * with the conventional primitive types.
150 * One that works is PT_RECTLIST, which we use here. */
151
152 /* setup viewport */
153 viewport.scale[0] = 1.0f;
154 viewport.scale[1] = 1.0f;
155 viewport.scale[2] = 1.0f;
156 viewport.translate[0] = 0.0f;
157 viewport.translate[1] = 0.0f;
158 viewport.translate[2] = 0.0f;
159 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
160
161 /* Upload vertices. The hw rectangle has only 3 vertices,
162 * The 4th one is derived from the first 3.
163 * The vertex specification should match u_blitter's vertex element state. */
164 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
165 rctx->screen->info.tcc_cache_line_size,
166 &offset, &buf, (void**)&vb);
167 if (!buf)
168 return;
169
170 vb[0] = x1;
171 vb[1] = y1;
172 vb[2] = depth;
173 vb[3] = 1;
174
175 vb[8] = x1;
176 vb[9] = y2;
177 vb[10] = depth;
178 vb[11] = 1;
179
180 vb[16] = x2;
181 vb[17] = y1;
182 vb[18] = depth;
183 vb[19] = 1;
184
185 switch (type) {
186 case UTIL_BLITTER_ATTRIB_COLOR:
187 memcpy(vb+4, attrib->color, sizeof(float)*4);
188 memcpy(vb+12, attrib->color, sizeof(float)*4);
189 memcpy(vb+20, attrib->color, sizeof(float)*4);
190 break;
191 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
192 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
193 vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
194 vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
195 /* fall through */
196 vb[4] = attrib->texcoord.x1;
197 vb[5] = attrib->texcoord.y1;
198 vb[12] = attrib->texcoord.x1;
199 vb[13] = attrib->texcoord.y2;
200 vb[20] = attrib->texcoord.x2;
201 vb[21] = attrib->texcoord.y1;
202 break;
203 default:; /* Nothing to do. */
204 }
205
206 /* draw */
207 struct pipe_vertex_buffer vbuffer = {};
208 vbuffer.buffer.resource = buf;
209 vbuffer.buffer_offset = offset;
210
211 util_set_vertex_buffers(&rctx->b, 1, false, &vbuffer);
212 util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
213 0, num_instances);
214 pipe_resource_reference(&buf, NULL);
215 }
216
r600_dma_emit_wait_idle(struct r600_common_context * rctx)217 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
218 {
219 struct radeon_cmdbuf *cs = &rctx->dma.cs;
220
221 if (rctx->gfx_level >= EVERGREEN)
222 radeon_emit(cs, 0xf0000000); /* NOP */
223 else {
224 /* TODO: R600-R700 should use the FENCE packet.
225 * CS checker support is required. */
226 }
227 }
228
r600_need_dma_space(struct r600_common_context * ctx,unsigned num_dw,struct r600_resource * dst,struct r600_resource * src)229 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
230 struct r600_resource *dst, struct r600_resource *src)
231 {
232 uint64_t vram = (uint64_t)ctx->dma.cs.used_vram_kb * 1024;
233 uint64_t gtt = (uint64_t)ctx->dma.cs.used_gart_kb * 1024;
234
235 if (dst) {
236 vram += dst->vram_usage;
237 gtt += dst->gart_usage;
238 }
239 if (src) {
240 vram += src->vram_usage;
241 gtt += src->gart_usage;
242 }
243
244 /* Flush the GFX IB if DMA depends on it. */
245 if (radeon_emitted(&ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
246 ((dst &&
247 ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs, dst->buf,
248 RADEON_USAGE_READWRITE)) ||
249 (src &&
250 ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs, src->buf,
251 RADEON_USAGE_WRITE))))
252 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
253
254 /* Flush if there's not enough space, or if the memory usage per IB
255 * is too large.
256 *
257 * IBs using too little memory are limited by the IB submission overhead.
258 * IBs using too much memory are limited by the kernel/TTM overhead.
259 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
260 *
261 * This heuristic makes sure that DMA requests are executed
262 * very soon after the call is made and lowers memory usage.
263 * It improves texture upload performance by keeping the DMA
264 * engine busy while uploads are being submitted.
265 */
266 num_dw++; /* for emit_wait_idle below */
267 if (!ctx->ws->cs_check_space(&ctx->dma.cs, num_dw) ||
268 ctx->dma.cs.used_vram_kb + ctx->dma.cs.used_gart_kb > 64 * 1024 ||
269 !radeon_cs_memory_below_limit(ctx->screen, &ctx->dma.cs, vram, gtt)) {
270 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
271 assert((num_dw + ctx->dma.cs.current.cdw) <= ctx->dma.cs.current.max_dw);
272 }
273
274 /* Wait for idle if either buffer has been used in the IB before to
275 * prevent read-after-write hazards.
276 */
277 if ((dst &&
278 ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs, dst->buf,
279 RADEON_USAGE_READWRITE)) ||
280 (src &&
281 ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs, src->buf,
282 RADEON_USAGE_WRITE)))
283 r600_dma_emit_wait_idle(ctx);
284
285 /* If GPUVM is not supported, the CS checker needs 2 entries
286 * in the buffer list per packet, which has to be done manually.
287 */
288 if (ctx->screen->info.r600_has_virtual_memory) {
289 if (dst)
290 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
291 RADEON_USAGE_WRITE);
292 if (src)
293 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
294 RADEON_USAGE_READ);
295 }
296
297 /* this function is called before all DMA calls, so increment this. */
298 ctx->num_dma_calls++;
299 }
300
r600_preflush_suspend_features(struct r600_common_context * ctx)301 void r600_preflush_suspend_features(struct r600_common_context *ctx)
302 {
303 /* suspend queries */
304 if (!list_is_empty(&ctx->active_queries))
305 r600_suspend_queries(ctx);
306
307 ctx->streamout.suspended = false;
308 if (ctx->streamout.begin_emitted) {
309 r600_emit_streamout_end(ctx);
310 ctx->streamout.suspended = true;
311 }
312 }
313
r600_postflush_resume_features(struct r600_common_context * ctx)314 void r600_postflush_resume_features(struct r600_common_context *ctx)
315 {
316 if (ctx->streamout.suspended) {
317 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
318 r600_streamout_buffers_dirty(ctx);
319 }
320
321 /* resume queries */
322 if (!list_is_empty(&ctx->active_queries))
323 r600_resume_queries(ctx);
324 }
325
r600_fence_server_sync(struct pipe_context * ctx,struct pipe_fence_handle * fence)326 static void r600_fence_server_sync(struct pipe_context *ctx,
327 struct pipe_fence_handle *fence)
328 {
329 /* radeon synchronizes all rings by default and will not implement
330 * fence imports.
331 */
332 }
333
r600_flush_from_st(struct pipe_context * ctx,struct pipe_fence_handle ** fence,unsigned flags)334 static void r600_flush_from_st(struct pipe_context *ctx,
335 struct pipe_fence_handle **fence,
336 unsigned flags)
337 {
338 struct pipe_screen *screen = ctx->screen;
339 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
340 struct radeon_winsys *ws = rctx->ws;
341 struct pipe_fence_handle *gfx_fence = NULL;
342 struct pipe_fence_handle *sdma_fence = NULL;
343 bool deferred_fence = false;
344 unsigned rflags = PIPE_FLUSH_ASYNC;
345
346 if (flags & PIPE_FLUSH_END_OF_FRAME)
347 rflags |= PIPE_FLUSH_END_OF_FRAME;
348
349 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
350 if (rctx->dma.cs.priv)
351 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
352
353 if (!radeon_emitted(&rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
354 if (fence)
355 ws->fence_reference(ws, &gfx_fence, rctx->last_gfx_fence);
356 if (!(flags & PIPE_FLUSH_DEFERRED))
357 ws->cs_sync_flush(&rctx->gfx.cs);
358 } else {
359 /* Instead of flushing, create a deferred fence. Constraints:
360 * - the gallium frontend must allow a deferred flush.
361 * - the gallium frontend must request a fence.
362 * Thread safety in fence_finish must be ensured by the gallium frontend.
363 */
364 if (flags & PIPE_FLUSH_DEFERRED && fence) {
365 gfx_fence = rctx->ws->cs_get_next_fence(&rctx->gfx.cs);
366 deferred_fence = true;
367 } else {
368 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
369 }
370 }
371
372 /* Both engines can signal out of order, so we need to keep both fences. */
373 if (fence) {
374 struct r600_multi_fence *multi_fence =
375 CALLOC_STRUCT(r600_multi_fence);
376 if (!multi_fence) {
377 ws->fence_reference(ws, &sdma_fence, NULL);
378 ws->fence_reference(ws, &gfx_fence, NULL);
379 goto finish;
380 }
381
382 multi_fence->reference.count = 1;
383 /* If both fences are NULL, fence_finish will always return true. */
384 multi_fence->gfx = gfx_fence;
385 multi_fence->sdma = sdma_fence;
386
387 if (deferred_fence) {
388 multi_fence->gfx_unflushed.ctx = rctx;
389 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
390 }
391
392 screen->fence_reference(screen, fence, NULL);
393 *fence = (struct pipe_fence_handle*)multi_fence;
394 }
395 finish:
396 if (!(flags & PIPE_FLUSH_DEFERRED)) {
397 if (rctx->dma.cs.priv)
398 ws->cs_sync_flush(&rctx->dma.cs);
399 ws->cs_sync_flush(&rctx->gfx.cs);
400 }
401 }
402
r600_flush_dma_ring(void * ctx,unsigned flags,struct pipe_fence_handle ** fence)403 static void r600_flush_dma_ring(void *ctx, unsigned flags,
404 struct pipe_fence_handle **fence)
405 {
406 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
407 struct radeon_cmdbuf *cs = &rctx->dma.cs;
408 struct radeon_saved_cs saved;
409 bool check_vm =
410 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
411 rctx->check_vm_faults;
412
413 if (!radeon_emitted(cs, 0)) {
414 if (fence)
415 rctx->ws->fence_reference(rctx->ws, fence, rctx->last_sdma_fence);
416 return;
417 }
418
419 if (check_vm)
420 radeon_save_cs(rctx->ws, cs, &saved, true);
421
422 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
423 if (fence)
424 rctx->ws->fence_reference(rctx->ws, fence, rctx->last_sdma_fence);
425
426 if (check_vm) {
427 /* Use conservative timeout 800ms, after which we won't wait any
428 * longer and assume the GPU is hung.
429 */
430 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
431
432 rctx->check_vm_faults(rctx, &saved, AMD_IP_SDMA);
433 radeon_clear_saved_cs(&saved);
434 }
435 }
436
437 /**
438 * Store a linearized copy of all chunks of \p cs together with the buffer
439 * list in \p saved.
440 */
radeon_save_cs(struct radeon_winsys * ws,struct radeon_cmdbuf * cs,struct radeon_saved_cs * saved,bool get_buffer_list)441 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
442 struct radeon_saved_cs *saved, bool get_buffer_list)
443 {
444 uint32_t *buf;
445 unsigned i;
446
447 /* Save the IB chunks. */
448 saved->num_dw = cs->prev_dw + cs->current.cdw;
449 saved->ib = MALLOC(4 * saved->num_dw);
450 if (!saved->ib)
451 goto oom;
452
453 buf = saved->ib;
454 for (i = 0; i < cs->num_prev; ++i) {
455 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
456 buf += cs->prev[i].cdw;
457 }
458 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
459
460 if (!get_buffer_list)
461 return;
462
463 /* Save the buffer list. */
464 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
465 saved->bo_list = CALLOC(saved->bo_count,
466 sizeof(saved->bo_list[0]));
467 if (!saved->bo_list) {
468 FREE(saved->ib);
469 goto oom;
470 }
471 ws->cs_get_buffer_list(cs, saved->bo_list);
472
473 return;
474
475 oom:
476 fprintf(stderr, "%s: out of memory\n", __func__);
477 memset(saved, 0, sizeof(*saved));
478 }
479
radeon_clear_saved_cs(struct radeon_saved_cs * saved)480 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
481 {
482 FREE(saved->ib);
483 FREE(saved->bo_list);
484
485 memset(saved, 0, sizeof(*saved));
486 }
487
r600_get_reset_status(struct pipe_context * ctx)488 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
489 {
490 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
491
492 return rctx->ws->ctx_query_reset_status(rctx->ctx, false, NULL, NULL);
493 }
494
r600_set_debug_callback(struct pipe_context * ctx,const struct util_debug_callback * cb)495 static void r600_set_debug_callback(struct pipe_context *ctx,
496 const struct util_debug_callback *cb)
497 {
498 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
499
500 if (cb)
501 rctx->debug = *cb;
502 else
503 memset(&rctx->debug, 0, sizeof(rctx->debug));
504 }
505
r600_set_device_reset_callback(struct pipe_context * ctx,const struct pipe_device_reset_callback * cb)506 static void r600_set_device_reset_callback(struct pipe_context *ctx,
507 const struct pipe_device_reset_callback *cb)
508 {
509 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
510
511 if (cb)
512 rctx->device_reset_callback = *cb;
513 else
514 memset(&rctx->device_reset_callback, 0,
515 sizeof(rctx->device_reset_callback));
516 }
517
r600_check_device_reset(struct r600_common_context * rctx)518 bool r600_check_device_reset(struct r600_common_context *rctx)
519 {
520 enum pipe_reset_status status;
521
522 if (!rctx->device_reset_callback.reset)
523 return false;
524
525 if (!rctx->b.get_device_reset_status)
526 return false;
527
528 status = rctx->b.get_device_reset_status(&rctx->b);
529 if (status == PIPE_NO_RESET)
530 return false;
531
532 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
533 return true;
534 }
535
r600_dma_clear_buffer_fallback(struct pipe_context * ctx,struct pipe_resource * dst,uint64_t offset,uint64_t size,unsigned value)536 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
537 struct pipe_resource *dst,
538 uint64_t offset, uint64_t size,
539 unsigned value)
540 {
541 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
542
543 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
544 }
545
r600_resource_commit(struct pipe_context * pctx,struct pipe_resource * resource,unsigned level,struct pipe_box * box,bool commit)546 static bool r600_resource_commit(struct pipe_context *pctx,
547 struct pipe_resource *resource,
548 unsigned level, struct pipe_box *box,
549 bool commit)
550 {
551 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
552 struct r600_resource *res = r600_resource(resource);
553
554 /*
555 * Since buffer commitment changes cannot be pipelined, we need to
556 * (a) flush any pending commands that refer to the buffer we're about
557 * to change, and
558 * (b) wait for threaded submit to finish, including those that were
559 * triggered by some other, earlier operation.
560 */
561 if (radeon_emitted(&ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
562 ctx->ws->cs_is_buffer_referenced(&ctx->gfx.cs,
563 res->buf, RADEON_USAGE_READWRITE)) {
564 ctx->gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
565 }
566 if (radeon_emitted(&ctx->dma.cs, 0) &&
567 ctx->ws->cs_is_buffer_referenced(&ctx->dma.cs,
568 res->buf, RADEON_USAGE_READWRITE)) {
569 ctx->dma.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
570 }
571
572 ctx->ws->cs_sync_flush(&ctx->dma.cs);
573 ctx->ws->cs_sync_flush(&ctx->gfx.cs);
574
575 assert(resource->target == PIPE_BUFFER);
576
577 return ctx->ws->buffer_commit(ctx->ws, res->buf, box->x, box->width, commit);
578 }
579
r600_common_context_init(struct r600_common_context * rctx,struct r600_common_screen * rscreen,unsigned context_flags)580 bool r600_common_context_init(struct r600_common_context *rctx,
581 struct r600_common_screen *rscreen,
582 unsigned context_flags)
583 {
584 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
585 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
586
587 rctx->screen = rscreen;
588 rctx->ws = rscreen->ws;
589 rctx->family = rscreen->family;
590 rctx->gfx_level = rscreen->gfx_level;
591
592 rctx->b.clear_buffer = u_default_clear_buffer;
593 rctx->b.invalidate_resource = r600_invalidate_resource;
594 rctx->b.resource_commit = r600_resource_commit;
595 rctx->b.buffer_map = r600_buffer_transfer_map;
596 rctx->b.texture_map = r600_texture_transfer_map;
597 rctx->b.transfer_flush_region = r600_buffer_flush_region;
598 rctx->b.buffer_unmap = r600_buffer_transfer_unmap;
599 rctx->b.texture_unmap = r600_texture_transfer_unmap;
600 rctx->b.texture_subdata = u_default_texture_subdata;
601 rctx->b.flush = r600_flush_from_st;
602 rctx->b.set_debug_callback = r600_set_debug_callback;
603 rctx->b.fence_server_sync = r600_fence_server_sync;
604 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
605
606 /* evergreen_compute.c has a special codepath for global buffers.
607 * Everything else can use the direct path.
608 */
609 if ((rscreen->gfx_level == EVERGREEN || rscreen->gfx_level == CAYMAN) &&
610 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
611 rctx->b.buffer_subdata = u_default_buffer_subdata;
612 else
613 rctx->b.buffer_subdata = r600_buffer_subdata;
614
615 rctx->b.get_device_reset_status = r600_get_reset_status;
616 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
617
618 r600_init_context_texture_functions(rctx);
619 r600_init_viewport_functions(rctx);
620 r600_streamout_init(rctx);
621 r600_query_init(rctx);
622 cayman_init_msaa(&rctx->b);
623
624 u_suballocator_init(&rctx->allocator_zeroed_memory, &rctx->b, rscreen->info.gart_page_size,
625 0, PIPE_USAGE_DEFAULT, 0, true);
626
627 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
628 0, PIPE_USAGE_STREAM, 0);
629 if (!rctx->b.stream_uploader)
630 return false;
631
632 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
633 0, PIPE_USAGE_DEFAULT, 0);
634 if (!rctx->b.const_uploader)
635 return false;
636
637 rctx->ctx = rctx->ws->ctx_create(rctx->ws, RADEON_CTX_PRIORITY_MEDIUM, false);
638 if (!rctx->ctx)
639 return false;
640
641 if (rscreen->info.ip[AMD_IP_SDMA].num_queues && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
642 rctx->ws->cs_create(&rctx->dma.cs, rctx->ctx, AMD_IP_SDMA,
643 r600_flush_dma_ring, rctx);
644 rctx->dma.flush = r600_flush_dma_ring;
645 }
646
647 return true;
648 }
649
r600_common_context_cleanup(struct r600_common_context * rctx)650 void r600_common_context_cleanup(struct r600_common_context *rctx)
651 {
652 if (rctx->query_result_shader)
653 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
654
655 rctx->ws->cs_destroy(&rctx->gfx.cs);
656 rctx->ws->cs_destroy(&rctx->dma.cs);
657 if (rctx->ctx)
658 rctx->ws->ctx_destroy(rctx->ctx);
659
660 if (rctx->b.stream_uploader)
661 u_upload_destroy(rctx->b.stream_uploader);
662 if (rctx->b.const_uploader)
663 u_upload_destroy(rctx->b.const_uploader);
664
665 slab_destroy_child(&rctx->pool_transfers);
666 slab_destroy_child(&rctx->pool_transfers_unsync);
667
668 u_suballocator_destroy(&rctx->allocator_zeroed_memory);
669 rctx->ws->fence_reference(rctx->ws, &rctx->last_gfx_fence, NULL);
670 rctx->ws->fence_reference(rctx->ws, &rctx->last_sdma_fence, NULL);
671 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
672 }
673
674 /*
675 * pipe_screen
676 */
677
678 static const struct debug_named_value common_debug_options[] = {
679 /* logging */
680 { "tex", DBG_TEX, "Print texture info" },
681 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
682 { "compute", DBG_COMPUTE, "Print compute info" },
683 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
684 { "info", DBG_INFO, "Print driver information" },
685
686 /* shaders */
687 { "fs", DBG_FS, "Print fetch shaders" },
688 { "vs", DBG_VS, "Print vertex shaders" },
689 { "gs", DBG_GS, "Print geometry shaders" },
690 { "ps", DBG_PS, "Print pixel shaders" },
691 { "cs", DBG_CS, "Print compute shaders" },
692 { "tcs", DBG_TCS, "Print tessellation control shaders" },
693 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
694 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
695 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
696
697 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
698 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
699 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
700 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
701
702 /* features */
703 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
704 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
705 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
706 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
707 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
708 { "notiling", DBG_NO_TILING, "Disable tiling" },
709 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
710 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
711 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
712 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
713
714 DEBUG_NAMED_VALUE_END /* must be last */
715 };
716
r600_get_vendor(struct pipe_screen * pscreen)717 static const char* r600_get_vendor(struct pipe_screen* pscreen)
718 {
719 return "Mesa";
720 }
721
r600_get_device_vendor(struct pipe_screen * pscreen)722 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
723 {
724 return "AMD";
725 }
726
r600_get_family_name(const struct r600_common_screen * rscreen)727 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
728 {
729 switch (rscreen->info.family) {
730 case CHIP_R600: return "AMD R600";
731 case CHIP_RV610: return "AMD RV610";
732 case CHIP_RV630: return "AMD RV630";
733 case CHIP_RV670: return "AMD RV670";
734 case CHIP_RV620: return "AMD RV620";
735 case CHIP_RV635: return "AMD RV635";
736 case CHIP_RS780: return "AMD RS780";
737 case CHIP_RS880: return "AMD RS880";
738 case CHIP_RV770: return "AMD RV770";
739 case CHIP_RV730: return "AMD RV730";
740 case CHIP_RV710: return "AMD RV710";
741 case CHIP_RV740: return "AMD RV740";
742 case CHIP_CEDAR: return "AMD CEDAR";
743 case CHIP_REDWOOD: return "AMD REDWOOD";
744 case CHIP_JUNIPER: return "AMD JUNIPER";
745 case CHIP_CYPRESS: return "AMD CYPRESS";
746 case CHIP_HEMLOCK: return "AMD HEMLOCK";
747 case CHIP_PALM: return "AMD PALM";
748 case CHIP_SUMO: return "AMD SUMO";
749 case CHIP_SUMO2: return "AMD SUMO2";
750 case CHIP_BARTS: return "AMD BARTS";
751 case CHIP_TURKS: return "AMD TURKS";
752 case CHIP_CAICOS: return "AMD CAICOS";
753 case CHIP_CAYMAN: return "AMD CAYMAN";
754 case CHIP_ARUBA: return "AMD ARUBA";
755 default: return "AMD unknown";
756 }
757 }
758
r600_disk_cache_create(struct r600_common_screen * rscreen)759 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
760 {
761 /* Don't use the cache if shader dumping is enabled. */
762 if (rscreen->debug_flags & DBG_ALL_SHADERS)
763 return;
764
765 struct mesa_sha1 ctx;
766 unsigned char sha1[20];
767 char cache_id[20 * 2 + 1];
768
769 _mesa_sha1_init(&ctx);
770 if (!disk_cache_get_function_identifier(r600_disk_cache_create,
771 &ctx))
772 return;
773
774 _mesa_sha1_final(&ctx, sha1);
775 mesa_bytes_to_hex(cache_id, sha1, 20);
776
777 /* These flags affect shader compilation. */
778 rscreen->disk_shader_cache =
779 disk_cache_create(r600_get_family_name(rscreen),
780 cache_id, 0);
781 }
782
r600_get_disk_shader_cache(struct pipe_screen * pscreen)783 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
784 {
785 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
786 return rscreen->disk_shader_cache;
787 }
788
r600_get_name(struct pipe_screen * pscreen)789 static const char* r600_get_name(struct pipe_screen* pscreen)
790 {
791 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
792
793 return rscreen->renderer_string;
794 }
795
r600_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)796 static float r600_get_paramf(struct pipe_screen* pscreen,
797 enum pipe_capf param)
798 {
799 switch (param) {
800 case PIPE_CAPF_MIN_LINE_WIDTH:
801 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
802 case PIPE_CAPF_MIN_POINT_SIZE:
803 case PIPE_CAPF_MIN_POINT_SIZE_AA:
804 return 1;
805
806 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
807 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
808 return 0.1;
809
810 case PIPE_CAPF_MAX_LINE_WIDTH:
811 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
812 case PIPE_CAPF_MAX_POINT_SIZE:
813 case PIPE_CAPF_MAX_POINT_SIZE_AA:
814 return 8191.0f;
815 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
816 return 16.0f;
817 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
818 return 16.0f;
819 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
820 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
821 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
822 return 0.0f;
823 }
824 return 0.0f;
825 }
826
r600_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)827 static int r600_get_video_param(struct pipe_screen *screen,
828 enum pipe_video_profile profile,
829 enum pipe_video_entrypoint entrypoint,
830 enum pipe_video_cap param)
831 {
832 switch (param) {
833 case PIPE_VIDEO_CAP_SUPPORTED:
834 return vl_profile_supported(screen, profile, entrypoint);
835 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
836 return 1;
837 case PIPE_VIDEO_CAP_MAX_WIDTH:
838 case PIPE_VIDEO_CAP_MAX_HEIGHT:
839 return vl_video_buffer_max_size(screen);
840 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
841 return PIPE_FORMAT_NV12;
842 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
843 return false;
844 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
845 return false;
846 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
847 return true;
848 case PIPE_VIDEO_CAP_MAX_LEVEL:
849 return vl_level_supported(screen, profile);
850 default:
851 return 0;
852 }
853 }
854
r600_get_llvm_processor_name(enum radeon_family family)855 const char *r600_get_llvm_processor_name(enum radeon_family family)
856 {
857 switch (family) {
858 case CHIP_R600:
859 case CHIP_RV630:
860 case CHIP_RV635:
861 case CHIP_RV670:
862 return "r600";
863 case CHIP_RV610:
864 case CHIP_RV620:
865 case CHIP_RS780:
866 case CHIP_RS880:
867 return "rs880";
868 case CHIP_RV710:
869 return "rv710";
870 case CHIP_RV730:
871 return "rv730";
872 case CHIP_RV740:
873 case CHIP_RV770:
874 return "rv770";
875 case CHIP_PALM:
876 case CHIP_CEDAR:
877 return "cedar";
878 case CHIP_SUMO:
879 case CHIP_SUMO2:
880 return "sumo";
881 case CHIP_REDWOOD:
882 return "redwood";
883 case CHIP_JUNIPER:
884 return "juniper";
885 case CHIP_HEMLOCK:
886 case CHIP_CYPRESS:
887 return "cypress";
888 case CHIP_BARTS:
889 return "barts";
890 case CHIP_TURKS:
891 return "turks";
892 case CHIP_CAICOS:
893 return "caicos";
894 case CHIP_CAYMAN:
895 case CHIP_ARUBA:
896 return "cayman";
897
898 default:
899 return "";
900 }
901 }
902
get_max_threads_per_block(struct r600_common_screen * screen,enum pipe_shader_ir ir_type)903 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
904 enum pipe_shader_ir ir_type)
905 {
906 if (ir_type != PIPE_SHADER_IR_TGSI &&
907 ir_type != PIPE_SHADER_IR_NIR)
908 return 256;
909 if (screen->gfx_level >= EVERGREEN)
910 return 1024;
911 return 256;
912 }
913
r600_get_compute_param(struct pipe_screen * screen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)914 static int r600_get_compute_param(struct pipe_screen *screen,
915 enum pipe_shader_ir ir_type,
916 enum pipe_compute_cap param,
917 void *ret)
918 {
919 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
920
921 //TODO: select these params by asic
922 switch (param) {
923 case PIPE_COMPUTE_CAP_IR_TARGET: {
924 const char *gpu;
925 const char *triple = "r600--";
926 gpu = r600_get_llvm_processor_name(rscreen->family);
927 if (ret) {
928 sprintf(ret, "%s-%s", gpu, triple);
929 }
930 /* +2 for dash and terminating NIL byte */
931 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
932 }
933 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
934 if (ret) {
935 uint64_t *grid_dimension = ret;
936 grid_dimension[0] = 3;
937 }
938 return 1 * sizeof(uint64_t);
939
940 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
941 if (ret) {
942 uint64_t *grid_size = ret;
943 grid_size[0] = 65535;
944 grid_size[1] = 65535;
945 grid_size[2] = 65535;
946 }
947 return 3 * sizeof(uint64_t) ;
948
949 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
950 if (ret) {
951 uint64_t *block_size = ret;
952 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
953 block_size[0] = threads_per_block;
954 block_size[1] = threads_per_block;
955 block_size[2] = threads_per_block;
956 }
957 return 3 * sizeof(uint64_t);
958
959 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
960 if (ret) {
961 uint64_t *max_threads_per_block = ret;
962 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
963 }
964 return sizeof(uint64_t);
965 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
966 if (ret) {
967 uint32_t *address_bits = ret;
968 address_bits[0] = 32;
969 }
970 return 1 * sizeof(uint32_t);
971
972 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
973 if (ret) {
974 uint64_t *max_global_size = ret;
975 uint64_t max_mem_alloc_size;
976
977 r600_get_compute_param(screen, ir_type,
978 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
979 &max_mem_alloc_size);
980
981 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
982 * 1/4 of the MAX_GLOBAL_SIZE. Since the
983 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
984 * make sure we never report more than
985 * 4 * MAX_MEM_ALLOC_SIZE.
986 */
987 *max_global_size = MIN2(4 * max_mem_alloc_size,
988 rscreen->info.max_heap_size_kb * 1024ull);
989 }
990 return sizeof(uint64_t);
991
992 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
993 if (ret) {
994 uint64_t *max_local_size = ret;
995 /* Value reported by the closed source driver. */
996 *max_local_size = 32768;
997 }
998 return sizeof(uint64_t);
999
1000 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1001 if (ret) {
1002 uint64_t *max_input_size = ret;
1003 /* Value reported by the closed source driver. */
1004 *max_input_size = 1024;
1005 }
1006 return sizeof(uint64_t);
1007
1008 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1009 if (ret) {
1010 uint64_t *max_mem_alloc_size = ret;
1011
1012 *max_mem_alloc_size = (rscreen->info.max_heap_size_kb / 4) * 1024ull;
1013 }
1014 return sizeof(uint64_t);
1015
1016 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1017 if (ret) {
1018 uint32_t *max_clock_frequency = ret;
1019 *max_clock_frequency = rscreen->info.max_gpu_freq_mhz;
1020 }
1021 return sizeof(uint32_t);
1022
1023 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1024 if (ret) {
1025 uint32_t *max_compute_units = ret;
1026 *max_compute_units = rscreen->info.num_cu;
1027 }
1028 return sizeof(uint32_t);
1029
1030 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1031 if (ret) {
1032 uint32_t *images_supported = ret;
1033 *images_supported = 0;
1034 }
1035 return sizeof(uint32_t);
1036 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1037 break; /* unused */
1038 case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
1039 if (ret) {
1040 uint32_t *subgroup_size = ret;
1041 *subgroup_size = r600_wavefront_size(rscreen->family);
1042 }
1043 return sizeof(uint32_t);
1044 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1045 if (ret) {
1046 uint64_t *max_variable_threads_per_block = ret;
1047 *max_variable_threads_per_block = 0;
1048 }
1049 return sizeof(uint64_t);
1050 case PIPE_COMPUTE_CAP_MAX_SUBGROUPS:
1051 return 0;
1052 }
1053
1054 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1055 return 0;
1056 }
1057
r600_get_timestamp(struct pipe_screen * screen)1058 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1059 {
1060 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1061
1062 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1063 rscreen->info.clock_crystal_freq;
1064 }
1065
r600_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** dst,struct pipe_fence_handle * src)1066 static void r600_fence_reference(struct pipe_screen *screen,
1067 struct pipe_fence_handle **dst,
1068 struct pipe_fence_handle *src)
1069 {
1070 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1071 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1072 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1073
1074 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1075 ws->fence_reference(ws, &(*rdst)->gfx, NULL);
1076 ws->fence_reference(ws, &(*rdst)->sdma, NULL);
1077 FREE(*rdst);
1078 }
1079 *rdst = rsrc;
1080 }
1081
r600_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)1082 static bool r600_fence_finish(struct pipe_screen *screen,
1083 struct pipe_context *ctx,
1084 struct pipe_fence_handle *fence,
1085 uint64_t timeout)
1086 {
1087 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1088 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1089 struct r600_common_context *rctx;
1090 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1091
1092 ctx = threaded_context_unwrap_sync(ctx);
1093 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1094
1095 if (rfence->sdma) {
1096 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1097 return false;
1098
1099 /* Recompute the timeout after waiting. */
1100 if (timeout && timeout != OS_TIMEOUT_INFINITE) {
1101 int64_t time = os_time_get_nano();
1102 timeout = abs_timeout > time ? abs_timeout - time : 0;
1103 }
1104 }
1105
1106 if (!rfence->gfx)
1107 return true;
1108
1109 /* Flush the gfx IB if it hasn't been flushed yet. */
1110 if (rctx &&
1111 rfence->gfx_unflushed.ctx == rctx &&
1112 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1113 rctx->gfx.flush(rctx, timeout ? 0 : PIPE_FLUSH_ASYNC, NULL);
1114 rfence->gfx_unflushed.ctx = NULL;
1115
1116 if (!timeout)
1117 return false;
1118
1119 /* Recompute the timeout after all that. */
1120 if (timeout && timeout != OS_TIMEOUT_INFINITE) {
1121 int64_t time = os_time_get_nano();
1122 timeout = abs_timeout > time ? abs_timeout - time : 0;
1123 }
1124 }
1125
1126 return rws->fence_wait(rws, rfence->gfx, timeout);
1127 }
1128
r600_query_memory_info(struct pipe_screen * screen,struct pipe_memory_info * info)1129 static void r600_query_memory_info(struct pipe_screen *screen,
1130 struct pipe_memory_info *info)
1131 {
1132 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1133 struct radeon_winsys *ws = rscreen->ws;
1134 unsigned vram_usage, gtt_usage;
1135
1136 info->total_device_memory = rscreen->info.vram_size_kb;
1137 info->total_staging_memory = rscreen->info.gart_size_kb;
1138
1139 /* The real TTM memory usage is somewhat random, because:
1140 *
1141 * 1) TTM delays freeing memory, because it can only free it after
1142 * fences expire.
1143 *
1144 * 2) The memory usage can be really low if big VRAM evictions are
1145 * taking place, but the real usage is well above the size of VRAM.
1146 *
1147 * Instead, return statistics of this process.
1148 */
1149 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1150 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1151
1152 info->avail_device_memory =
1153 vram_usage <= info->total_device_memory ?
1154 info->total_device_memory - vram_usage : 0;
1155 info->avail_staging_memory =
1156 gtt_usage <= info->total_staging_memory ?
1157 info->total_staging_memory - gtt_usage : 0;
1158
1159 info->device_memory_evicted =
1160 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1161
1162 /* Just return the number of evicted 64KB pages. */
1163 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1164 }
1165
r600_resource_create_common(struct pipe_screen * screen,const struct pipe_resource * templ)1166 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1167 const struct pipe_resource *templ)
1168 {
1169 if (templ->target == PIPE_BUFFER) {
1170 return r600_buffer_create(screen, templ, 256);
1171 } else {
1172 return r600_texture_create(screen, templ);
1173 }
1174 }
1175
1176 static const void *
r600_get_compiler_options(struct pipe_screen * screen,enum pipe_shader_ir ir,enum pipe_shader_type shader)1177 r600_get_compiler_options(struct pipe_screen *screen,
1178 enum pipe_shader_ir ir,
1179 enum pipe_shader_type shader)
1180 {
1181 assert(ir == PIPE_SHADER_IR_NIR);
1182
1183 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1184
1185 if (shader != PIPE_SHADER_FRAGMENT)
1186 return &rscreen->nir_options;
1187 else
1188 return &rscreen->nir_options_fs;
1189 }
1190
1191 extern bool r600_lower_to_scalar_instr_filter(const nir_instr *instr, const void *);
1192
r600_resource_destroy(struct pipe_screen * screen,struct pipe_resource * res)1193 static void r600_resource_destroy(struct pipe_screen *screen,
1194 struct pipe_resource *res)
1195 {
1196 if (res->target == PIPE_BUFFER) {
1197 if (r600_resource(res)->compute_global_bo)
1198 r600_compute_global_buffer_destroy(screen, res);
1199 else
1200 r600_buffer_destroy(screen, res);
1201 } else {
1202 r600_texture_destroy(screen, res);
1203 }
1204 }
1205
r600_get_screen_fd(struct pipe_screen * screen)1206 static int r600_get_screen_fd(struct pipe_screen *screen)
1207 {
1208 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1209
1210 return ws->get_fd(ws);
1211 }
1212
r600_get_driver_uuid(UNUSED struct pipe_screen * screen,char * uuid)1213 static void r600_get_driver_uuid(UNUSED struct pipe_screen *screen, char *uuid)
1214 {
1215 const char *driver_id = PACKAGE_VERSION MESA_GIT_SHA1 "r600";
1216
1217 /* The driver UUID is used for determining sharability of images and
1218 * memory between two Vulkan instances in separate processes, but also
1219 * to determining memory objects and sharability between Vulkan and
1220 * OpenGL driver. People who want to share memory need to also check
1221 * the device UUID.
1222 */
1223 struct mesa_sha1 sha1_ctx;
1224 _mesa_sha1_init(&sha1_ctx);
1225
1226 _mesa_sha1_update(&sha1_ctx, driver_id, strlen(driver_id));
1227
1228 uint8_t sha1[SHA1_DIGEST_LENGTH];
1229 _mesa_sha1_final(&sha1_ctx, sha1);
1230
1231 assert(SHA1_DIGEST_LENGTH >= PIPE_UUID_SIZE);
1232 memcpy(uuid, sha1, PIPE_UUID_SIZE);
1233 }
1234
r600_get_device_uuid(struct pipe_screen * screen,char * uuid)1235 static void r600_get_device_uuid(struct pipe_screen *screen, char *uuid)
1236 {
1237 uint32_t *uint_uuid = (uint32_t *)uuid;
1238 struct r600_common_screen* rs = (struct r600_common_screen*)screen;
1239
1240 assert(PIPE_UUID_SIZE >= sizeof(uint32_t) * 4);
1241
1242 /* Copied from ac_device_info
1243 * Use the device info directly instead of using a sha1. GL/VK UUIDs
1244 * are 16 byte vs 20 byte for sha1, and the truncation that would be
1245 * required would get rid of part of the little entropy we have.
1246 */
1247 memset(uuid, 0, PIPE_UUID_SIZE);
1248 if (!rs->info.pci.valid)
1249 fprintf(stderr,
1250 "r600 device_uuid output is based on invalid pci bus info.\n");
1251 uint_uuid[0] = rs->info.pci.domain;
1252 uint_uuid[1] = rs->info.pci.bus;
1253 uint_uuid[2] = rs->info.pci.dev;
1254 uint_uuid[3] = rs->info.pci.func;
1255 }
1256
r600_common_screen_init(struct r600_common_screen * rscreen,struct radeon_winsys * ws)1257 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1258 struct radeon_winsys *ws)
1259 {
1260 char family_name[32] = {}, kernel_version[128] = {};
1261 struct utsname uname_data;
1262 const char *chip_name;
1263
1264 ws->query_info(ws, &rscreen->info);
1265 rscreen->ws = ws;
1266
1267 chip_name = r600_get_family_name(rscreen);
1268
1269 if (uname(&uname_data) == 0)
1270 snprintf(kernel_version, sizeof(kernel_version),
1271 " / %s", uname_data.release);
1272
1273 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1274 "%s (%sDRM %i.%i.%i%s"
1275 #if LLVM_AVAILABLE
1276 ", LLVM " MESA_LLVM_VERSION_STRING
1277 #endif
1278 ")",
1279 chip_name, family_name, rscreen->info.drm_major,
1280 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1281 kernel_version);
1282
1283 rscreen->b.get_name = r600_get_name;
1284 rscreen->b.get_vendor = r600_get_vendor;
1285 rscreen->b.get_device_vendor = r600_get_device_vendor;
1286 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1287 rscreen->b.get_compute_param = r600_get_compute_param;
1288 rscreen->b.get_screen_fd = r600_get_screen_fd;
1289 rscreen->b.get_paramf = r600_get_paramf;
1290 rscreen->b.get_timestamp = r600_get_timestamp;
1291 rscreen->b.get_compiler_options = r600_get_compiler_options;
1292 rscreen->b.fence_finish = r600_fence_finish;
1293 rscreen->b.fence_reference = r600_fence_reference;
1294 rscreen->b.resource_destroy = r600_resource_destroy;
1295 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1296 rscreen->b.query_memory_info = r600_query_memory_info;
1297 rscreen->b.get_device_uuid = r600_get_device_uuid;
1298 rscreen->b.get_driver_uuid = r600_get_driver_uuid;
1299
1300 if (rscreen->info.ip[AMD_IP_UVD].num_queues) {
1301 rscreen->b.get_video_param = rvid_get_video_param;
1302 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1303 } else {
1304 rscreen->b.get_video_param = r600_get_video_param;
1305 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1306 }
1307
1308 r600_init_screen_texture_functions(rscreen);
1309 r600_init_screen_query_functions(rscreen);
1310
1311 rscreen->family = rscreen->info.family;
1312 rscreen->gfx_level = rscreen->info.gfx_level;
1313 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1314
1315 r600_disk_cache_create(rscreen);
1316
1317 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1318
1319 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1320 if (rscreen->force_aniso >= 0) {
1321 printf("radeon: Forcing anisotropy filter to %ix\n",
1322 /* round down to a power of two */
1323 1 << util_logbase2(rscreen->force_aniso));
1324 }
1325
1326 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1327 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1328
1329 if (rscreen->debug_flags & DBG_INFO) {
1330 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1331 rscreen->info.pci.domain, rscreen->info.pci.bus,
1332 rscreen->info.pci.dev, rscreen->info.pci.func);
1333 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1334 printf("family = %i (%s)\n", rscreen->info.family,
1335 r600_get_family_name(rscreen));
1336 printf("gfx_level = %i\n", rscreen->info.gfx_level);
1337 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1338 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1339 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size_kb, 1024));
1340 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size_kb, 1024));
1341 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size_kb, 1024));
1342 printf("max_heap_size = %i MB\n",
1343 (int)DIV_ROUND_UP(rscreen->info.max_heap_size_kb, 1024));
1344 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1345 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1346 printf("r600_has_virtual_memory = %i\n", rscreen->info.r600_has_virtual_memory);
1347 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1348 printf("ip[AMD_IP_UVD] = %u\n", rscreen->info.ip[AMD_IP_UVD].num_queues);
1349 printf("ip[AMD_IP_SDMA] = %i\n", rscreen->info.ip[AMD_IP_SDMA].num_queues);
1350 printf("ip[AMD_IP_COMPUTE] = %u\n", rscreen->info.ip[AMD_IP_COMPUTE].num_queues);
1351 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1352 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1353 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1354 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1355 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1356 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1357 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1358 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1359 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1360 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1361
1362 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1363 printf("max_gpu_freq_mhz = %i\n", rscreen->info.max_gpu_freq_mhz);
1364 printf("num_cu = %i\n", rscreen->info.num_cu);
1365 printf("max_se = %i\n", rscreen->info.max_se);
1366 printf("max_sh_per_se = %i\n", rscreen->info.max_sa_per_se);
1367
1368 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1369 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1370 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1371 printf("num_render_backends = %i\n", rscreen->info.max_render_backends);
1372 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1373 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1374 printf("enabled_rb_mask = 0x%" PRIx64 "\n", rscreen->info.enabled_rb_mask);
1375 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1376 }
1377
1378 const struct nir_shader_compiler_options nir_options = {
1379 .fuse_ffma16 = true,
1380 .fuse_ffma32 = true,
1381 .fuse_ffma64 = true,
1382 .lower_flrp32 = true,
1383 .lower_flrp64 = true,
1384 .lower_fdiv = true,
1385 .lower_isign = true,
1386 .lower_fsign = true,
1387 .lower_fmod = true,
1388 .lower_uadd_carry = true,
1389 .lower_usub_borrow = true,
1390 .lower_bitfield_extract = true,
1391 .lower_bitfield_insert = true,
1392 .lower_extract_byte = true,
1393 .lower_extract_word = true,
1394 .lower_insert_byte = true,
1395 .lower_insert_word = true,
1396 .lower_ldexp = true,
1397 /* due to a bug in the shader compiler, some loops hang
1398 * if they are not unrolled, see:
1399 * https://bugs.freedesktop.org/show_bug.cgi?id=86720
1400 */
1401 .max_unroll_iterations = 255,
1402 .lower_interpolate_at = true,
1403 .vectorize_io = true,
1404 .has_umad24 = true,
1405 .has_umul24 = true,
1406 .has_fmulz = true,
1407 .use_interpolated_input_intrinsics = true,
1408 .has_fsub = true,
1409 .has_isub = true,
1410 .has_find_msb_rev = true,
1411 .lower_iabs = true,
1412 .lower_uadd_sat = true,
1413 .lower_usub_sat = true,
1414 .has_fused_comp_and_csel = true,
1415 .lower_ifind_msb = true,
1416 .lower_ufind_msb = true,
1417 .lower_to_scalar = true,
1418 .lower_to_scalar_filter = r600_lower_to_scalar_instr_filter,
1419 .linker_ignore_precision = true,
1420 .lower_fpow = true,
1421 .lower_int64_options = ~0,
1422 .lower_cs_local_index_to_id = true,
1423 .lower_uniforms_to_ubo = true,
1424 .lower_image_offset_to_range_base = 1,
1425 .vectorize_tess_levels = 1,
1426 };
1427
1428 rscreen->nir_options = nir_options;
1429
1430 if (rscreen->info.family < CHIP_CEDAR)
1431 rscreen->nir_options.force_indirect_unrolling_sampler = true;
1432
1433 if (rscreen->info.gfx_level >= EVERGREEN) {
1434 rscreen->nir_options.has_bfe = true;
1435 rscreen->nir_options.has_bfm = true;
1436 rscreen->nir_options.has_bitfield_select = true;
1437 }
1438
1439 if (rscreen->info.gfx_level < EVERGREEN) {
1440 /* Pre-EG doesn't have these ALU ops */
1441 rscreen->nir_options.lower_bit_count = true;
1442 rscreen->nir_options.lower_bitfield_reverse = true;
1443 }
1444
1445 if (rscreen->info.gfx_level < CAYMAN) {
1446 rscreen->nir_options.lower_doubles_options = nir_lower_fp64_full_software;
1447 rscreen->nir_options.lower_atomic_offset_to_range_base = true;
1448 } else {
1449 rscreen->nir_options.lower_doubles_options =
1450 nir_lower_ddiv |
1451 nir_lower_dfloor |
1452 nir_lower_dceil |
1453 nir_lower_dmod |
1454 nir_lower_dsub |
1455 nir_lower_dtrunc |
1456 nir_lower_dround_even;
1457 }
1458
1459 rscreen->nir_options_fs = rscreen->nir_options;
1460 rscreen->nir_options_fs.lower_all_io_to_temps = true;
1461
1462 return true;
1463 }
1464
r600_destroy_common_screen(struct r600_common_screen * rscreen)1465 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1466 {
1467 r600_perfcounters_destroy(rscreen);
1468 r600_gpu_load_kill_thread(rscreen);
1469
1470 mtx_destroy(&rscreen->gpu_load_mutex);
1471 mtx_destroy(&rscreen->aux_context_lock);
1472 rscreen->aux_context->destroy(rscreen->aux_context);
1473
1474 slab_destroy_parent(&rscreen->pool_transfers);
1475
1476 disk_cache_destroy(rscreen->disk_shader_cache);
1477 rscreen->ws->destroy(rscreen->ws);
1478 FREE(rscreen);
1479 }
1480
r600_can_dump_shader(struct r600_common_screen * rscreen,unsigned processor)1481 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1482 unsigned processor)
1483 {
1484 return rscreen->debug_flags & (1 << processor);
1485 }
1486
r600_extra_shader_checks(struct r600_common_screen * rscreen,unsigned processor)1487 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1488 {
1489 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1490 r600_can_dump_shader(rscreen, processor);
1491 }
1492
r600_screen_clear_buffer(struct r600_common_screen * rscreen,struct pipe_resource * dst,uint64_t offset,uint64_t size,unsigned value)1493 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1494 uint64_t offset, uint64_t size, unsigned value)
1495 {
1496 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1497
1498 mtx_lock(&rscreen->aux_context_lock);
1499 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1500 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1501 mtx_unlock(&rscreen->aux_context_lock);
1502 }
1503