1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 /**
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
30 */
31
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
34
35 #include <stdio.h>
36
37 #include "winsys/radeon_winsys.h"
38
39 #include "util/disk_cache.h"
40 #include "util/u_blitter.h"
41 #include "util/list.h"
42 #include "util/u_range.h"
43 #include "util/slab.h"
44 #include "util/u_suballoc.h"
45 #include "util/u_transfer.h"
46 #include "util/u_threaded_context.h"
47
48 #include "compiler/nir/nir.h"
49
50 struct u_log_context;
51 #define ATI_VENDOR_ID 0x1002
52
53 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
54 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
55 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
56 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
57
58 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
59 /* Pipeline & streamout query controls. */
60 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
61 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
62 #define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3)
63 #define R600_CONTEXT_PRIVATE_FLAG (1u << 4)
64
65 /* special primitive types */
66 #define R600_PRIM_RECTANGLE_LIST MESA_PRIM_COUNT
67
68 #define R600_NOT_QUERY 0xffffffff
69
70 /* Debug flags. */
71 #define DBG_VS (1 << PIPE_SHADER_VERTEX)
72 #define DBG_PS (1 << PIPE_SHADER_FRAGMENT)
73 #define DBG_GS (1 << PIPE_SHADER_GEOMETRY)
74 #define DBG_TCS (1 << PIPE_SHADER_TESS_CTRL)
75 #define DBG_TES (1 << PIPE_SHADER_TESS_EVAL)
76 #define DBG_CS (1 << PIPE_SHADER_COMPUTE)
77 #define DBG_ALL_SHADERS (DBG_FS - 1)
78 #define DBG_FS (1 << 6) /* fetch shader */
79 #define DBG_TEX (1 << 7)
80 #define DBG_NIR (1 << 8)
81 #define DBG_COMPUTE (1 << 9)
82 /* gap */
83 #define DBG_VM (1 << 11)
84 #define DBG_PREOPT_IR (1 << 15)
85 #define DBG_CHECK_IR (1 << 16)
86 /* gaps */
87 #define DBG_TEST_DMA (1 << 20)
88 /* Bits 21-31 are reserved for the r600g driver. */
89 /* features */
90 #define DBG_NO_ASYNC_DMA (1ull << 32)
91 #define DBG_NO_HYPERZ (1ull << 33)
92 #define DBG_NO_DISCARD_RANGE (1ull << 34)
93 #define DBG_NO_2D_TILING (1ull << 35)
94 #define DBG_NO_TILING (1ull << 36)
95 #define DBG_SWITCH_ON_EOP (1ull << 37)
96 #define DBG_FORCE_DMA (1ull << 38)
97 #define DBG_INFO (1ull << 40)
98 #define DBG_NO_WC (1ull << 41)
99 #define DBG_CHECK_VM (1ull << 42)
100 /* gap */
101 #define DBG_TEST_VMFAULT_CP (1ull << 51)
102 #define DBG_TEST_VMFAULT_SDMA (1ull << 52)
103 #define DBG_TEST_VMFAULT_SHADER (1ull << 53)
104
105 #define R600_MAP_BUFFER_ALIGNMENT 64
106 #define R600_MAX_VIEWPORTS 16
107
108 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
109
110 enum r600_coherency {
111 R600_COHERENCY_NONE, /* no cache flushes needed */
112 R600_COHERENCY_SHADER,
113 R600_COHERENCY_CB_META,
114 };
115
116 struct r600_common_context;
117 struct r600_perfcounters;
118 struct tgsi_shader_info;
119 struct r600_qbo_state;
120
121 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
122 * at the moment.
123 */
124 struct r600_resource {
125 struct threaded_resource b;
126
127 /* Winsys objects. */
128 struct pb_buffer_lean *buf;
129 uint64_t gpu_address;
130 /* Memory usage if the buffer placement is optimal. */
131 uint64_t vram_usage;
132 uint64_t gart_usage;
133
134 /* Resource properties. */
135 uint64_t bo_size;
136 unsigned bo_alignment;
137 enum radeon_bo_domain domains;
138 enum radeon_bo_flag flags;
139 unsigned bind_history;
140
141 /* The buffer range which is initialized (with a write transfer,
142 * streamout, DMA, or as a random access target). The rest of
143 * the buffer is considered invalid and can be mapped unsynchronized.
144 *
145 * This allows unsynchronized mapping of a buffer range which hasn't
146 * been used yet. It's for applications which forget to use
147 * the unsynchronized map flag and expect the driver to figure it out.
148 */
149 struct util_range valid_buffer_range;
150
151 /* Whether the resource has been exported via resource_get_handle. */
152 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
153
154 /* Whether this resource is referenced by bindless handles. */
155 bool texture_handle_allocated;
156 bool image_handle_allocated;
157 bool compute_global_bo;
158
159 /*
160 * EG/Cayman only - for RAT operations hw need an immediate buffer
161 * to store results in.
162 */
163 struct r600_resource *immed_buffer;
164 };
165
166 struct r600_transfer {
167 struct threaded_transfer b;
168 struct r600_resource *staging;
169 };
170
171 struct r600_fmask_info {
172 uint64_t offset;
173 uint64_t size;
174 unsigned alignment;
175 unsigned pitch_in_pixels;
176 unsigned bank_height;
177 unsigned slice_tile_max;
178 unsigned tile_mode_index;
179 unsigned tile_swizzle;
180 };
181
182 struct r600_cmask_info {
183 uint64_t offset;
184 uint64_t size;
185 unsigned alignment;
186 unsigned slice_tile_max;
187 uint64_t base_address_reg;
188 };
189
190 struct r600_texture {
191 struct r600_resource resource;
192
193 uint64_t size;
194 unsigned num_level0_transfers;
195 enum pipe_format db_render_format;
196 bool is_depth;
197 bool db_compatible;
198 bool can_sample_z;
199 bool can_sample_s;
200 unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */
201 unsigned stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
202 struct r600_texture *flushed_depth_texture;
203 struct radeon_surf surface;
204
205 /* Colorbuffer compression and fast clear. */
206 struct r600_fmask_info fmask;
207 struct r600_cmask_info cmask;
208 struct r600_resource *cmask_buffer;
209 unsigned cb_color_info; /* fast clear enable bit */
210 unsigned color_clear_value[2];
211 unsigned last_msaa_resolve_target_micro_mode;
212
213 /* Depth buffer compression and fast clear. */
214 uint64_t htile_offset;
215 bool depth_cleared; /* if it was cleared at least once */
216 float depth_clear_value;
217 bool stencil_cleared; /* if it was cleared at least once */
218 uint8_t stencil_clear_value;
219
220 bool non_disp_tiling; /* R600-Cayman only */
221
222 /* Counter that should be non-zero if the texture is bound to a
223 * framebuffer. Implemented in radeonsi only.
224 */
225 uint32_t framebuffers_bound;
226 };
227
228 struct r600_surface {
229 struct pipe_surface base;
230
231 /* These can vary with block-compressed textures. */
232 unsigned width0;
233 unsigned height0;
234
235 bool color_initialized;
236 bool depth_initialized;
237
238 /* Misc. color flags. */
239 bool alphatest_bypass;
240 bool export_16bpc;
241 bool color_is_int8;
242 bool color_is_int10;
243
244 /* Color registers. */
245 unsigned cb_color_info;
246 unsigned cb_color_base;
247 unsigned cb_color_view;
248 unsigned cb_color_size; /* R600 only */
249 unsigned cb_color_dim; /* EG only */
250 unsigned cb_color_pitch; /* EG and later */
251 unsigned cb_color_slice; /* EG and later */
252 unsigned cb_color_attrib; /* EG and later */
253 unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
254 unsigned cb_color_fmask_slice; /* EG and later */
255 unsigned cb_color_cmask; /* CB_COLORn_TILE (r600 only) */
256 unsigned cb_color_mask; /* R600 only */
257 struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
258 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
259
260 /* DB registers. */
261 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
262 uint64_t db_stencil_base; /* EG and later */
263 uint64_t db_htile_data_base;
264 unsigned db_depth_info; /* R600 only, then SI and later */
265 unsigned db_z_info; /* EG and later */
266 unsigned db_depth_view;
267 unsigned db_depth_size;
268 unsigned db_depth_slice; /* EG and later */
269 unsigned db_stencil_info; /* EG and later */
270 unsigned db_prefetch_limit; /* R600 only */
271 unsigned db_htile_surface;
272 unsigned db_preload_control; /* EG and later */
273 };
274
275 struct r600_mmio_counter {
276 unsigned busy;
277 unsigned idle;
278 };
279
280 union r600_mmio_counters {
281 struct r600_mmio_counters_named {
282 /* For global GPU load including SDMA. */
283 struct r600_mmio_counter gpu;
284
285 /* GRBM_STATUS */
286 struct r600_mmio_counter spi;
287 struct r600_mmio_counter gui;
288 struct r600_mmio_counter ta;
289 struct r600_mmio_counter gds;
290 struct r600_mmio_counter vgt;
291 struct r600_mmio_counter ia;
292 struct r600_mmio_counter sx;
293 struct r600_mmio_counter wd;
294 struct r600_mmio_counter bci;
295 struct r600_mmio_counter sc;
296 struct r600_mmio_counter pa;
297 struct r600_mmio_counter db;
298 struct r600_mmio_counter cp;
299 struct r600_mmio_counter cb;
300
301 /* SRBM_STATUS2 */
302 struct r600_mmio_counter sdma;
303
304 /* CP_STAT */
305 struct r600_mmio_counter pfp;
306 struct r600_mmio_counter meq;
307 struct r600_mmio_counter me;
308 struct r600_mmio_counter surf_sync;
309 struct r600_mmio_counter cp_dma;
310 struct r600_mmio_counter scratch_ram;
311 } named;
312 unsigned array[sizeof(struct r600_mmio_counters_named) / sizeof(unsigned)];
313 };
314
315 struct r600_memory_object {
316 struct pipe_memory_object b;
317 struct pb_buffer_lean *buf;
318 uint32_t stride;
319 uint32_t offset;
320 };
321
322 struct r600_common_screen {
323 struct pipe_screen b;
324 struct radeon_winsys *ws;
325 enum radeon_family family;
326 enum amd_gfx_level gfx_level;
327 struct radeon_info info;
328 uint64_t debug_flags;
329 bool has_cp_dma;
330 bool has_streamout;
331
332 struct disk_cache *disk_shader_cache;
333
334 struct slab_parent_pool pool_transfers;
335
336 /* Texture filter settings. */
337 int force_aniso; /* -1 = disabled */
338
339 /* Auxiliary context. Mainly used to initialize resources.
340 * It must be locked prior to using and flushed before unlocking. */
341 struct pipe_context *aux_context;
342 mtx_t aux_context_lock;
343
344 /* This must be in the screen, because UE4 uses one context for
345 * compilation and another one for rendering.
346 */
347 unsigned num_compilations;
348 /* Along with ST_DEBUG=precompile, this should show if applications
349 * are loading shaders on demand. This is a monotonic counter.
350 */
351 unsigned num_shaders_created;
352 unsigned num_shader_cache_hits;
353
354 /* GPU load thread. */
355 mtx_t gpu_load_mutex;
356 thrd_t gpu_load_thread;
357 bool gpu_load_thread_created;
358 union r600_mmio_counters mmio_counters;
359 volatile unsigned gpu_load_stop_thread; /* bool */
360
361 char renderer_string[100];
362
363 /* Performance counters. */
364 struct r600_perfcounters *perfcounters;
365
366 /* If pipe_screen wants to recompute and re-emit the framebuffer,
367 * sampler, and image states of all contexts, it should atomically
368 * increment this.
369 *
370 * Each context will compare this with its own last known value of
371 * the counter before drawing and re-emit the states accordingly.
372 */
373 unsigned dirty_tex_counter;
374
375 /* Atomically increment this counter when an existing texture's
376 * metadata is enabled or disabled in a way that requires changing
377 * contexts' compressed texture binding masks.
378 */
379 unsigned compressed_colortex_counter;
380
381 struct {
382 /* Context flags to set so that all writes from earlier jobs
383 * in the CP are seen by L2 clients.
384 */
385 unsigned cp_to_L2;
386
387 /* Context flags to set so that all writes from earlier jobs
388 * that end in L2 are seen by CP.
389 */
390 unsigned L2_to_cp;
391
392 /* Context flags to set so that all writes from earlier
393 * compute jobs are seen by L2 clients.
394 */
395 unsigned compute_to_L2;
396 } barrier_flags;
397
398 struct nir_shader_compiler_options nir_options;
399 struct nir_shader_compiler_options nir_options_fs;
400 };
401
402 /* This encapsulates a state or an operation which can emitted into the GPU
403 * command stream. */
404 struct r600_atom {
405 void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
406 unsigned num_dw;
407 unsigned short id;
408 };
409
410 struct r600_so_target {
411 struct pipe_stream_output_target b;
412
413 /* The buffer where BUFFER_FILLED_SIZE is stored. */
414 struct r600_resource *buf_filled_size;
415 unsigned buf_filled_size_offset;
416 bool buf_filled_size_valid;
417
418 unsigned stride_in_dw;
419 };
420
421 struct r600_streamout {
422 struct r600_atom begin_atom;
423 bool begin_emitted;
424 unsigned num_dw_for_end;
425
426 unsigned enabled_mask;
427 unsigned num_targets;
428 struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
429
430 unsigned append_bitmask;
431 bool suspended;
432
433 /* External state which comes from the vertex shader,
434 * it must be set explicitly when binding a shader. */
435 uint16_t *stride_in_dw;
436 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
437
438 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
439 unsigned hw_enabled_mask;
440
441 /* The state of VGT_STRMOUT_(CONFIG|EN). */
442 struct r600_atom enable_atom;
443 bool streamout_enabled;
444 bool prims_gen_query_enabled;
445 int num_prims_gen_queries;
446 };
447
448 struct r600_signed_scissor {
449 int minx;
450 int miny;
451 int maxx;
452 int maxy;
453 };
454
455 struct r600_scissors {
456 struct r600_atom atom;
457 unsigned dirty_mask;
458 struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
459 };
460
461 struct r600_viewports {
462 struct r600_atom atom;
463 unsigned dirty_mask;
464 unsigned depth_range_dirty_mask;
465 struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
466 struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
467 };
468
469 struct r600_ring {
470 struct radeon_cmdbuf cs;
471 void (*flush)(void *ctx, unsigned flags,
472 struct pipe_fence_handle **fence);
473 };
474
475 /* Saved CS data for debugging features. */
476 struct radeon_saved_cs {
477 uint32_t *ib;
478 unsigned num_dw;
479
480 struct radeon_bo_list_item *bo_list;
481 unsigned bo_count;
482 };
483
484 struct r600_common_context {
485 struct pipe_context b; /* base class */
486
487 struct r600_common_screen *screen;
488 struct radeon_winsys *ws;
489 struct radeon_winsys_ctx *ctx;
490 enum radeon_family family;
491 enum amd_gfx_level gfx_level;
492 struct r600_ring gfx;
493 struct r600_ring dma;
494 struct pipe_fence_handle *last_gfx_fence;
495 struct pipe_fence_handle *last_sdma_fence;
496 struct r600_resource *eop_bug_scratch;
497 unsigned num_gfx_cs_flushes;
498 unsigned initial_gfx_cs_size;
499 unsigned last_dirty_tex_counter;
500 unsigned last_compressed_colortex_counter;
501 unsigned last_num_draw_calls;
502
503 struct threaded_context *tc;
504 struct u_suballocator allocator_zeroed_memory;
505 struct slab_child_pool pool_transfers;
506 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
507
508 /* Current unaccounted memory usage. */
509 uint64_t vram;
510 uint64_t gtt;
511
512 /* States. */
513 struct r600_streamout streamout;
514 struct r600_scissors scissors;
515 struct r600_viewports viewports;
516 bool scissor_enabled;
517 bool clip_halfz;
518 bool vs_writes_viewport_index;
519 bool vs_disables_clipping_viewport;
520
521 /* Additional context states. */
522 unsigned flags; /* flush flags */
523
524 /* Queries. */
525 /* Maintain the list of active queries for pausing between IBs. */
526 int num_occlusion_queries;
527 int num_perfect_occlusion_queries;
528 struct list_head active_queries;
529 unsigned num_cs_dw_queries_suspend;
530 /* Misc stats. */
531 unsigned num_draw_calls;
532 unsigned num_decompress_calls;
533 unsigned num_mrt_draw_calls;
534 unsigned num_prim_restart_calls;
535 unsigned num_spill_draw_calls;
536 unsigned num_compute_calls;
537 unsigned num_spill_compute_calls;
538 unsigned num_dma_calls;
539 unsigned num_cp_dma_calls;
540 unsigned num_vs_flushes;
541 unsigned num_ps_flushes;
542 unsigned num_cs_flushes;
543 unsigned num_cb_cache_flushes;
544 unsigned num_db_cache_flushes;
545 unsigned num_resident_handles;
546 uint64_t num_alloc_tex_transfer_bytes;
547
548 /* Render condition. */
549 struct r600_atom render_cond_atom;
550 struct pipe_query *render_cond;
551 unsigned render_cond_mode;
552 bool render_cond_invert;
553 bool render_cond_force_off; /* for u_blitter */
554
555 /* MSAA sample locations.
556 * The first index is the sample index.
557 * The second index is the coordinate: X, Y. */
558 float sample_locations_1x[1][2];
559 float sample_locations_2x[2][2];
560 float sample_locations_4x[4][2];
561 float sample_locations_8x[8][2];
562 float sample_locations_16x[16][2];
563
564 struct util_debug_callback debug;
565 struct pipe_device_reset_callback device_reset_callback;
566 struct u_log_context *log;
567
568 void *query_result_shader;
569
570 /* Copy one resource to another using async DMA. */
571 void (*dma_copy)(struct pipe_context *ctx,
572 struct pipe_resource *dst,
573 unsigned dst_level,
574 unsigned dst_x, unsigned dst_y, unsigned dst_z,
575 struct pipe_resource *src,
576 unsigned src_level,
577 const struct pipe_box *src_box);
578
579 void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
580 uint64_t offset, uint64_t size, unsigned value);
581
582 void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
583 uint64_t offset, uint64_t size, unsigned value,
584 enum r600_coherency coher);
585
586 void (*blit_decompress_depth)(struct pipe_context *ctx,
587 struct r600_texture *texture,
588 struct r600_texture *staging,
589 unsigned first_level, unsigned last_level,
590 unsigned first_layer, unsigned last_layer,
591 unsigned first_sample, unsigned last_sample);
592
593 /* Reallocate the buffer and update all resource bindings where
594 * the buffer is bound, including all resource descriptors. */
595 void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
596
597 /* Update all resource bindings where the buffer is bound, including
598 * all resource descriptors. This is invalidate_buffer without
599 * the invalidation. */
600 void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
601 uint64_t old_gpu_address);
602
603 void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
604
605 /* This ensures there is enough space in the command stream. */
606 void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
607 bool include_draw_vbo);
608
609 void (*set_atom_dirty)(struct r600_common_context *ctx,
610 struct r600_atom *atom, bool dirty);
611
612 void (*check_vm_faults)(struct r600_common_context *ctx,
613 struct radeon_saved_cs *saved,
614 enum amd_ip_type ring);
615 };
616
617 /* r600_buffer_common.c */
618 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
619 struct pb_buffer_lean *buf,
620 unsigned usage);
621 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
622 struct r600_resource *resource,
623 unsigned usage);
624 void r600_buffer_subdata(struct pipe_context *ctx,
625 struct pipe_resource *buffer,
626 unsigned usage, unsigned offset,
627 unsigned size, const void *data);
628 void r600_init_resource_fields(struct r600_common_screen *rscreen,
629 struct r600_resource *res,
630 uint64_t size, unsigned alignment);
631 bool r600_alloc_resource(struct r600_common_screen *rscreen,
632 struct r600_resource *res);
633 void r600_buffer_destroy(struct pipe_screen *screen, struct pipe_resource *buf);
634 void r600_buffer_flush_region(struct pipe_context *ctx,
635 struct pipe_transfer *transfer,
636 const struct pipe_box *rel_box);
637 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
638 const struct pipe_resource *templ,
639 unsigned alignment);
640 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
641 unsigned flags,
642 unsigned usage,
643 unsigned size,
644 unsigned alignment);
645 struct pipe_resource *
646 r600_buffer_from_user_memory(struct pipe_screen *screen,
647 const struct pipe_resource *templ,
648 void *user_memory);
649 void
650 r600_invalidate_resource(struct pipe_context *ctx,
651 struct pipe_resource *resource);
652 void r600_replace_buffer_storage(struct pipe_context *ctx,
653 struct pipe_resource *dst,
654 struct pipe_resource *src);
655 void *r600_buffer_transfer_map(struct pipe_context *ctx,
656 struct pipe_resource *resource,
657 unsigned level,
658 unsigned usage,
659 const struct pipe_box *box,
660 struct pipe_transfer **ptransfer);
661 void r600_buffer_transfer_unmap(struct pipe_context *ctx,
662 struct pipe_transfer *transfer);
663
664 /* r600_common_pipe.c */
665 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
666 unsigned event, unsigned event_flags,
667 unsigned data_sel,
668 struct r600_resource *buf, uint64_t va,
669 uint32_t new_fence, unsigned query_type);
670 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
671 void r600_gfx_wait_fence(struct r600_common_context *ctx,
672 struct r600_resource *buf,
673 uint64_t va, uint32_t ref, uint32_t mask);
674 void r600_draw_rectangle(struct blitter_context *blitter,
675 void *vertex_elements_cso,
676 blitter_get_vs_func get_vs,
677 int x1, int y1, int x2, int y2,
678 float depth, unsigned num_instances,
679 enum blitter_attrib_type type,
680 const union blitter_attrib *attrib);
681 bool r600_common_screen_init(struct r600_common_screen *rscreen,
682 struct radeon_winsys *ws);
683 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
684 void r600_preflush_suspend_features(struct r600_common_context *ctx);
685 void r600_postflush_resume_features(struct r600_common_context *ctx);
686 bool r600_common_context_init(struct r600_common_context *rctx,
687 struct r600_common_screen *rscreen,
688 unsigned context_flags);
689 void r600_common_context_cleanup(struct r600_common_context *rctx);
690 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
691 unsigned processor);
692 bool r600_extra_shader_checks(struct r600_common_screen *rscreen,
693 unsigned processor);
694 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
695 uint64_t offset, uint64_t size, unsigned value);
696 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
697 const struct pipe_resource *templ);
698 const char *r600_get_llvm_processor_name(enum radeon_family family);
699 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
700 struct r600_resource *dst, struct r600_resource *src);
701 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
702 struct radeon_saved_cs *saved, bool get_buffer_list);
703 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
704 bool r600_check_device_reset(struct r600_common_context *rctx);
705
706 /* r600_gpu_load.c */
707 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
708 uint64_t r600_begin_counter(struct r600_common_screen *rscreen, unsigned type);
709 unsigned r600_end_counter(struct r600_common_screen *rscreen, unsigned type,
710 uint64_t begin);
711
712 /* r600_perfcounters.c */
713 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
714
715 /* r600_query.c */
716 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
717 void r600_query_init(struct r600_common_context *rctx);
718 void r600_suspend_queries(struct r600_common_context *ctx);
719 void r600_resume_queries(struct r600_common_context *ctx);
720 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen);
721
722 /* r600_streamout.c */
723 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
724 void r600_set_streamout_targets(struct pipe_context *ctx,
725 unsigned num_targets,
726 struct pipe_stream_output_target **targets,
727 const unsigned *offset);
728 void r600_emit_streamout_end(struct r600_common_context *rctx);
729 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
730 unsigned type, int diff);
731 void r600_streamout_init(struct r600_common_context *rctx);
732
733 /* r600_test_dma.c */
734 void r600_test_dma(struct r600_common_screen *rscreen);
735
736 /* r600_texture.c */
737 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
738 struct r600_texture *rdst,
739 unsigned dst_level, unsigned dstx,
740 unsigned dsty, unsigned dstz,
741 struct r600_texture *rsrc,
742 unsigned src_level,
743 const struct pipe_box *src_box);
744 void r600_texture_destroy(struct pipe_screen *screen, struct pipe_resource *ptex);
745 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
746 struct r600_texture *rtex,
747 unsigned nr_samples,
748 struct r600_fmask_info *out);
749 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
750 struct r600_texture *rtex,
751 struct r600_cmask_info *out);
752 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
753 struct pipe_resource *texture,
754 struct r600_texture **staging);
755 void r600_print_texture_info(struct r600_common_screen *rscreen,
756 struct r600_texture *rtex, struct u_log_context *log);
757 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
758 const struct pipe_resource *templ);
759 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
760 struct pipe_resource *texture,
761 const struct pipe_surface *templ,
762 unsigned width0, unsigned height0,
763 unsigned width, unsigned height);
764 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
765 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
766 struct pipe_framebuffer_state *fb,
767 struct r600_atom *fb_state,
768 unsigned *buffers, uint8_t *dirty_cbufs,
769 const union pipe_color_union *color);
770 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
771 void r600_init_context_texture_functions(struct r600_common_context *rctx);
772 void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
773 struct r600_resource *res,
774 unsigned immed_size);
775 void *r600_texture_transfer_map(struct pipe_context *ctx,
776 struct pipe_resource *texture,
777 unsigned level,
778 unsigned usage,
779 const struct pipe_box *box,
780 struct pipe_transfer **ptransfer);
781 void r600_texture_transfer_unmap(struct pipe_context *ctx,
782 struct pipe_transfer* transfer);
783
784 /* r600_viewport.c */
785 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
786 struct pipe_scissor_state *scissor);
787 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
788 bool scissor_enable, bool clip_halfz);
789 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
790 struct tgsi_shader_info *info);
791 void r600_init_viewport_functions(struct r600_common_context *rctx);
792
793 /* cayman_msaa.c */
794 extern const uint32_t eg_sample_locs_2x[4];
795 extern const unsigned eg_max_dist_2x;
796 extern const uint32_t eg_sample_locs_4x[4];
797 extern const unsigned eg_max_dist_4x;
798 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
799 unsigned sample_index, float *out_value);
800 void cayman_init_msaa(struct pipe_context *ctx);
801 void cayman_emit_msaa_state(struct radeon_cmdbuf *cs, int nr_samples,
802 int ps_iter_samples, int overrast_samples);
803
804
805 /* Inline helpers. */
806
r600_resource(struct pipe_resource * r)807 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
808 {
809 return (struct r600_resource*)r;
810 }
811
812 static inline void
r600_resource_reference(struct r600_resource ** ptr,struct r600_resource * res)813 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
814 {
815 pipe_resource_reference((struct pipe_resource **)ptr,
816 (struct pipe_resource *)res);
817 }
818
819 static inline void
r600_texture_reference(struct r600_texture ** ptr,struct r600_texture * res)820 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
821 {
822 pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
823 }
824
825 static inline void
r600_context_add_resource_size(struct pipe_context * ctx,struct pipe_resource * r)826 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
827 {
828 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
829 struct r600_resource *res = (struct r600_resource *)r;
830
831 if (res) {
832 /* Add memory usage for need_gfx_cs_space */
833 rctx->vram += res->vram_usage;
834 rctx->gtt += res->gart_usage;
835 }
836 }
837
r600_get_strmout_en(struct r600_common_context * rctx)838 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
839 {
840 return rctx->streamout.streamout_enabled ||
841 rctx->streamout.prims_gen_query_enabled;
842 }
843
844 #define SQ_TEX_XY_FILTER_POINT 0x00
845 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
846 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
847 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
848
eg_tex_filter(unsigned filter,unsigned max_aniso)849 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
850 {
851 if (filter == PIPE_TEX_FILTER_LINEAR)
852 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
853 : SQ_TEX_XY_FILTER_BILINEAR;
854 else
855 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
856 : SQ_TEX_XY_FILTER_POINT;
857 }
858
r600_tex_aniso_filter(unsigned filter)859 static inline unsigned r600_tex_aniso_filter(unsigned filter)
860 {
861 if (filter < 2)
862 return 0;
863 if (filter < 4)
864 return 1;
865 if (filter < 8)
866 return 2;
867 if (filter < 16)
868 return 3;
869 return 4;
870 }
871
r600_wavefront_size(enum radeon_family family)872 static inline unsigned r600_wavefront_size(enum radeon_family family)
873 {
874 switch (family) {
875 case CHIP_RV610:
876 case CHIP_RS780:
877 case CHIP_RV620:
878 case CHIP_RS880:
879 return 16;
880 case CHIP_RV630:
881 case CHIP_RV635:
882 case CHIP_RV730:
883 case CHIP_RV710:
884 case CHIP_PALM:
885 case CHIP_CEDAR:
886 return 32;
887 default:
888 return 64;
889 }
890 }
891
892 static inline unsigned
r600_get_sampler_view_priority(struct r600_resource * res)893 r600_get_sampler_view_priority(struct r600_resource *res)
894 {
895 if (res->b.b.target == PIPE_BUFFER)
896 return RADEON_PRIO_SAMPLER_BUFFER;
897
898 if (res->b.b.nr_samples > 1)
899 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
900
901 return RADEON_PRIO_SAMPLER_TEXTURE;
902 }
903
904 static inline bool
r600_can_sample_zs(struct r600_texture * tex,bool stencil_sampler)905 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
906 {
907 return (stencil_sampler && tex->can_sample_s) ||
908 (!stencil_sampler && tex->can_sample_z);
909 }
910
911 static inline bool
r600_htile_enabled(struct r600_texture * tex,unsigned level)912 r600_htile_enabled(struct r600_texture *tex, unsigned level)
913 {
914 return tex->htile_offset && level == 0;
915 }
916
917 #define COMPUTE_DBG(rscreen, fmt, args...) \
918 do { \
919 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
920 } while (0);
921
922 #define R600_ERR(fmt, args...) \
923 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
924
925 /* For MSAA sample positions. */
926 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
927 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
928 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
929 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
930 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
931
S_FIXED(float value,unsigned frac_bits)932 static inline int S_FIXED(float value, unsigned frac_bits)
933 {
934 return value * (1 << frac_bits);
935 }
936
937 #endif
938