1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_formats.h"
24 #include "r600_shader.h"
25 #include "r600d.h"
26 #include "r600d_common.h"
27
28 #include "pipe/p_shader_tokens.h"
29 #include "util/u_endian.h"
30 #include "util/u_pack_color.h"
31 #include "util/u_memory.h"
32 #include "util/u_framebuffer.h"
33 #include "util/u_dual_blend.h"
34
35 #include <assert.h>
36
r600_translate_blend_function(int blend_func)37 static uint32_t r600_translate_blend_function(int blend_func)
38 {
39 switch (blend_func) {
40 case PIPE_BLEND_ADD:
41 return V_028804_COMB_DST_PLUS_SRC;
42 case PIPE_BLEND_SUBTRACT:
43 return V_028804_COMB_SRC_MINUS_DST;
44 case PIPE_BLEND_REVERSE_SUBTRACT:
45 return V_028804_COMB_DST_MINUS_SRC;
46 case PIPE_BLEND_MIN:
47 return V_028804_COMB_MIN_DST_SRC;
48 case PIPE_BLEND_MAX:
49 return V_028804_COMB_MAX_DST_SRC;
50 default:
51 R600_ERR("Unknown blend function %d\n", blend_func);
52 assert(0);
53 break;
54 }
55 return 0;
56 }
57
r600_translate_blend_factor(int blend_fact)58 static uint32_t r600_translate_blend_factor(int blend_fact)
59 {
60 switch (blend_fact) {
61 case PIPE_BLENDFACTOR_ONE:
62 return V_028804_BLEND_ONE;
63 case PIPE_BLENDFACTOR_SRC_COLOR:
64 return V_028804_BLEND_SRC_COLOR;
65 case PIPE_BLENDFACTOR_SRC_ALPHA:
66 return V_028804_BLEND_SRC_ALPHA;
67 case PIPE_BLENDFACTOR_DST_ALPHA:
68 return V_028804_BLEND_DST_ALPHA;
69 case PIPE_BLENDFACTOR_DST_COLOR:
70 return V_028804_BLEND_DST_COLOR;
71 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
72 return V_028804_BLEND_SRC_ALPHA_SATURATE;
73 case PIPE_BLENDFACTOR_CONST_COLOR:
74 return V_028804_BLEND_CONST_COLOR;
75 case PIPE_BLENDFACTOR_CONST_ALPHA:
76 return V_028804_BLEND_CONST_ALPHA;
77 case PIPE_BLENDFACTOR_ZERO:
78 return V_028804_BLEND_ZERO;
79 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
80 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
81 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
82 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
83 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
84 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
85 case PIPE_BLENDFACTOR_INV_DST_COLOR:
86 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
87 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
88 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
89 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
90 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
91 case PIPE_BLENDFACTOR_SRC1_COLOR:
92 return V_028804_BLEND_SRC1_COLOR;
93 case PIPE_BLENDFACTOR_SRC1_ALPHA:
94 return V_028804_BLEND_SRC1_ALPHA;
95 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
96 return V_028804_BLEND_INV_SRC1_COLOR;
97 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
98 return V_028804_BLEND_INV_SRC1_ALPHA;
99 default:
100 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
101 assert(0);
102 break;
103 }
104 return 0;
105 }
106
r600_tex_dim(unsigned dim,unsigned nr_samples)107 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
108 {
109 switch (dim) {
110 default:
111 case PIPE_TEXTURE_1D:
112 return V_038000_SQ_TEX_DIM_1D;
113 case PIPE_TEXTURE_1D_ARRAY:
114 return V_038000_SQ_TEX_DIM_1D_ARRAY;
115 case PIPE_TEXTURE_2D:
116 case PIPE_TEXTURE_RECT:
117 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
118 V_038000_SQ_TEX_DIM_2D;
119 case PIPE_TEXTURE_2D_ARRAY:
120 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
121 V_038000_SQ_TEX_DIM_2D_ARRAY;
122 case PIPE_TEXTURE_3D:
123 return V_038000_SQ_TEX_DIM_3D;
124 case PIPE_TEXTURE_CUBE:
125 case PIPE_TEXTURE_CUBE_ARRAY:
126 return V_038000_SQ_TEX_DIM_CUBEMAP;
127 }
128 }
129
r600_translate_dbformat(enum pipe_format format)130 static uint32_t r600_translate_dbformat(enum pipe_format format)
131 {
132 switch (format) {
133 case PIPE_FORMAT_Z16_UNORM:
134 return V_028010_DEPTH_16;
135 case PIPE_FORMAT_Z24X8_UNORM:
136 return V_028010_DEPTH_X8_24;
137 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
138 return V_028010_DEPTH_8_24;
139 case PIPE_FORMAT_Z32_FLOAT:
140 return V_028010_DEPTH_32_FLOAT;
141 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
142 return V_028010_DEPTH_X24_8_32_FLOAT;
143 default:
144 return ~0U;
145 }
146 }
147
r600_is_sampler_format_supported(struct pipe_screen * screen,enum pipe_format format)148 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
149 {
150 return r600_translate_texformat(screen, format, NULL, NULL, NULL,
151 false) != ~0U;
152 }
153
r600_is_colorbuffer_format_supported(enum amd_gfx_level chip,enum pipe_format format)154 static bool r600_is_colorbuffer_format_supported(enum amd_gfx_level chip, enum pipe_format format)
155 {
156 return r600_translate_colorformat(chip, format, false) != ~0U &&
157 r600_translate_colorswap(format, false) != ~0U;
158 }
159
r600_is_zs_format_supported(enum pipe_format format)160 static bool r600_is_zs_format_supported(enum pipe_format format)
161 {
162 return r600_translate_dbformat(format) != ~0U;
163 }
164
r600_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)165 bool r600_is_format_supported(struct pipe_screen *screen,
166 enum pipe_format format,
167 enum pipe_texture_target target,
168 unsigned sample_count,
169 unsigned storage_sample_count,
170 unsigned usage)
171 {
172 struct r600_screen *rscreen = (struct r600_screen*)screen;
173 unsigned retval = 0;
174
175 if (target >= PIPE_MAX_TEXTURE_TYPES) {
176 R600_ERR("r600: unsupported texture type %d\n", target);
177 return false;
178 }
179
180 if (util_format_get_num_planes(format) > 1)
181 return false;
182
183 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
184 return false;
185
186 if (sample_count > 1) {
187 if (!rscreen->has_msaa)
188 return false;
189
190 /* R11G11B10 is broken on R6xx. */
191 if (rscreen->b.gfx_level == R600 &&
192 format == PIPE_FORMAT_R11G11B10_FLOAT)
193 return false;
194
195 /* MSAA integer colorbuffers hang. */
196 if (util_format_is_pure_integer(format) &&
197 !util_format_is_depth_or_stencil(format))
198 return false;
199
200 switch (sample_count) {
201 case 2:
202 case 4:
203 case 8:
204 break;
205 default:
206 return false;
207 }
208 }
209
210 if (usage & PIPE_BIND_SAMPLER_VIEW) {
211 if (target == PIPE_BUFFER) {
212 if (r600_is_buffer_format_supported(format, false))
213 retval |= PIPE_BIND_SAMPLER_VIEW;
214 } else {
215 if (r600_is_sampler_format_supported(screen, format))
216 retval |= PIPE_BIND_SAMPLER_VIEW;
217 }
218 }
219
220 if ((usage & (PIPE_BIND_RENDER_TARGET |
221 PIPE_BIND_DISPLAY_TARGET |
222 PIPE_BIND_SCANOUT |
223 PIPE_BIND_SHARED |
224 PIPE_BIND_BLENDABLE)) &&
225 r600_is_colorbuffer_format_supported(rscreen->b.gfx_level, format)) {
226 retval |= usage &
227 (PIPE_BIND_RENDER_TARGET |
228 PIPE_BIND_DISPLAY_TARGET |
229 PIPE_BIND_SCANOUT |
230 PIPE_BIND_SHARED);
231 if (!util_format_is_pure_integer(format) &&
232 !util_format_is_depth_or_stencil(format))
233 retval |= usage & PIPE_BIND_BLENDABLE;
234 }
235
236 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
237 r600_is_zs_format_supported(format)) {
238 retval |= PIPE_BIND_DEPTH_STENCIL;
239 }
240
241 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
242 r600_is_buffer_format_supported(format, true)) {
243 retval |= PIPE_BIND_VERTEX_BUFFER;
244 }
245
246 if (usage & PIPE_BIND_INDEX_BUFFER &&
247 r600_is_index_format_supported(format)) {
248 retval |= PIPE_BIND_INDEX_BUFFER;
249 }
250
251 if ((usage & PIPE_BIND_LINEAR) &&
252 !util_format_is_compressed(format) &&
253 !(usage & PIPE_BIND_DEPTH_STENCIL))
254 retval |= PIPE_BIND_LINEAR;
255
256 return retval == usage;
257 }
258
r600_emit_polygon_offset(struct r600_context * rctx,struct r600_atom * a)259 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
260 {
261 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
262 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
263 float offset_units = state->offset_units;
264 float offset_scale = state->offset_scale;
265 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
266
267 if (!state->offset_units_unscaled) {
268 switch (state->zs_format) {
269 case PIPE_FORMAT_Z24X8_UNORM:
270 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
271 offset_units *= 2.0f;
272 pa_su_poly_offset_db_fmt_cntl =
273 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
274 break;
275 case PIPE_FORMAT_Z16_UNORM:
276 offset_units *= 4.0f;
277 pa_su_poly_offset_db_fmt_cntl =
278 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
279 break;
280 default:
281 pa_su_poly_offset_db_fmt_cntl =
282 S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
283 S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
284 }
285 }
286
287 radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 4);
288 radeon_emit(cs, fui(offset_scale));
289 radeon_emit(cs, fui(offset_units));
290 radeon_emit(cs, fui(offset_scale));
291 radeon_emit(cs, fui(offset_units));
292
293 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
294 pa_su_poly_offset_db_fmt_cntl);
295 }
296
r600_get_blend_control(const struct pipe_blend_state * state,unsigned i)297 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, unsigned i)
298 {
299 int j = state->independent_blend_enable ? i : 0;
300
301 unsigned eqRGB = state->rt[j].rgb_func;
302 unsigned srcRGB = state->rt[j].rgb_src_factor;
303 unsigned dstRGB = state->rt[j].rgb_dst_factor;
304
305 unsigned eqA = state->rt[j].alpha_func;
306 unsigned srcA = state->rt[j].alpha_src_factor;
307 unsigned dstA = state->rt[j].alpha_dst_factor;
308 uint32_t bc = 0;
309
310 if (!state->rt[j].blend_enable)
311 return 0;
312
313 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
314 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
315 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
316
317 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
318 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
319 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
320 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
321 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
322 }
323 return bc;
324 }
325
r600_create_blend_state_mode(struct pipe_context * ctx,const struct pipe_blend_state * state,int mode)326 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
327 const struct pipe_blend_state *state,
328 int mode)
329 {
330 struct r600_context *rctx = (struct r600_context *)ctx;
331 uint32_t color_control = 0, target_mask = 0;
332 struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
333
334 if (!blend) {
335 return NULL;
336 }
337
338 r600_init_command_buffer(&blend->buffer, 20);
339 r600_init_command_buffer(&blend->buffer_no_blend, 20);
340
341 /* R600 does not support per-MRT blends */
342 if (rctx->b.family > CHIP_R600)
343 color_control |= S_028808_PER_MRT_BLEND(1);
344
345 if (state->logicop_enable) {
346 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
347 } else {
348 color_control |= (0xcc << 16);
349 }
350 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
351 if (state->independent_blend_enable) {
352 for (int i = 0; i < 8; i++) {
353 if (state->rt[i].blend_enable) {
354 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
355 }
356 target_mask |= (state->rt[i].colormask << (4 * i));
357 }
358 } else {
359 for (int i = 0; i < 8; i++) {
360 if (state->rt[0].blend_enable) {
361 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
362 }
363 target_mask |= (state->rt[0].colormask << (4 * i));
364 }
365 }
366
367 if (target_mask)
368 color_control |= S_028808_SPECIAL_OP(mode);
369 else
370 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
371
372 /* only MRT0 has dual src blend */
373 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
374 blend->cb_target_mask = target_mask;
375 blend->cb_color_control = color_control;
376 blend->cb_color_control_no_blend = color_control & C_028808_TARGET_BLEND_ENABLE;
377 blend->alpha_to_one = state->alpha_to_one;
378
379 r600_store_context_reg(&blend->buffer, R_028D44_DB_ALPHA_TO_MASK,
380 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
381 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
382 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
383 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
384 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
385
386 /* Copy over the registers set so far into buffer_no_blend. */
387 memcpy(blend->buffer_no_blend.buf, blend->buffer.buf, blend->buffer.num_dw * 4);
388 blend->buffer_no_blend.num_dw = blend->buffer.num_dw;
389
390 /* Only add blend registers if blending is enabled. */
391 if (!G_028808_TARGET_BLEND_ENABLE(color_control)) {
392 return blend;
393 }
394
395 /* The first R600 does not support per-MRT blends */
396 r600_store_context_reg(&blend->buffer, R_028804_CB_BLEND_CONTROL,
397 r600_get_blend_control(state, 0));
398
399 if (rctx->b.family > CHIP_R600) {
400 r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
401 for (int i = 0; i < 8; i++) {
402 r600_store_value(&blend->buffer, r600_get_blend_control(state, i));
403 }
404 }
405 return blend;
406 }
407
r600_create_blend_state(struct pipe_context * ctx,const struct pipe_blend_state * state)408 static void *r600_create_blend_state(struct pipe_context *ctx,
409 const struct pipe_blend_state *state)
410 {
411 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
412 }
413
r600_create_dsa_state(struct pipe_context * ctx,const struct pipe_depth_stencil_alpha_state * state)414 static void *r600_create_dsa_state(struct pipe_context *ctx,
415 const struct pipe_depth_stencil_alpha_state *state)
416 {
417 unsigned db_depth_control, alpha_test_control, alpha_ref;
418 struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state);
419
420 if (!dsa) {
421 return NULL;
422 }
423
424 r600_init_command_buffer(&dsa->buffer, 3);
425
426 dsa->valuemask[0] = state->stencil[0].valuemask;
427 dsa->valuemask[1] = state->stencil[1].valuemask;
428 dsa->writemask[0] = state->stencil[0].writemask;
429 dsa->writemask[1] = state->stencil[1].writemask;
430 dsa->zwritemask = state->depth_writemask;
431
432 db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) |
433 S_028800_Z_WRITE_ENABLE(state->depth_writemask) |
434 S_028800_ZFUNC(state->depth_func);
435
436 /* stencil */
437 if (state->stencil[0].enabled) {
438 db_depth_control |= S_028800_STENCIL_ENABLE(1);
439 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
440 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
441 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
442 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
443
444 if (state->stencil[1].enabled) {
445 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
446 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
447 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
448 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
449 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
450 }
451 }
452
453 /* alpha */
454 alpha_test_control = 0;
455 alpha_ref = 0;
456 if (state->alpha_enabled) {
457 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha_func);
458 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
459 alpha_ref = fui(state->alpha_ref_value);
460 }
461 dsa->sx_alpha_test_control = alpha_test_control & 0xff;
462 dsa->alpha_ref = alpha_ref;
463
464 r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control);
465 return dsa;
466 }
467
r600_create_rs_state(struct pipe_context * ctx,const struct pipe_rasterizer_state * state)468 static void *r600_create_rs_state(struct pipe_context *ctx,
469 const struct pipe_rasterizer_state *state)
470 {
471 struct r600_context *rctx = (struct r600_context *)ctx;
472 unsigned tmp, sc_mode_cntl, spi_interp;
473 float psize_min, psize_max;
474 struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state);
475
476 if (!rs) {
477 return NULL;
478 }
479
480 r600_init_command_buffer(&rs->buffer, 30);
481
482 rs->scissor_enable = state->scissor;
483 rs->clip_halfz = state->clip_halfz;
484 rs->flatshade = state->flatshade;
485 rs->sprite_coord_enable = state->sprite_coord_enable;
486 rs->rasterizer_discard = state->rasterizer_discard;
487 rs->two_side = state->light_twoside;
488 rs->clip_plane_enable = state->clip_plane_enable;
489 rs->pa_sc_line_stipple = state->line_stipple_enable ?
490 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
491 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
492 rs->pa_cl_clip_cntl =
493 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
494 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
495 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
496 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
497 if (rctx->b.gfx_level == R700) {
498 rs->pa_cl_clip_cntl |=
499 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
500 }
501 rs->multisample_enable = state->multisample;
502
503 /* offset */
504 rs->offset_units = state->offset_units;
505 rs->offset_scale = state->offset_scale * 16.0f;
506 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
507 rs->offset_units_unscaled = state->offset_units_unscaled;
508
509 if (state->point_size_per_vertex) {
510 psize_min = util_get_min_point_size(state);
511 psize_max = 8192;
512 } else {
513 /* Force the point size to be as if the vertex output was disabled. */
514 psize_min = state->point_size;
515 psize_max = state->point_size;
516 }
517
518 sc_mode_cntl = S_028A4C_MSAA_ENABLE(state->multisample) |
519 S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
520 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
521 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
522 if (rctx->b.family == CHIP_RV770) {
523 /* workaround possible rendering corruption on RV770 with hyperz together with sample shading */
524 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
525 }
526 if (rctx->b.gfx_level >= R700) {
527 sc_mode_cntl |= S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
528 S_028A4C_R700_ZMM_LINE_OFFSET(1) |
529 S_028A4C_R700_VPORT_SCISSOR_ENABLE(1);
530 } else {
531 sc_mode_cntl |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1);
532 }
533
534 spi_interp = S_0286D4_FLAT_SHADE_ENA(1);
535 spi_interp |= S_0286D4_PNT_SPRITE_ENA(1) |
536 S_0286D4_PNT_SPRITE_OVRD_X(2) |
537 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
538 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
539 S_0286D4_PNT_SPRITE_OVRD_W(1);
540 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
541 spi_interp |= S_0286D4_PNT_SPRITE_TOP_1(1);
542 }
543
544 r600_store_context_reg_seq(&rs->buffer, R_028A00_PA_SU_POINT_SIZE, 3);
545 /* point size 12.4 fixed point (divide by two, because 0.5 = 1 pixel. */
546 tmp = r600_pack_float_12p4(state->point_size/2);
547 r600_store_value(&rs->buffer, /* R_028A00_PA_SU_POINT_SIZE */
548 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
549 r600_store_value(&rs->buffer, /* R_028A04_PA_SU_POINT_MINMAX */
550 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
551 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
552 r600_store_value(&rs->buffer, /* R_028A08_PA_SU_LINE_CNTL */
553 S_028A08_WIDTH(r600_pack_float_12p4(state->line_width/2)));
554
555 r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp);
556 r600_store_context_reg(&rs->buffer, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
557 r600_store_context_reg(&rs->buffer, R_028C08_PA_SU_VTX_CNTL,
558 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
559 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
560 r600_store_context_reg(&rs->buffer, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
561
562 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
563 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
564 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
565 S_028814_FACE(!state->front_ccw) |
566 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
567 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
568 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
569 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
570 state->fill_back != PIPE_POLYGON_MODE_FILL) |
571 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
572 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
573 if (rctx->b.gfx_level == R700) {
574 r600_store_context_reg(&rs->buffer, R_028814_PA_SU_SC_MODE_CNTL, rs->pa_su_sc_mode_cntl);
575 }
576 if (rctx->b.gfx_level == R600) {
577 r600_store_context_reg(&rs->buffer, R_028350_SX_MISC,
578 S_028350_MULTIPASS(state->rasterizer_discard));
579 }
580 return rs;
581 }
582
r600_tex_filter(unsigned filter,unsigned max_aniso)583 static unsigned r600_tex_filter(unsigned filter, unsigned max_aniso)
584 {
585 if (filter == PIPE_TEX_FILTER_LINEAR)
586 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_BILINEAR
587 : V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
588 else
589 return max_aniso > 1 ? V_03C000_SQ_TEX_XY_FILTER_ANISO_POINT
590 : V_03C000_SQ_TEX_XY_FILTER_POINT;
591 }
592
r600_create_sampler_state(struct pipe_context * ctx,const struct pipe_sampler_state * state)593 static void *r600_create_sampler_state(struct pipe_context *ctx,
594 const struct pipe_sampler_state *state)
595 {
596 struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen;
597 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
598 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
599 : state->max_anisotropy;
600 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
601
602 if (!ss) {
603 return NULL;
604 }
605
606 ss->seamless_cube_map = state->seamless_cube_map;
607 ss->border_color_use = sampler_state_needs_border_color(state);
608
609 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
610 ss->tex_sampler_words[0] =
611 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
612 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
613 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
614 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter, max_aniso)) |
615 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter, max_aniso)) |
616 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
617 S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) |
618 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
619 S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
620 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
621 ss->tex_sampler_words[1] =
622 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
623 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
624 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
625 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
626 ss->tex_sampler_words[2] = S_03C008_TYPE(1);
627
628 if (ss->border_color_use) {
629 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
630 }
631 return ss;
632 }
633
634 static struct pipe_sampler_view *
texture_buffer_sampler_view(struct r600_pipe_sampler_view * view,unsigned width0,unsigned height0)635 texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
636 unsigned width0, unsigned height0)
637
638 {
639 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
640 int stride = util_format_get_blocksize(view->base.format);
641 unsigned format, num_format, format_comp, endian;
642 uint64_t offset = view->base.u.buf.offset;
643 unsigned size = view->base.u.buf.size;
644
645 r600_vertex_data_type(view->base.format,
646 &format, &num_format, &format_comp,
647 &endian);
648
649 view->tex_resource = &tmp->resource;
650 view->skip_mip_address_reloc = true;
651
652 view->tex_resource_words[0] = offset;
653 view->tex_resource_words[1] = size - 1;
654 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
655 S_038008_STRIDE(stride) |
656 S_038008_DATA_FORMAT(format) |
657 S_038008_NUM_FORMAT_ALL(num_format) |
658 S_038008_FORMAT_COMP_ALL(format_comp) |
659 S_038008_ENDIAN_SWAP(endian);
660 view->tex_resource_words[3] = 0;
661 /*
662 * in theory dword 4 is for number of elements, for use with resinfo,
663 * but it seems to utterly fail to work, the amd gpu shader analyser
664 * uses a const buffer to store the element sizes for buffer txq
665 */
666 view->tex_resource_words[4] = 0;
667 view->tex_resource_words[5] = 0;
668 view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
669 return &view->base;
670 }
671
672 struct pipe_sampler_view *
r600_create_sampler_view_custom(struct pipe_context * ctx,struct pipe_resource * texture,const struct pipe_sampler_view * state,unsigned width_first_level,unsigned height_first_level)673 r600_create_sampler_view_custom(struct pipe_context *ctx,
674 struct pipe_resource *texture,
675 const struct pipe_sampler_view *state,
676 unsigned width_first_level, unsigned height_first_level)
677 {
678 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
679 struct r600_texture *tmp = (struct r600_texture*)texture;
680 unsigned format, endian;
681 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
682 unsigned char swizzle[4], array_mode = 0;
683 unsigned width, height, depth, offset_level, last_level;
684 bool do_endian_swap = false;
685
686 if (!view)
687 return NULL;
688
689 /* initialize base object */
690 view->base = *state;
691 view->base.texture = NULL;
692 pipe_reference(NULL, &texture->reference);
693 view->base.texture = texture;
694 view->base.reference.count = 1;
695 view->base.context = ctx;
696
697 if (texture->target == PIPE_BUFFER)
698 return texture_buffer_sampler_view(view, texture->width0, 1);
699
700 swizzle[0] = state->swizzle_r;
701 swizzle[1] = state->swizzle_g;
702 swizzle[2] = state->swizzle_b;
703 swizzle[3] = state->swizzle_a;
704
705 if (UTIL_ARCH_BIG_ENDIAN)
706 do_endian_swap = !tmp->db_compatible;
707
708 format = r600_translate_texformat(ctx->screen, state->format,
709 swizzle,
710 &word4, &yuv_format, do_endian_swap);
711 assert(format != ~0);
712 if (format == ~0) {
713 FREE(view);
714 return NULL;
715 }
716
717 if (state->format == PIPE_FORMAT_X24S8_UINT ||
718 state->format == PIPE_FORMAT_S8X24_UINT ||
719 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
720 state->format == PIPE_FORMAT_S8_UINT)
721 view->is_stencil_sampler = true;
722
723 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
724 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
725 FREE(view);
726 return NULL;
727 }
728 tmp = tmp->flushed_depth_texture;
729 }
730
731 endian = r600_colorformat_endian_swap(format, do_endian_swap);
732
733 offset_level = state->u.tex.first_level;
734 last_level = state->u.tex.last_level - offset_level;
735 width = width_first_level;
736 height = height_first_level;
737 depth = u_minify(texture->depth0, offset_level);
738 pitch = tmp->surface.u.legacy.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
739
740 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
741 height = 1;
742 depth = texture->array_size;
743 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
744 depth = texture->array_size;
745 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
746 depth = texture->array_size / 6;
747
748 switch (tmp->surface.u.legacy.level[offset_level].mode) {
749 default:
750 case RADEON_SURF_MODE_LINEAR_ALIGNED:
751 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
752 break;
753 case RADEON_SURF_MODE_1D:
754 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
755 break;
756 case RADEON_SURF_MODE_2D:
757 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
758 break;
759 }
760
761 view->tex_resource = &tmp->resource;
762 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
763 S_038000_TILE_MODE(array_mode) |
764 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
765 S_038000_PITCH((pitch / 8) - 1) |
766 S_038000_TEX_WIDTH(width - 1));
767 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
768 S_038004_TEX_DEPTH(depth - 1) |
769 S_038004_DATA_FORMAT(format));
770 view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset_256B;
771 if (offset_level >= tmp->resource.b.b.last_level) {
772 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset_256B;
773 } else {
774 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset_256B;
775 }
776 view->tex_resource_words[4] = (word4 |
777 S_038010_REQUEST_SIZE(1) |
778 S_038010_ENDIAN_SWAP(endian) |
779 S_038010_BASE_LEVEL(0));
780 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
781 S_038014_LAST_ARRAY(state->u.tex.last_layer));
782 if (texture->nr_samples > 1) {
783 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
784 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
785 } else {
786 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
787 }
788 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
789 S_038018_MAX_ANISO(4 /* max 16 samples */));
790 return &view->base;
791 }
792
793 static struct pipe_sampler_view *
r600_create_sampler_view(struct pipe_context * ctx,struct pipe_resource * tex,const struct pipe_sampler_view * state)794 r600_create_sampler_view(struct pipe_context *ctx,
795 struct pipe_resource *tex,
796 const struct pipe_sampler_view *state)
797 {
798 return r600_create_sampler_view_custom(ctx, tex, state,
799 u_minify(tex->width0, state->u.tex.first_level),
800 u_minify(tex->height0, state->u.tex.first_level));
801 }
802
r600_emit_clip_state(struct r600_context * rctx,struct r600_atom * atom)803 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
804 {
805 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
806 struct pipe_clip_state *state = &rctx->clip_state.state;
807
808 radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
809 radeon_emit_array(cs, (unsigned*)state, 6*4);
810 }
811
r600_set_polygon_stipple(struct pipe_context * ctx,const struct pipe_poly_stipple * state)812 static void r600_set_polygon_stipple(struct pipe_context *ctx,
813 const struct pipe_poly_stipple *state)
814 {
815 }
816
r600_init_color_surface(struct r600_context * rctx,struct r600_surface * surf,bool force_cmask_fmask)817 static void r600_init_color_surface(struct r600_context *rctx,
818 struct r600_surface *surf,
819 bool force_cmask_fmask)
820 {
821 struct r600_screen *rscreen = rctx->screen;
822 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
823 unsigned level = surf->base.u.tex.level;
824 unsigned pitch, slice;
825 unsigned color_info;
826 unsigned color_view;
827 unsigned format, swap, ntype, endian;
828 unsigned offset;
829 const struct util_format_description *desc;
830 int i;
831 bool blend_bypass = 0, blend_clamp = 0, do_endian_swap = false;
832
833 if (rtex->db_compatible && !r600_can_sample_zs(rtex, false)) {
834 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
835 rtex = rtex->flushed_depth_texture;
836 assert(rtex);
837 }
838
839 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
840 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
841 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
842
843 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
844 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
845 if (slice) {
846 slice = slice - 1;
847 }
848 color_info = 0;
849 switch (rtex->surface.u.legacy.level[level].mode) {
850 default:
851 case RADEON_SURF_MODE_LINEAR_ALIGNED:
852 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
853 break;
854 case RADEON_SURF_MODE_1D:
855 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
856 break;
857 case RADEON_SURF_MODE_2D:
858 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
859 break;
860 }
861
862 desc = util_format_description(surf->base.format);
863
864 i = util_format_get_first_non_void_channel(surf->base.format);
865
866 ntype = V_0280A0_NUMBER_UNORM;
867 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
868 ntype = V_0280A0_NUMBER_SRGB;
869 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
870 if (desc->channel[i].normalized)
871 ntype = V_0280A0_NUMBER_SNORM;
872 else if (desc->channel[i].pure_integer)
873 ntype = V_0280A0_NUMBER_SINT;
874 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
875 if (desc->channel[i].normalized)
876 ntype = V_0280A0_NUMBER_UNORM;
877 else if (desc->channel[i].pure_integer)
878 ntype = V_0280A0_NUMBER_UINT;
879 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
880 ntype = V_0280A0_NUMBER_FLOAT;
881 }
882
883 if (UTIL_ARCH_BIG_ENDIAN)
884 do_endian_swap = !rtex->db_compatible;
885
886 format = r600_translate_colorformat(rctx->b.gfx_level, surf->base.format,
887 do_endian_swap);
888 assert(format != ~0);
889
890 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
891 assert(swap != ~0);
892
893 endian = r600_colorformat_endian_swap(format, do_endian_swap);
894
895 /* blend clamp should be set for all NORM/SRGB types */
896 if (ntype == V_0280A0_NUMBER_UNORM || ntype == V_0280A0_NUMBER_SNORM ||
897 ntype == V_0280A0_NUMBER_SRGB)
898 blend_clamp = 1;
899
900 /* set blend bypass according to docs if SINT/UINT or
901 8/24 COLOR variants */
902 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
903 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
904 format == V_0280A0_COLOR_X24_8_32_FLOAT) {
905 blend_clamp = 0;
906 blend_bypass = 1;
907 }
908
909 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
910
911 color_info |= S_0280A0_FORMAT(format) |
912 S_0280A0_COMP_SWAP(swap) |
913 S_0280A0_BLEND_BYPASS(blend_bypass) |
914 S_0280A0_BLEND_CLAMP(blend_clamp) |
915 S_0280A0_SIMPLE_FLOAT(1) |
916 S_0280A0_NUMBER_TYPE(ntype) |
917 S_0280A0_ENDIAN(endian);
918
919 /* EXPORT_NORM is an optimization that can be enabled for better
920 * performance in certain cases
921 */
922 if (rctx->b.gfx_level == R600) {
923 /* EXPORT_NORM can be enabled if:
924 * - 11-bit or smaller UNORM/SNORM/SRGB
925 * - BLEND_CLAMP is enabled
926 * - BLEND_FLOAT32 is disabled
927 */
928 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
929 (desc->channel[i].size < 12 &&
930 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
931 ntype != V_0280A0_NUMBER_UINT &&
932 ntype != V_0280A0_NUMBER_SINT) &&
933 G_0280A0_BLEND_CLAMP(color_info) &&
934 /* XXX this condition is always true since BLEND_FLOAT32 is never set (bug?). */
935 !G_0280A0_BLEND_FLOAT32(color_info)) {
936 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
937 surf->export_16bpc = true;
938 }
939 } else {
940 /* EXPORT_NORM can be enabled if:
941 * - 11-bit or smaller UNORM/SNORM/SRGB
942 * - 16-bit or smaller FLOAT
943 */
944 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
945 ((desc->channel[i].size < 12 &&
946 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
947 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
948 (desc->channel[i].size < 17 &&
949 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
950 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
951 surf->export_16bpc = true;
952 }
953 }
954
955 /* These might not always be initialized to zero. */
956 surf->cb_color_base = offset >> 8;
957 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
958 S_028060_SLICE_TILE_MAX(slice);
959 surf->cb_color_fmask = surf->cb_color_base;
960 surf->cb_color_cmask = surf->cb_color_base;
961 surf->cb_color_mask = 0;
962
963 r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource);
964 r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource);
965
966 if (rtex->cmask.size) {
967 surf->cb_color_cmask = rtex->cmask.offset >> 8;
968 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
969
970 if (rtex->fmask.size) {
971 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
972 surf->cb_color_fmask = rtex->fmask.offset >> 8;
973 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
974 } else { /* cmask only */
975 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
976 }
977 } else if (force_cmask_fmask) {
978 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
979 *
980 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
981 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
982 * because it's not an MSAA buffer.
983 */
984 struct r600_cmask_info cmask;
985 struct r600_fmask_info fmask;
986
987 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask);
988 r600_texture_get_fmask_info(&rscreen->b, rtex, 8, &fmask);
989
990 /* CMASK. */
991 if (!rctx->dummy_cmask ||
992 rctx->dummy_cmask->b.b.width0 < cmask.size ||
993 (1 << rctx->dummy_cmask->buf->alignment_log2) % cmask.alignment != 0) {
994 struct pipe_transfer *transfer;
995 void *ptr;
996
997 r600_resource_reference(&rctx->dummy_cmask, NULL);
998 rctx->dummy_cmask = (struct r600_resource*)
999 r600_aligned_buffer_create(&rscreen->b.b, 0,
1000 PIPE_USAGE_DEFAULT,
1001 cmask.size, cmask.alignment);
1002
1003 if (unlikely(!rctx->dummy_cmask)) {
1004 surf->color_initialized = false;
1005 return;
1006 }
1007
1008 /* Set the contents to 0xCC. */
1009 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_MAP_WRITE, &transfer);
1010 memset(ptr, 0xCC, cmask.size);
1011 pipe_buffer_unmap(&rctx->b.b, transfer);
1012 }
1013 r600_resource_reference(&surf->cb_buffer_cmask, rctx->dummy_cmask);
1014
1015 /* FMASK. */
1016 if (!rctx->dummy_fmask ||
1017 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1018 (1 << rctx->dummy_fmask->buf->alignment_log2) % fmask.alignment != 0) {
1019 r600_resource_reference(&rctx->dummy_fmask, NULL);
1020 rctx->dummy_fmask = (struct r600_resource*)
1021 r600_aligned_buffer_create(&rscreen->b.b, 0,
1022 PIPE_USAGE_DEFAULT,
1023 fmask.size, fmask.alignment);
1024
1025 if (unlikely(!rctx->dummy_fmask)) {
1026 surf->color_initialized = false;
1027 return;
1028 }
1029 }
1030 r600_resource_reference(&surf->cb_buffer_fmask, rctx->dummy_fmask);
1031
1032 /* Init the registers. */
1033 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1034 surf->cb_color_cmask = 0;
1035 surf->cb_color_fmask = 0;
1036 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1037 S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
1038 }
1039
1040 surf->cb_color_info = color_info;
1041 surf->cb_color_view = color_view;
1042 surf->color_initialized = true;
1043 }
1044
r600_init_depth_surface(struct r600_context * rctx,struct r600_surface * surf)1045 static void r600_init_depth_surface(struct r600_context *rctx,
1046 struct r600_surface *surf)
1047 {
1048 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1049 unsigned level, pitch, slice, format, offset, array_mode;
1050
1051 level = surf->base.u.tex.level;
1052 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
1053 pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
1054 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1055 if (slice) {
1056 slice = slice - 1;
1057 }
1058 switch (rtex->surface.u.legacy.level[level].mode) {
1059 case RADEON_SURF_MODE_2D:
1060 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1061 break;
1062 case RADEON_SURF_MODE_1D:
1063 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1064 default:
1065 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1066 break;
1067 }
1068
1069 format = r600_translate_dbformat(surf->base.format);
1070 assert(format != ~0);
1071
1072 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1073 surf->db_depth_base = offset >> 8;
1074 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1075 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1076 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1077 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1;
1078
1079 if (r600_htile_enabled(rtex, level)) {
1080 surf->db_htile_data_base = rtex->htile_offset >> 8;
1081 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1082 S_028D24_HTILE_HEIGHT(1) |
1083 S_028D24_FULL_CACHE(1);
1084 /* preload is not working properly on r6xx/r7xx */
1085 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1086 }
1087
1088 surf->depth_initialized = true;
1089 }
1090
r600_set_framebuffer_state(struct pipe_context * ctx,const struct pipe_framebuffer_state * state)1091 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1092 const struct pipe_framebuffer_state *state)
1093 {
1094 struct r600_context *rctx = (struct r600_context *)ctx;
1095 struct r600_surface *surf;
1096 struct r600_texture *rtex;
1097 unsigned i;
1098 uint32_t target_mask = 0;
1099
1100 /* Flush TC when changing the framebuffer state, because the only
1101 * client not using TC that can change textures is the framebuffer.
1102 * Other places don't typically have to flush TC.
1103 */
1104 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1105 R600_CONTEXT_FLUSH_AND_INV |
1106 R600_CONTEXT_FLUSH_AND_INV_CB |
1107 R600_CONTEXT_FLUSH_AND_INV_CB_META |
1108 R600_CONTEXT_FLUSH_AND_INV_DB |
1109 R600_CONTEXT_FLUSH_AND_INV_DB_META |
1110 R600_CONTEXT_INV_TEX_CACHE;
1111
1112 /* Set the new state. */
1113 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1114
1115 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1116 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1117 util_format_is_pure_integer(state->cbufs[0]->format);
1118 rctx->framebuffer.compressed_cb_mask = 0;
1119 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1120 state->cbufs[0] && state->cbufs[1] &&
1121 state->cbufs[0]->texture->nr_samples > 1 &&
1122 state->cbufs[1]->texture->nr_samples <= 1;
1123 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1124
1125 /* Colorbuffers. */
1126 for (i = 0; i < state->nr_cbufs; i++) {
1127 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1128 bool force_cmask_fmask = rctx->b.gfx_level == R600 &&
1129 rctx->framebuffer.is_msaa_resolve &&
1130 i == 1;
1131
1132 surf = (struct r600_surface*)state->cbufs[i];
1133 if (!surf)
1134 continue;
1135
1136 rtex = (struct r600_texture*)surf->base.texture;
1137 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1138
1139 target_mask |= (0xf << (i * 4));
1140
1141 if (!surf->color_initialized || force_cmask_fmask) {
1142 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1143 if (force_cmask_fmask) {
1144 /* re-initialize later without compression */
1145 surf->color_initialized = false;
1146 }
1147 }
1148
1149 if (!surf->export_16bpc) {
1150 rctx->framebuffer.export_16bpc = false;
1151 }
1152
1153 if (rtex->fmask.size) {
1154 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1155 }
1156 }
1157
1158 /* Update alpha-test state dependencies.
1159 * Alpha-test is done on the first colorbuffer only. */
1160 if (state->nr_cbufs) {
1161 bool alphatest_bypass = false;
1162
1163 surf = (struct r600_surface*)state->cbufs[0];
1164 if (surf) {
1165 alphatest_bypass = surf->alphatest_bypass;
1166 }
1167
1168 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1169 rctx->alphatest_state.bypass = alphatest_bypass;
1170 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1171 }
1172 }
1173
1174 /* ZS buffer. */
1175 if (state->zsbuf) {
1176 surf = (struct r600_surface*)state->zsbuf;
1177
1178 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1179
1180 if (!surf->depth_initialized) {
1181 r600_init_depth_surface(rctx, surf);
1182 }
1183
1184 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1185 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1186 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1187 }
1188
1189 if (rctx->db_state.rsurf != surf) {
1190 rctx->db_state.rsurf = surf;
1191 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1192 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1193 }
1194 } else if (rctx->db_state.rsurf) {
1195 rctx->db_state.rsurf = NULL;
1196 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1197 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1198 }
1199
1200 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
1201 rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) {
1202 rctx->cb_misc_state.bound_cbufs_target_mask = target_mask;
1203 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1204 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1205 }
1206
1207 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1208 rctx->alphatest_state.bypass = false;
1209 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1210 }
1211
1212 /* Calculate the CS size. */
1213 rctx->framebuffer.atom.num_dw =
1214 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
1215
1216 if (rctx->framebuffer.state.nr_cbufs) {
1217 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1218 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1219 }
1220 if (rctx->framebuffer.state.zsbuf) {
1221 rctx->framebuffer.atom.num_dw += 16;
1222 } else {
1223 rctx->framebuffer.atom.num_dw += 3;
1224 }
1225 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1226 rctx->framebuffer.atom.num_dw += 2;
1227 }
1228
1229 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1230
1231 r600_set_sample_locations_constant_buffer(rctx);
1232 rctx->framebuffer.do_update_surf_dirtiness = true;
1233 }
1234
1235 static const uint32_t sample_locs_2x[] = {
1236 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1237 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1238 };
1239 static const unsigned max_dist_2x = 4;
1240
1241 static const uint32_t sample_locs_4x[] = {
1242 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1243 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1244 };
1245 static const unsigned max_dist_4x = 6;
1246 static const uint32_t sample_locs_8x[] = {
1247 FILL_SREG(-1, 1, 1, 5, 3, -5, 5, 3),
1248 FILL_SREG(-7, -1, -3, -7, 7, -3, -5, 7),
1249 };
1250 static const unsigned max_dist_8x = 7;
1251
r600_get_sample_position(struct pipe_context * ctx,unsigned sample_count,unsigned sample_index,float * out_value)1252 static void r600_get_sample_position(struct pipe_context *ctx,
1253 unsigned sample_count,
1254 unsigned sample_index,
1255 float *out_value)
1256 {
1257 int offset, index;
1258 struct {
1259 int idx:4;
1260 } val;
1261 switch (sample_count) {
1262 case 1:
1263 default:
1264 out_value[0] = out_value[1] = 0.5;
1265 break;
1266 case 2:
1267 offset = 4 * (sample_index * 2);
1268 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1269 out_value[0] = (float)(val.idx + 8) / 16.0f;
1270 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1271 out_value[1] = (float)(val.idx + 8) / 16.0f;
1272 break;
1273 case 4:
1274 offset = 4 * (sample_index * 2);
1275 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1276 out_value[0] = (float)(val.idx + 8) / 16.0f;
1277 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1278 out_value[1] = (float)(val.idx + 8) / 16.0f;
1279 break;
1280 case 8:
1281 offset = 4 * (sample_index % 4 * 2);
1282 index = (sample_index / 4);
1283 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1284 out_value[0] = (float)(val.idx + 8) / 16.0f;
1285 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1286 out_value[1] = (float)(val.idx + 8) / 16.0f;
1287 break;
1288 }
1289 }
1290
r600_emit_msaa_state(struct r600_context * rctx,int nr_samples)1291 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1292 {
1293 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1294 unsigned max_dist = 0;
1295
1296 if (rctx->b.family == CHIP_R600) {
1297 switch (nr_samples) {
1298 default:
1299 nr_samples = 0;
1300 break;
1301 case 2:
1302 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1303 max_dist = max_dist_2x;
1304 break;
1305 case 4:
1306 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1307 max_dist = max_dist_4x;
1308 break;
1309 case 8:
1310 radeon_set_config_reg_seq(cs, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, 2);
1311 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */
1312 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */
1313 max_dist = max_dist_8x;
1314 break;
1315 }
1316 } else {
1317 switch (nr_samples) {
1318 default:
1319 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1320 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1321 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1322 nr_samples = 0;
1323 break;
1324 case 2:
1325 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1326 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1327 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1328 max_dist = max_dist_2x;
1329 break;
1330 case 4:
1331 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1332 radeon_emit(cs, sample_locs_4x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1333 radeon_emit(cs, sample_locs_4x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1334 max_dist = max_dist_4x;
1335 break;
1336 case 8:
1337 radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 2);
1338 radeon_emit(cs, sample_locs_8x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
1339 radeon_emit(cs, sample_locs_8x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */
1340 max_dist = max_dist_8x;
1341 break;
1342 }
1343 }
1344
1345 if (nr_samples > 1) {
1346 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1347 radeon_emit(cs, S_028C00_LAST_PIXEL(1) |
1348 S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
1349 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
1350 S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
1351 } else {
1352 radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
1353 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
1354 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
1355 }
1356 }
1357
r600_emit_framebuffer_state(struct r600_context * rctx,struct r600_atom * atom)1358 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1359 {
1360 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1361 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1362 unsigned nr_cbufs = state->nr_cbufs;
1363 struct r600_surface **cb = (struct r600_surface**)&state->cbufs[0];
1364 unsigned i, sbu = 0;
1365
1366 /* Colorbuffers. */
1367 radeon_set_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
1368 for (i = 0; i < nr_cbufs; i++) {
1369 radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
1370 }
1371 /* set CB_COLOR1_INFO for possible dual-src blending */
1372 if (rctx->framebuffer.dual_src_blend && i == 1 && cb[0]) {
1373 radeon_emit(cs, cb[0]->cb_color_info);
1374 i++;
1375 }
1376 for (; i < 8; i++) {
1377 radeon_emit(cs, 0);
1378 }
1379
1380 if (nr_cbufs) {
1381 for (i = 0; i < nr_cbufs; i++) {
1382 unsigned reloc;
1383
1384 if (!cb[i])
1385 continue;
1386
1387 /* COLOR_BASE */
1388 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
1389
1390 reloc = radeon_add_to_buffer_list(&rctx->b,
1391 &rctx->b.gfx,
1392 (struct r600_resource*)cb[i]->base.texture,
1393 RADEON_USAGE_READWRITE |
1394 (cb[i]->base.texture->nr_samples > 1 ?
1395 RADEON_PRIO_COLOR_BUFFER_MSAA :
1396 RADEON_PRIO_COLOR_BUFFER));
1397 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1398 radeon_emit(cs, reloc);
1399
1400 /* FMASK */
1401 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
1402
1403 reloc = radeon_add_to_buffer_list(&rctx->b,
1404 &rctx->b.gfx,
1405 cb[i]->cb_buffer_fmask,
1406 RADEON_USAGE_READWRITE |
1407 (cb[i]->base.texture->nr_samples > 1 ?
1408 RADEON_PRIO_COLOR_BUFFER_MSAA :
1409 RADEON_PRIO_COLOR_BUFFER));
1410 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1411 radeon_emit(cs, reloc);
1412
1413 /* CMASK */
1414 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
1415
1416 reloc = radeon_add_to_buffer_list(&rctx->b,
1417 &rctx->b.gfx,
1418 cb[i]->cb_buffer_cmask,
1419 RADEON_USAGE_READWRITE |
1420 (cb[i]->base.texture->nr_samples > 1 ?
1421 RADEON_PRIO_COLOR_BUFFER_MSAA :
1422 RADEON_PRIO_COLOR_BUFFER));
1423 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1424 radeon_emit(cs, reloc);
1425 }
1426
1427 radeon_set_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
1428 for (i = 0; i < nr_cbufs; i++) {
1429 radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
1430 }
1431
1432 radeon_set_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
1433 for (i = 0; i < nr_cbufs; i++) {
1434 radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
1435 }
1436
1437 radeon_set_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
1438 for (i = 0; i < nr_cbufs; i++) {
1439 radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
1440 }
1441
1442 sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
1443 }
1444
1445 /* SURFACE_BASE_UPDATE */
1446 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1447 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1448 radeon_emit(cs, sbu);
1449 sbu = 0;
1450 }
1451
1452 /* Zbuffer. */
1453 if (state->zsbuf) {
1454 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1455 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1456 &rctx->b.gfx,
1457 (struct r600_resource*)state->zsbuf->texture,
1458 RADEON_USAGE_READWRITE |
1459 (surf->base.texture->nr_samples > 1 ?
1460 RADEON_PRIO_DEPTH_BUFFER_MSAA :
1461 RADEON_PRIO_DEPTH_BUFFER));
1462
1463 radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
1464 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1465 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1466 radeon_set_context_reg_seq(cs, R_02800C_DB_DEPTH_BASE, 2);
1467 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1468 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1469
1470 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1471 radeon_emit(cs, reloc);
1472
1473 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1474
1475 sbu |= SURFACE_BASE_UPDATE_DEPTH;
1476 } else {
1477 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID));
1478 }
1479
1480 /* SURFACE_BASE_UPDATE */
1481 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1482 radeon_emit(cs, PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0));
1483 radeon_emit(cs, sbu);
1484 sbu = 0;
1485 }
1486
1487 /* Framebuffer dimensions. */
1488 radeon_set_context_reg_seq(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, 2);
1489 radeon_emit(cs, S_028240_TL_X(0) | S_028240_TL_Y(0) |
1490 S_028240_WINDOW_OFFSET_DISABLE(1)); /* R_028204_PA_SC_WINDOW_SCISSOR_TL */
1491 radeon_emit(cs, S_028244_BR_X(state->width) |
1492 S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */
1493
1494 if (rctx->framebuffer.is_msaa_resolve) {
1495 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1);
1496 } else {
1497 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1498 * will assure that the alpha-test will work even if there is
1499 * no colorbuffer bound. */
1500 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL,
1501 (1ull << MAX2(nr_cbufs, 1)) - 1);
1502 }
1503
1504 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1505 }
1506
r600_set_min_samples(struct pipe_context * ctx,unsigned min_samples)1507 static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
1508 {
1509 struct r600_context *rctx = (struct r600_context *)ctx;
1510
1511 if (rctx->ps_iter_samples == min_samples)
1512 return;
1513
1514 rctx->ps_iter_samples = min_samples;
1515 if (rctx->framebuffer.nr_samples > 1) {
1516 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1517 if (rctx->b.gfx_level == R600)
1518 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1519 }
1520 }
1521
r600_emit_cb_misc_state(struct r600_context * rctx,struct r600_atom * atom)1522 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1523 {
1524 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1525 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1526
1527 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1528 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1529 if (rctx->b.gfx_level == R600) {
1530 radeon_emit(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1531 radeon_emit(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1532 } else {
1533 radeon_emit(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1534 radeon_emit(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1535 }
1536 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1537 } else {
1538 unsigned fb_colormask = a->bound_cbufs_target_mask;
1539 unsigned ps_colormask = a->ps_color_export_mask;
1540 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1541
1542 radeon_set_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1543 radeon_emit(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1544 /* Always enable the first color output to make sure alpha-test works even without one. */
1545 radeon_emit(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1546 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1547 a->cb_color_control |
1548 S_028808_MULTIWRITE_ENABLE(multiwrite));
1549 }
1550 }
1551
r600_emit_db_state(struct r600_context * rctx,struct r600_atom * atom)1552 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1553 {
1554 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1555 struct r600_db_state *a = (struct r600_db_state*)atom;
1556
1557 if (a->rsurf && a->rsurf->db_htile_surface) {
1558 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
1559 unsigned reloc_idx;
1560
1561 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
1562 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface);
1563 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base);
1564 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
1565 RADEON_USAGE_READWRITE | RADEON_PRIO_SEPARATE_META);
1566 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1567 radeon_emit(cs, reloc_idx);
1568 } else {
1569 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, 0);
1570 }
1571 }
1572
r600_emit_db_misc_state(struct r600_context * rctx,struct r600_atom * atom)1573 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1574 {
1575 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1576 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1577 unsigned db_render_control = 0;
1578 unsigned db_render_override =
1579 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1580 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1581
1582 if (rctx->b.gfx_level >= R700) {
1583 switch (a->ps_conservative_z) {
1584 default: /* fall through */
1585 case FRAG_DEPTH_LAYOUT_ANY:
1586 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_ANY_Z);
1587 break;
1588 case FRAG_DEPTH_LAYOUT_GREATER:
1589 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_GREATER_THAN_Z);
1590 break;
1591 case FRAG_DEPTH_LAYOUT_LESS:
1592 db_render_control |= S_028D0C_CONSERVATIVE_Z_EXPORT(V_028D0C_EXPORT_LESS_THAN_Z);
1593 break;
1594 }
1595 }
1596
1597 if (rctx->b.num_occlusion_queries > 0 &&
1598 !a->occlusion_queries_disabled) {
1599 if (rctx->b.gfx_level >= R700) {
1600 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1601 }
1602 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1603 } else {
1604 db_render_control |= S_028D0C_ZPASS_INCREMENT_DISABLE(1);
1605 }
1606
1607 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1608 /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */
1609 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF);
1610 /* This is to fix a lockup when hyperz and alpha test are enabled at
1611 * the same time somehow GPU get confuse on which order to pick for
1612 * z test
1613 */
1614 if (rctx->alphatest_state.sx_alpha_test_control) {
1615 db_render_override |= S_028D10_FORCE_SHADER_Z_ORDER(1);
1616 }
1617 } else {
1618 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1619 }
1620 if (rctx->b.gfx_level == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1621 /* sample shading and hyperz causes lockups on R6xx chips */
1622 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1623 }
1624 if (a->flush_depthstencil_through_cb) {
1625 assert(a->copy_depth || a->copy_stencil);
1626
1627 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1628 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1629 S_028D0C_COPY_CENTROID(1) |
1630 S_028D0C_COPY_SAMPLE(a->copy_sample);
1631
1632 if (rctx->b.gfx_level == R600)
1633 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1634
1635 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1636 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1637 db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE);
1638 } else if (a->flush_depth_inplace || a->flush_stencil_inplace) {
1639 db_render_control |= S_028D0C_DEPTH_COMPRESS_DISABLE(a->flush_depth_inplace) |
1640 S_028D0C_STENCIL_COMPRESS_DISABLE(a->flush_stencil_inplace);
1641 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1642 }
1643 if (a->htile_clear) {
1644 db_render_control |= S_028D0C_DEPTH_CLEAR_ENABLE(1);
1645 }
1646
1647 /* RV770 workaround for a hang with 8x MSAA. */
1648 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1649 db_render_override |= S_028D10_MAX_TILES_IN_DTT(6);
1650 }
1651
1652 radeon_set_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1653 radeon_emit(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1654 radeon_emit(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1655 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
1656 }
1657
r600_emit_config_state(struct r600_context * rctx,struct r600_atom * atom)1658 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1659 {
1660 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1661 struct r600_config_state *a = (struct r600_config_state*)atom;
1662
1663 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
1664 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2);
1665 }
1666
r600_emit_vertex_buffers(struct r600_context * rctx,struct r600_atom * atom)1667 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1668 {
1669 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1670 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)rctx->vertex_fetch_shader.cso;
1671 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask & shader->buffer_mask;
1672
1673 while (dirty_mask) {
1674 struct pipe_vertex_buffer *vb;
1675 struct r600_resource *rbuffer;
1676 unsigned offset;
1677 unsigned buffer_index = u_bit_scan(&dirty_mask);
1678 unsigned stride = shader->strides[buffer_index];
1679
1680 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1681 rbuffer = (struct r600_resource*)vb->buffer.resource;
1682 assert(rbuffer);
1683
1684 offset = vb->buffer_offset;
1685
1686 /* fetch resources start at index 320 (OFFSET_FS) */
1687 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1688 radeon_emit(cs, (R600_FETCH_CONSTANTS_OFFSET_FS + buffer_index) * 7);
1689 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1690 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1691 radeon_emit(cs, /* RESOURCEi_WORD2 */
1692 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1693 S_038008_STRIDE(stride));
1694 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1695 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1696 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1697 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1698
1699 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1700 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1701 RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER));
1702 }
1703 }
1704
r600_emit_constant_buffers(struct r600_context * rctx,struct r600_constbuf_state * state,unsigned buffer_id_base,unsigned reg_alu_constbuf_size,unsigned reg_alu_const_cache)1705 static void r600_emit_constant_buffers(struct r600_context *rctx,
1706 struct r600_constbuf_state *state,
1707 unsigned buffer_id_base,
1708 unsigned reg_alu_constbuf_size,
1709 unsigned reg_alu_const_cache)
1710 {
1711 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1712 uint32_t dirty_mask = state->dirty_mask;
1713
1714 while (dirty_mask) {
1715 struct pipe_constant_buffer *cb;
1716 struct r600_resource *rbuffer;
1717 unsigned offset;
1718 unsigned buffer_index = ffs(dirty_mask) - 1;
1719 unsigned gs_ring_buffer = (buffer_index == R600_GS_RING_CONST_BUFFER);
1720 cb = &state->cb[buffer_index];
1721 rbuffer = (struct r600_resource*)cb->buffer;
1722 assert(rbuffer);
1723
1724 offset = cb->buffer_offset;
1725
1726 if (!gs_ring_buffer) {
1727 assert(buffer_index < R600_MAX_ALU_CONST_BUFFERS);
1728 radeon_set_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1729 DIV_ROUND_UP(cb->buffer_size, 256));
1730 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1731 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1732 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1733 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER));
1734 }
1735
1736 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1737 radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
1738 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1739 radeon_emit(cs, cb->buffer_size - 1); /* RESOURCEi_WORD1 */
1740 radeon_emit(cs, /* RESOURCEi_WORD2 */
1741 S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : r600_endian_swap(32)) |
1742 S_038008_STRIDE(gs_ring_buffer ? 4 : 16));
1743 radeon_emit(cs, 0); /* RESOURCEi_WORD3 */
1744 radeon_emit(cs, 0); /* RESOURCEi_WORD4 */
1745 radeon_emit(cs, 0); /* RESOURCEi_WORD5 */
1746 radeon_emit(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1747
1748 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1749 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1750 RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER));
1751
1752 dirty_mask &= ~(1 << buffer_index);
1753 }
1754 state->dirty_mask = 0;
1755 }
1756
r600_emit_vs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1757 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1758 {
1759 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1760 R600_FETCH_CONSTANTS_OFFSET_VS,
1761 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1762 R_028980_ALU_CONST_CACHE_VS_0);
1763 }
1764
r600_emit_gs_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1765 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1766 {
1767 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1768 R600_FETCH_CONSTANTS_OFFSET_GS,
1769 R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0,
1770 R_0289C0_ALU_CONST_CACHE_GS_0);
1771 }
1772
r600_emit_ps_constant_buffers(struct r600_context * rctx,struct r600_atom * atom)1773 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1774 {
1775 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1776 R600_FETCH_CONSTANTS_OFFSET_PS,
1777 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1778 R_028940_ALU_CONST_CACHE_PS_0);
1779 }
1780
r600_emit_sampler_views(struct r600_context * rctx,struct r600_samplerview_state * state,unsigned resource_id_base)1781 static void r600_emit_sampler_views(struct r600_context *rctx,
1782 struct r600_samplerview_state *state,
1783 unsigned resource_id_base)
1784 {
1785 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1786 uint32_t dirty_mask = state->dirty_mask;
1787
1788 while (dirty_mask) {
1789 struct r600_pipe_sampler_view *rview;
1790 unsigned resource_index = u_bit_scan(&dirty_mask);
1791 unsigned reloc;
1792
1793 rview = state->views[resource_index];
1794 assert(rview);
1795
1796 radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1797 radeon_emit(cs, (resource_id_base + resource_index) * 7);
1798 radeon_emit_array(cs, rview->tex_resource_words, 7);
1799
1800 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1801 RADEON_USAGE_READ |
1802 r600_get_sampler_view_priority(rview->tex_resource));
1803 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1804 radeon_emit(cs, reloc);
1805 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1806 radeon_emit(cs, reloc);
1807 }
1808 state->dirty_mask = 0;
1809 }
1810
1811
r600_emit_vs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)1812 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1813 {
1814 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1815 }
1816
r600_emit_gs_sampler_views(struct r600_context * rctx,struct r600_atom * atom)1817 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1818 {
1819 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1820 }
1821
r600_emit_ps_sampler_views(struct r600_context * rctx,struct r600_atom * atom)1822 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1823 {
1824 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1825 }
1826
r600_emit_sampler_states(struct r600_context * rctx,struct r600_textures_info * texinfo,unsigned resource_id_base,unsigned border_color_reg)1827 static void r600_emit_sampler_states(struct r600_context *rctx,
1828 struct r600_textures_info *texinfo,
1829 unsigned resource_id_base,
1830 unsigned border_color_reg)
1831 {
1832 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1833 uint32_t dirty_mask = texinfo->states.dirty_mask;
1834
1835 while (dirty_mask) {
1836 struct r600_pipe_sampler_state *rstate;
1837 struct r600_pipe_sampler_view *rview;
1838 unsigned i = u_bit_scan(&dirty_mask);
1839
1840 rstate = texinfo->states.states[i];
1841 assert(rstate);
1842 rview = texinfo->views.views[i];
1843
1844 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1845 * filtering between layers.
1846 */
1847 enum pipe_texture_target target = PIPE_BUFFER;
1848 if (rview)
1849 target = rview->base.texture->target;
1850
1851 /* If seamless cube map is set, set the CAMP_(X|Y|Z) to
1852 * SQ_TEX_WRAP which seems to trigger properly ignoring the
1853 * texture wrap mode */
1854 if (target == PIPE_TEXTURE_CUBE ||
1855 target == PIPE_TEXTURE_CUBE_ARRAY) {
1856 if (rstate->seamless_cube_map){
1857 uint32_t mask = ~(S_03C000_CLAMP_X(7) |
1858 S_03C000_CLAMP_Y(7) |
1859 S_03C000_CLAMP_Z(7));
1860 rstate->tex_sampler_words[0] &= mask;
1861 }
1862 }
1863
1864 if (target == PIPE_TEXTURE_1D_ARRAY ||
1865 target == PIPE_TEXTURE_2D_ARRAY) {
1866 rstate->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1867 texinfo->is_array_sampler[i] = true;
1868 } else {
1869 rstate->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1870 texinfo->is_array_sampler[i] = false;
1871 }
1872
1873 radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1874 radeon_emit(cs, (resource_id_base + i) * 3);
1875 radeon_emit_array(cs, rstate->tex_sampler_words, 3);
1876
1877 if (rstate->border_color_use) {
1878 unsigned offset;
1879
1880 offset = border_color_reg;
1881 offset += i * 16;
1882 radeon_set_config_reg_seq(cs, offset, 4);
1883 radeon_emit_array(cs, rstate->border_color.ui, 4);
1884 }
1885 }
1886 texinfo->states.dirty_mask = 0;
1887 }
1888
r600_emit_vs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)1889 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1890 {
1891 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1892 }
1893
r600_emit_gs_sampler_states(struct r600_context * rctx,struct r600_atom * atom)1894 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1895 {
1896 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1897 }
1898
r600_emit_ps_sampler_states(struct r600_context * rctx,struct r600_atom * atom)1899 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1900 {
1901 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1902 }
1903
r600_emit_seamless_cube_map(struct r600_context * rctx,struct r600_atom * atom)1904 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1905 {
1906 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1907 unsigned tmp;
1908
1909 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1910 S_009508_SYNC_GRADIENT(1) |
1911 S_009508_SYNC_WALKER(1) |
1912 S_009508_SYNC_ALIGNER(1);
1913 if (!rctx->seamless_cube_map.enabled) {
1914 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1915 }
1916 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1917 }
1918
r600_emit_sample_mask(struct r600_context * rctx,struct r600_atom * a)1919 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1920 {
1921 struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1922 uint8_t mask = s->sample_mask;
1923
1924 radeon_set_context_reg(&rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1925 mask | (mask << 8) | (mask << 16) | (mask << 24));
1926 }
1927
r600_emit_vertex_fetch_shader(struct r600_context * rctx,struct r600_atom * a)1928 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1929 {
1930 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1931 struct r600_cso_state *state = (struct r600_cso_state*)a;
1932 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
1933
1934 if (!shader)
1935 return;
1936
1937 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);
1938 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1939 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1940 RADEON_USAGE_READ |
1941 RADEON_PRIO_SHADER_BINARY));
1942 }
1943
r600_emit_shader_stages(struct r600_context * rctx,struct r600_atom * a)1944 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1945 {
1946 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1947 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
1948
1949 uint32_t v2 = 0, primid = 0;
1950
1951 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1952 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
1953 primid = 1;
1954 }
1955
1956 if (state->geom_enable) {
1957 uint32_t cut_val;
1958
1959 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1960 cut_val = V_028A40_GS_CUT_128;
1961 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1962 cut_val = V_028A40_GS_CUT_256;
1963 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1964 cut_val = V_028A40_GS_CUT_512;
1965 else
1966 cut_val = V_028A40_GS_CUT_1024;
1967
1968 v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
1969 S_028A40_CUT_MODE(cut_val);
1970
1971 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1972 primid = 1;
1973 }
1974
1975 radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2);
1976 radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid);
1977 }
1978
r600_emit_gs_rings(struct r600_context * rctx,struct r600_atom * a)1979 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1980 {
1981 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1982 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
1983 struct r600_resource *rbuffer;
1984
1985 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1986 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1987 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1988
1989 if (state->enable) {
1990 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
1991 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0);
1992 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1993 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1994 RADEON_USAGE_READWRITE |
1995 RADEON_PRIO_SHADER_RINGS));
1996 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE,
1997 state->esgs_ring.buffer_size >> 8);
1998
1999 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2000 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0);
2001 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2002 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2003 RADEON_USAGE_READWRITE |
2004 RADEON_PRIO_SHADER_RINGS));
2005 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE,
2006 state->gsvs_ring.buffer_size >> 8);
2007 } else {
2008 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0);
2009 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0);
2010 }
2011
2012 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2013 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2014 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
2015 }
2016
2017 /* Adjust GPR allocation on R6xx/R7xx */
r600_adjust_gprs(struct r600_context * rctx)2018 bool r600_adjust_gprs(struct r600_context *rctx)
2019 {
2020 unsigned num_gprs[R600_NUM_HW_STAGES];
2021 unsigned new_gprs[R600_NUM_HW_STAGES];
2022 unsigned cur_gprs[R600_NUM_HW_STAGES];
2023 unsigned def_gprs[R600_NUM_HW_STAGES];
2024 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2025 unsigned max_gprs;
2026 unsigned tmp, tmp2;
2027 unsigned i;
2028 bool need_recalc = false, use_default = true;
2029
2030 /* hardware will reserve twice num_clause_temp_gprs */
2031 max_gprs = def_num_clause_temp_gprs * 2;
2032 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2033 def_gprs[i] = rctx->default_gprs[i];
2034 max_gprs += def_gprs[i];
2035 }
2036
2037 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2038 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2039 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2040 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2041
2042 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2043 if (rctx->gs_shader) {
2044 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2045 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2046 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2047 } else {
2048 num_gprs[R600_HW_STAGE_ES] = 0;
2049 num_gprs[R600_HW_STAGE_GS] = 0;
2050 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2051 }
2052
2053 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2054 new_gprs[i] = num_gprs[i];
2055 if (new_gprs[i] > cur_gprs[i])
2056 need_recalc = true;
2057 if (new_gprs[i] > def_gprs[i])
2058 use_default = false;
2059 }
2060
2061 /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must <= to max_gprs */
2062 if (!need_recalc)
2063 return true;
2064
2065 /* try to use switch back to default */
2066 if (!use_default) {
2067 /* always privilege vs stage so that at worst we have the
2068 * pixel stage producing wrong output (not the vertex
2069 * stage) */
2070 new_gprs[R600_HW_STAGE_PS] = max_gprs - def_num_clause_temp_gprs * 2;
2071 for (i = R600_HW_STAGE_VS; i < R600_NUM_HW_STAGES; i++)
2072 new_gprs[R600_HW_STAGE_PS] -= new_gprs[i];
2073 } else {
2074 for (i = 0; i < R600_NUM_HW_STAGES; i++)
2075 new_gprs[i] = def_gprs[i];
2076 }
2077
2078 /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value <=
2079 * SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU will lockup
2080 * Also if a shader use more gpr than SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS
2081 * it will lockup. So in this case just discard the draw command
2082 * and don't change the current gprs repartitions.
2083 */
2084 for (i = 0; i < R600_NUM_HW_STAGES; i++) {
2085 if (num_gprs[i] > new_gprs[i]) {
2086 R600_ERR("shaders require too many register (%d + %d + %d + %d) "
2087 "for a combined maximum of %d\n",
2088 num_gprs[R600_HW_STAGE_PS], num_gprs[R600_HW_STAGE_VS], num_gprs[R600_HW_STAGE_ES], num_gprs[R600_HW_STAGE_GS], max_gprs);
2089 return false;
2090 }
2091 }
2092
2093 /* in some case we endup recomputing the current value */
2094 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2095 S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) |
2096 S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs);
2097
2098 tmp2 = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
2099 S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]);
2100 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2101 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2102 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2103 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2104 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2105 }
2106 return true;
2107 }
2108
r600_init_atom_start_cs(struct r600_context * rctx)2109 void r600_init_atom_start_cs(struct r600_context *rctx)
2110 {
2111 int ps_prio;
2112 int vs_prio;
2113 int gs_prio;
2114 int es_prio;
2115 int num_ps_gprs;
2116 int num_vs_gprs;
2117 int num_gs_gprs;
2118 int num_es_gprs;
2119 int num_temp_gprs;
2120 int num_ps_threads;
2121 int num_vs_threads;
2122 int num_gs_threads;
2123 int num_es_threads;
2124 int num_ps_stack_entries;
2125 int num_vs_stack_entries;
2126 int num_gs_stack_entries;
2127 int num_es_stack_entries;
2128 enum radeon_family family;
2129 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2130 uint32_t tmp, i;
2131
2132 r600_init_command_buffer(cb, 256);
2133
2134 /* R6xx requires this packet at the start of each command buffer */
2135 if (rctx->b.gfx_level == R600) {
2136 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2137 r600_store_value(cb, 0);
2138 }
2139 /* All asics require this one */
2140 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2141 r600_store_value(cb, 0x80000000);
2142 r600_store_value(cb, 0x80000000);
2143
2144 /* We're setting config registers here. */
2145 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2146 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2147
2148 /* This enables pipeline stat & streamout queries.
2149 * They are only disabled by blits.
2150 */
2151 r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
2152 r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0));
2153
2154 family = rctx->b.family;
2155 ps_prio = 0;
2156 vs_prio = 1;
2157 gs_prio = 2;
2158 es_prio = 3;
2159 switch (family) {
2160 case CHIP_R600:
2161 num_ps_gprs = 192;
2162 num_vs_gprs = 56;
2163 num_temp_gprs = 4;
2164 num_gs_gprs = 0;
2165 num_es_gprs = 0;
2166 num_ps_threads = 136;
2167 num_vs_threads = 48;
2168 num_gs_threads = 4;
2169 num_es_threads = 4;
2170 num_ps_stack_entries = 128;
2171 num_vs_stack_entries = 128;
2172 num_gs_stack_entries = 0;
2173 num_es_stack_entries = 0;
2174 break;
2175 case CHIP_RV630:
2176 case CHIP_RV635:
2177 num_ps_gprs = 84;
2178 num_vs_gprs = 36;
2179 num_temp_gprs = 4;
2180 num_gs_gprs = 0;
2181 num_es_gprs = 0;
2182 num_ps_threads = 144;
2183 num_vs_threads = 40;
2184 num_gs_threads = 4;
2185 num_es_threads = 4;
2186 num_ps_stack_entries = 40;
2187 num_vs_stack_entries = 40;
2188 num_gs_stack_entries = 32;
2189 num_es_stack_entries = 16;
2190 break;
2191 case CHIP_RV610:
2192 case CHIP_RV620:
2193 case CHIP_RS780:
2194 case CHIP_RS880:
2195 default:
2196 num_ps_gprs = 84;
2197 num_vs_gprs = 36;
2198 num_temp_gprs = 4;
2199 num_gs_gprs = 0;
2200 num_es_gprs = 0;
2201 /* use limits 40 VS and at least 16 ES/GS */
2202 num_ps_threads = 120;
2203 num_vs_threads = 40;
2204 num_gs_threads = 16;
2205 num_es_threads = 16;
2206 num_ps_stack_entries = 40;
2207 num_vs_stack_entries = 40;
2208 num_gs_stack_entries = 32;
2209 num_es_stack_entries = 16;
2210 break;
2211 case CHIP_RV670:
2212 num_ps_gprs = 144;
2213 num_vs_gprs = 40;
2214 num_temp_gprs = 4;
2215 num_gs_gprs = 0;
2216 num_es_gprs = 0;
2217 num_ps_threads = 136;
2218 num_vs_threads = 48;
2219 num_gs_threads = 4;
2220 num_es_threads = 4;
2221 num_ps_stack_entries = 40;
2222 num_vs_stack_entries = 40;
2223 num_gs_stack_entries = 32;
2224 num_es_stack_entries = 16;
2225 break;
2226 case CHIP_RV770:
2227 num_ps_gprs = 130;
2228 num_vs_gprs = 56;
2229 num_temp_gprs = 4;
2230 num_gs_gprs = 31;
2231 num_es_gprs = 31;
2232 num_ps_threads = 180;
2233 num_vs_threads = 60;
2234 num_gs_threads = 4;
2235 num_es_threads = 4;
2236 num_ps_stack_entries = 128;
2237 num_vs_stack_entries = 128;
2238 num_gs_stack_entries = 128;
2239 num_es_stack_entries = 128;
2240 break;
2241 case CHIP_RV730:
2242 case CHIP_RV740:
2243 num_ps_gprs = 84;
2244 num_vs_gprs = 36;
2245 num_temp_gprs = 4;
2246 num_gs_gprs = 0;
2247 num_es_gprs = 0;
2248 num_ps_threads = 180;
2249 num_vs_threads = 60;
2250 num_gs_threads = 4;
2251 num_es_threads = 4;
2252 num_ps_stack_entries = 128;
2253 num_vs_stack_entries = 128;
2254 num_gs_stack_entries = 0;
2255 num_es_stack_entries = 0;
2256 break;
2257 case CHIP_RV710:
2258 num_ps_gprs = 192;
2259 num_vs_gprs = 56;
2260 num_temp_gprs = 4;
2261 num_gs_gprs = 0;
2262 num_es_gprs = 0;
2263 num_ps_threads = 136;
2264 num_vs_threads = 48;
2265 num_gs_threads = 4;
2266 num_es_threads = 4;
2267 num_ps_stack_entries = 128;
2268 num_vs_stack_entries = 128;
2269 num_gs_stack_entries = 0;
2270 num_es_stack_entries = 0;
2271 break;
2272 }
2273
2274 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2275 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2276 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2277 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2278
2279 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2280
2281 /* SQ_CONFIG */
2282 tmp = 0;
2283 switch (family) {
2284 case CHIP_RV610:
2285 case CHIP_RV620:
2286 case CHIP_RS780:
2287 case CHIP_RS880:
2288 case CHIP_RV710:
2289 break;
2290 default:
2291 tmp |= S_008C00_VC_ENABLE(1);
2292 break;
2293 }
2294 tmp |= S_008C00_DX9_CONSTS(0);
2295 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2296 tmp |= S_008C00_PS_PRIO(ps_prio);
2297 tmp |= S_008C00_VS_PRIO(vs_prio);
2298 tmp |= S_008C00_GS_PRIO(gs_prio);
2299 tmp |= S_008C00_ES_PRIO(es_prio);
2300 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2301
2302 /* SQ_GPR_RESOURCE_MGMT_2 */
2303 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2304 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2305 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2306 r600_store_value(cb, tmp);
2307
2308 /* SQ_THREAD_RESOURCE_MGMT */
2309 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2310 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2311 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2312 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2313 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2314
2315 /* SQ_STACK_RESOURCE_MGMT_1 */
2316 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2317 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2318 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2319
2320 /* SQ_STACK_RESOURCE_MGMT_2 */
2321 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2322 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2323 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2324
2325 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2326
2327 if (rctx->b.gfx_level >= R700) {
2328 r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
2329 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2330 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2331 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2332 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2333 } else {
2334 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2335 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2336 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2337 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2338 }
2339 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2340 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2341 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2342 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2343 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2344 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2345 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2346 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2347 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2348 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2349
2350 /* to avoid GPU doing any preloading of constant from random address */
2351 r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16);
2352 for (i = 0; i < 16; i++)
2353 r600_store_value(cb, 0);
2354
2355 r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16);
2356 for (i = 0; i < 16; i++)
2357 r600_store_value(cb, 0);
2358
2359 r600_store_context_reg_seq(cb, R_0281C0_ALU_CONST_BUFFER_SIZE_GS_0, 16);
2360 for (i = 0; i < 16; i++)
2361 r600_store_value(cb, 0);
2362
2363 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2364 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2365 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2366 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2367 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2368 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2369 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2370 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2371 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2372 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2373 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2374 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2375 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2376 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2377
2378 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2379 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2380 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2381
2382 r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2383 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2384 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2385
2386 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2387
2388 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2389
2390 r600_store_context_reg(cb, R_028028_DB_STENCIL_CLEAR, 0);
2391
2392 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2393 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2394 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2395 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2396
2397 r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3);
2398 r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */
2399 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2400 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2401
2402 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2403 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2404
2405 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2406 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2407
2408 if (rctx->b.gfx_level >= R700) {
2409 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2410 }
2411
2412 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2413 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */
2414 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */
2415 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */
2416 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2417
2418 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2419 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2420 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2421
2422 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2423 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2424 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2425
2426 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 5);
2427 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2428 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2429 r600_store_value(cb, 0); /* R_0288D4_SQ_PGM_CF_OFFSET_GS */
2430 r600_store_value(cb, 0); /* R_0288D8_SQ_PGM_CF_OFFSET_ES */
2431 r600_store_value(cb, 0); /* R_0288DC_SQ_PGM_CF_OFFSET_FS */
2432
2433 r600_store_context_reg(cb, R_0288E0_SQ_VTX_SEMANTIC_CLEAR, ~0);
2434
2435 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2436 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2437 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2438
2439 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2440
2441 if (rctx->b.gfx_level == R700)
2442 r600_store_context_reg(cb, R_028350_SX_MISC, 0);
2443 if (rctx->b.gfx_level == R700 && rctx->screen->b.has_streamout)
2444 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2445
2446 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2447 if (rctx->screen->b.has_streamout) {
2448 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2449 }
2450
2451 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2452 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2453 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (64 * 4), 0x1000FFF);
2454 }
2455
r600_update_ps_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2456 void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2457 {
2458 struct r600_context *rctx = (struct r600_context *)ctx;
2459 struct r600_command_buffer *cb = &shader->command_buffer;
2460 struct r600_shader *rshader = &shader->shader;
2461 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2462 int pos_index = -1, face_index = -1, fixed_pt_position_index = -1;
2463 unsigned tmp, sid, ufi = 0;
2464 int need_linear = 0;
2465 unsigned z_export = 0, stencil_export = 0, mask_export = 0;
2466
2467 /* Pull any state we use out of rctx. Make sure that any additional
2468 * state added to this list is also checked in the caller in
2469 * r600_update_derived_state().
2470 */
2471 bool sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2472 bool flatshade = rctx->rasterizer ? rctx->rasterizer->flatshade : 0;
2473 bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0;
2474
2475 if (!cb->buf) {
2476 r600_init_command_buffer(cb, 64);
2477 } else {
2478 cb->num_dw = 0;
2479 }
2480
2481 r600_store_context_reg_seq(cb, R_028644_SPI_PS_INPUT_CNTL_0, rshader->ninput);
2482 for (i = 0; i < rshader->ninput; i++) {
2483 const gl_varying_slot varying_slot = rshader->input[i].varying_slot;
2484
2485 if (varying_slot == VARYING_SLOT_POS)
2486 pos_index = i;
2487 else if (varying_slot == VARYING_SLOT_FACE) {
2488 if (face_index == -1)
2489 face_index = i;
2490 }
2491 else if (rshader->input[i].system_value == SYSTEM_VALUE_SAMPLE_ID)
2492 fixed_pt_position_index = i;
2493
2494 sid = rshader->input[i].spi_sid;
2495
2496 tmp = S_028644_SEMANTIC(sid);
2497
2498 /* D3D 9 behaviour. GL is undefined */
2499 if (varying_slot == VARYING_SLOT_COL0)
2500 tmp |= S_028644_DEFAULT_VAL(3);
2501
2502 if (varying_slot == VARYING_SLOT_POS ||
2503 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2504 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && flatshade))
2505 tmp |= S_028644_FLAT_SHADE(1);
2506
2507 if (varying_slot == VARYING_SLOT_PNTC ||
2508 (varying_slot >= VARYING_SLOT_TEX0 && varying_slot <= VARYING_SLOT_TEX7 &&
2509 (sprite_coord_enable & (1 << ((int)varying_slot - (int)VARYING_SLOT_TEX0))))) {
2510 tmp |= S_028644_PT_SPRITE_TEX(1);
2511 }
2512
2513 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID)
2514 tmp |= S_028644_SEL_CENTROID(1);
2515
2516 if (rshader->input[i].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE)
2517 tmp |= S_028644_SEL_SAMPLE(1);
2518
2519 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2520 need_linear = 1;
2521 tmp |= S_028644_SEL_LINEAR(1);
2522 }
2523
2524 r600_store_value(cb, tmp);
2525 }
2526
2527 db_shader_control = 0;
2528 exports_ps = 0;
2529 for (i = 0; i < rshader->noutput; i++) {
2530 switch (rshader->output[i].frag_result) {
2531 case FRAG_RESULT_DEPTH:
2532 z_export = 1;
2533 exports_ps |= 1;
2534 break;
2535 case FRAG_RESULT_STENCIL:
2536 stencil_export = 1;
2537 exports_ps |= 1;
2538 break;
2539 case FRAG_RESULT_SAMPLE_MASK:
2540 if (msaa)
2541 mask_export = 1;
2542 exports_ps |= 1;
2543 break;
2544 default:
2545 break;
2546 }
2547 }
2548 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2549 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2550 db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(mask_export);
2551 if (rshader->uses_kill)
2552 db_shader_control |= S_02880C_KILL_ENABLE(1);
2553
2554 num_cout = rshader->nr_ps_color_exports;
2555 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2556 if (!exports_ps) {
2557 /* always at least export 1 component per pixel */
2558 exports_ps = 2;
2559 }
2560
2561 shader->nr_ps_color_outputs = num_cout;
2562 shader->ps_color_export_mask = rshader->ps_color_export_mask;
2563
2564 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2565 S_0286CC_PERSP_GRADIENT_ENA(1)|
2566 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2567 spi_input_z = 0;
2568 if (pos_index != -1) {
2569 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2570 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_CENTROID) |
2571 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2572 S_0286CC_BARYC_SAMPLE_CNTL(1)) |
2573 S_0286CC_POSITION_SAMPLE(rshader->input[pos_index].interpolate_location == TGSI_INTERPOLATE_LOC_SAMPLE);
2574 spi_input_z |= S_0286D8_PROVIDE_Z_TO_SPI(1);
2575 }
2576
2577 spi_ps_in_control_1 = 0;
2578 if (face_index != -1) {
2579 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2580 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2581 }
2582 if (fixed_pt_position_index != -1) {
2583 spi_ps_in_control_1 |= S_0286D0_FIXED_PT_POSITION_ENA(1) |
2584 S_0286D0_FIXED_PT_POSITION_ADDR(rshader->input[fixed_pt_position_index].gpr);
2585 }
2586
2587 /* HW bug in original R600 */
2588 if (rctx->b.family == CHIP_R600)
2589 ufi = 1;
2590
2591 r600_store_context_reg_seq(cb, R_0286CC_SPI_PS_IN_CONTROL_0, 2);
2592 r600_store_value(cb, spi_ps_in_control_0); /* R_0286CC_SPI_PS_IN_CONTROL_0 */
2593 r600_store_value(cb, spi_ps_in_control_1); /* R_0286D0_SPI_PS_IN_CONTROL_1 */
2594
2595 r600_store_context_reg(cb, R_0286D8_SPI_INPUT_Z, spi_input_z);
2596
2597 r600_store_context_reg_seq(cb, R_028850_SQ_PGM_RESOURCES_PS, 2);
2598 r600_store_value(cb, /* R_028850_SQ_PGM_RESOURCES_PS*/
2599 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2600 /*
2601 * docs are misleading about the dx10_clamp bit. This only affects
2602 * instructions using CLAMP dst modifier, in which case they will
2603 * return 0 with this set for a NaN (otherwise NaN).
2604 */
2605 S_028850_DX10_CLAMP(1) |
2606 S_028850_STACK_SIZE(rshader->bc.nstack) |
2607 S_028850_UNCACHED_FIRST_INST(ufi));
2608 r600_store_value(cb, exports_ps); /* R_028854_SQ_PGM_EXPORTS_PS */
2609
2610 r600_store_context_reg(cb, R_028840_SQ_PGM_START_PS, 0);
2611 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2612
2613 /* only set some bits here, the other bits are set in the dsa state */
2614 shader->db_shader_control = db_shader_control;
2615 shader->ps_depth_export = z_export | stencil_export | mask_export;
2616
2617 shader->sprite_coord_enable = sprite_coord_enable;
2618 shader->flatshade = flatshade;
2619 shader->msaa = msaa;
2620 }
2621
r600_update_vs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2622 void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2623 {
2624 struct r600_command_buffer *cb = &shader->command_buffer;
2625 struct r600_shader *rshader = &shader->shader;
2626 unsigned spi_vs_out_id[10] = {};
2627 unsigned i;
2628
2629 for (i = 0; i < rshader->noutput; i++) {
2630 const int param = rshader->output[i].export_param;
2631 if (param < 0)
2632 continue;
2633 unsigned *const param_spi_vs_out_id = &spi_vs_out_id[param / 4];
2634 const unsigned param_shift = (param & 3) * 8;
2635 assert(!(*param_spi_vs_out_id & (0xFFu << param_shift)));
2636 *param_spi_vs_out_id |= (unsigned)rshader->output[i].spi_sid << param_shift;
2637 }
2638
2639 r600_init_command_buffer(cb, 32);
2640
2641 r600_store_context_reg_seq(cb, R_028614_SPI_VS_OUT_ID_0, 10);
2642 for (i = 0; i < 10; i++) {
2643 r600_store_value(cb, spi_vs_out_id[i]);
2644 }
2645
2646 r600_store_context_reg(cb, R_0286C4_SPI_VS_OUT_CONFIG,
2647 S_0286C4_VS_EXPORT_COUNT(rshader->highest_export_param));
2648 r600_store_context_reg(cb, R_028868_SQ_PGM_RESOURCES_VS,
2649 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2650 S_028868_DX10_CLAMP(1) |
2651 S_028868_STACK_SIZE(rshader->bc.nstack));
2652 if (rshader->vs_position_window_space) {
2653 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2654 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
2655 } else {
2656 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL,
2657 S_028818_VTX_W0_FMT(1) |
2658 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
2659 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
2660 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
2661
2662 }
2663 r600_store_context_reg(cb, R_028858_SQ_PGM_START_VS, 0);
2664 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2665
2666 shader->pa_cl_vs_out_cntl =
2667 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2668 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2669 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2670 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size) |
2671 S_02881C_USE_VTX_EDGE_FLAG(rshader->vs_out_edgeflag) |
2672 S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer) |
2673 S_02881C_USE_VTX_VIEWPORT_INDX(rshader->vs_out_viewport);
2674 }
2675
2676 #define RV610_GSVS_ALIGN 32
2677 #define R600_GSVS_ALIGN 16
2678
r600_update_gs_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2679 void r600_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2680 {
2681 struct r600_context *rctx = (struct r600_context *)ctx;
2682 struct r600_command_buffer *cb = &shader->command_buffer;
2683 struct r600_shader *rshader = &shader->shader;
2684 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
2685 unsigned gsvs_itemsize =
2686 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2;
2687
2688 /* some r600s needs gsvs itemsize aligned to cacheline size
2689 this was fixed in rs780 and above. */
2690 switch (rctx->b.family) {
2691 case CHIP_RV610:
2692 gsvs_itemsize = align(gsvs_itemsize, RV610_GSVS_ALIGN);
2693 break;
2694 case CHIP_R600:
2695 case CHIP_RV630:
2696 case CHIP_RV670:
2697 case CHIP_RV620:
2698 case CHIP_RV635:
2699 gsvs_itemsize = align(gsvs_itemsize, R600_GSVS_ALIGN);
2700 break;
2701 default:
2702 break;
2703 }
2704
2705 r600_init_command_buffer(cb, 64);
2706
2707 /* VGT_GS_MODE is written by r600_emit_shader_stages */
2708 r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1);
2709
2710 if (rctx->b.gfx_level >= R700) {
2711 r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT,
2712 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
2713 }
2714 r600_store_context_reg(cb, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
2715 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
2716
2717 r600_store_context_reg(cb, R_0288C8_SQ_GS_VERT_ITEMSIZE,
2718 cp_shader->ring_item_sizes[0] >> 2);
2719
2720 r600_store_context_reg(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE,
2721 (rshader->ring_item_sizes[0]) >> 2);
2722
2723 r600_store_context_reg(cb, R_0288AC_SQ_GSVS_RING_ITEMSIZE,
2724 gsvs_itemsize);
2725
2726 /* FIXME calculate these values somehow ??? */
2727 r600_store_config_reg_seq(cb, R_0088C8_VGT_GS_PER_ES, 2);
2728 r600_store_value(cb, 0x80); /* GS_PER_ES */
2729 r600_store_value(cb, 0x100); /* ES_PER_GS */
2730 r600_store_config_reg_seq(cb, R_0088E8_VGT_GS_PER_VS, 1);
2731 r600_store_value(cb, 0x2); /* GS_PER_VS */
2732
2733 r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_GS,
2734 S_02887C_NUM_GPRS(rshader->bc.ngpr) |
2735 S_02887C_DX10_CLAMP(1) |
2736 S_02887C_STACK_SIZE(rshader->bc.nstack));
2737 r600_store_context_reg(cb, R_02886C_SQ_PGM_START_GS, 0);
2738 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2739 }
2740
r600_update_es_state(struct pipe_context * ctx,struct r600_pipe_shader * shader)2741 void r600_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2742 {
2743 struct r600_command_buffer *cb = &shader->command_buffer;
2744 struct r600_shader *rshader = &shader->shader;
2745
2746 r600_init_command_buffer(cb, 32);
2747
2748 r600_store_context_reg(cb, R_028890_SQ_PGM_RESOURCES_ES,
2749 S_028890_NUM_GPRS(rshader->bc.ngpr) |
2750 S_028890_DX10_CLAMP(1) |
2751 S_028890_STACK_SIZE(rshader->bc.nstack));
2752 r600_store_context_reg(cb, R_028880_SQ_PGM_START_ES, 0);
2753 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
2754 }
2755
2756
r600_create_resolve_blend(struct r600_context * rctx)2757 void *r600_create_resolve_blend(struct r600_context *rctx)
2758 {
2759 struct pipe_blend_state blend;
2760 unsigned i;
2761
2762 memset(&blend, 0, sizeof(blend));
2763 blend.independent_blend_enable = true;
2764 for (i = 0; i < 2; i++) {
2765 blend.rt[i].colormask = 0xf;
2766 blend.rt[i].blend_enable = 1;
2767 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2768 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2769 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2770 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2771 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2772 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2773 }
2774 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2775 }
2776
r700_create_resolve_blend(struct r600_context * rctx)2777 void *r700_create_resolve_blend(struct r600_context *rctx)
2778 {
2779 struct pipe_blend_state blend;
2780
2781 memset(&blend, 0, sizeof(blend));
2782 blend.independent_blend_enable = true;
2783 blend.rt[0].colormask = 0xf;
2784 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2785 }
2786
r600_create_decompress_blend(struct r600_context * rctx)2787 void *r600_create_decompress_blend(struct r600_context *rctx)
2788 {
2789 struct pipe_blend_state blend;
2790
2791 memset(&blend, 0, sizeof(blend));
2792 blend.independent_blend_enable = true;
2793 blend.rt[0].colormask = 0xf;
2794 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2795 }
2796
r600_create_db_flush_dsa(struct r600_context * rctx)2797 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2798 {
2799 struct pipe_depth_stencil_alpha_state dsa;
2800 bool quirk = false;
2801
2802 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2803 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2804 quirk = true;
2805
2806 memset(&dsa, 0, sizeof(dsa));
2807
2808 if (quirk) {
2809 dsa.depth_enabled = 1;
2810 dsa.depth_func = PIPE_FUNC_LEQUAL;
2811 dsa.stencil[0].enabled = 1;
2812 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2813 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2814 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2815 dsa.stencil[0].writemask = 0xff;
2816 }
2817
2818 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2819 }
2820
r600_update_db_shader_control(struct r600_context * rctx)2821 void r600_update_db_shader_control(struct r600_context * rctx)
2822 {
2823 bool dual_export;
2824 unsigned db_shader_control;
2825 uint8_t ps_conservative_z;
2826
2827 if (!rctx->ps_shader) {
2828 return;
2829 }
2830
2831 dual_export = rctx->framebuffer.export_16bpc &&
2832 !rctx->ps_shader->current->ps_depth_export;
2833
2834 db_shader_control = rctx->ps_shader->current->db_shader_control |
2835 S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2836
2837 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2838
2839 /* When alpha test is enabled we can't trust the hw to make the proper
2840 * decision on the order in which ztest should be run related to fragment
2841 * shader execution.
2842 *
2843 * If alpha test is enabled perform z test after fragment. RE_Z (early
2844 * z test but no write to the zbuffer) seems to cause lockup on r6xx/r7xx
2845 */
2846 if (rctx->alphatest_state.sx_alpha_test_control) {
2847 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2848 } else {
2849 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2850 }
2851
2852 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2853 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2854 rctx->db_misc_state.db_shader_control = db_shader_control;
2855 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2856 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2857 }
2858 }
2859
r600_array_mode(unsigned mode)2860 static inline unsigned r600_array_mode(unsigned mode)
2861 {
2862 switch (mode) {
2863 default:
2864 case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_0280A0_ARRAY_LINEAR_ALIGNED;
2865 break;
2866 case RADEON_SURF_MODE_1D: return V_0280A0_ARRAY_1D_TILED_THIN1;
2867 break;
2868 case RADEON_SURF_MODE_2D: return V_0280A0_ARRAY_2D_TILED_THIN1;
2869 }
2870 }
2871
r600_dma_copy_tile(struct r600_context * rctx,struct pipe_resource * dst,unsigned dst_level,unsigned dst_x,unsigned dst_y,unsigned dst_z,struct pipe_resource * src,unsigned src_level,unsigned src_x,unsigned src_y,unsigned src_z,unsigned copy_height,unsigned pitch,unsigned bpp)2872 static bool r600_dma_copy_tile(struct r600_context *rctx,
2873 struct pipe_resource *dst,
2874 unsigned dst_level,
2875 unsigned dst_x,
2876 unsigned dst_y,
2877 unsigned dst_z,
2878 struct pipe_resource *src,
2879 unsigned src_level,
2880 unsigned src_x,
2881 unsigned src_y,
2882 unsigned src_z,
2883 unsigned copy_height,
2884 unsigned pitch,
2885 unsigned bpp)
2886 {
2887 struct radeon_cmdbuf *cs = &rctx->b.dma.cs;
2888 struct r600_texture *rsrc = (struct r600_texture*)src;
2889 struct r600_texture *rdst = (struct r600_texture*)dst;
2890 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
2891 unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
2892 uint64_t base, addr;
2893
2894 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
2895 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
2896 assert(dst_mode != src_mode);
2897
2898 y = 0;
2899 lbpp = util_logbase2(bpp);
2900 pitch_tile_max = ((pitch / bpp) / 8) - 1;
2901
2902 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
2903 /* T2L */
2904 array_mode = r600_array_mode(src_mode);
2905 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
2906 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2907 /* linear height must be the same as the slice tile max height, it's ok even
2908 * if the linear destination/source have smaller height as the size of the
2909 * dma packet will be using the copy_height which is always smaller or equal
2910 * to the linear height
2911 */
2912 height = u_minify(rsrc->resource.b.b.height0, src_level);
2913 detile = 1;
2914 x = src_x;
2915 y = src_y;
2916 z = src_z;
2917 base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
2918 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
2919 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
2920 addr += dst_y * pitch + dst_x * bpp;
2921 } else {
2922 /* L2T */
2923 array_mode = r600_array_mode(dst_mode);
2924 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
2925 slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
2926 /* linear height must be the same as the slice tile max height, it's ok even
2927 * if the linear destination/source have smaller height as the size of the
2928 * dma packet will be using the copy_height which is always smaller or equal
2929 * to the linear height
2930 */
2931 height = u_minify(rdst->resource.b.b.height0, dst_level);
2932 detile = 0;
2933 x = dst_x;
2934 y = dst_y;
2935 z = dst_z;
2936 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
2937 addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
2938 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
2939 addr += src_y * pitch + src_x * bpp;
2940 }
2941 /* check that we are in dw/base alignment constraint */
2942 if (addr % 4 || base % 256) {
2943 return false;
2944 }
2945
2946 /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for number
2947 * line in the blit. Compute max 8 line we can copy in the size limit
2948 */
2949 cheight = ((R600_DMA_COPY_MAX_SIZE_DW * 4) / pitch) & 0xfffffff8;
2950 ncopy = (copy_height / cheight) + !!(copy_height % cheight);
2951 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2952
2953 for (i = 0; i < ncopy; i++) {
2954 cheight = cheight > copy_height ? copy_height : cheight;
2955 size = (cheight * pitch) / 4;
2956 /* emit reloc before writing cs so that cs is always in consistent state */
2957 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ);
2958 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE);
2959 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, 1, 0, size));
2960 radeon_emit(cs, base >> 8);
2961 radeon_emit(cs, (detile << 31) | (array_mode << 27) |
2962 (lbpp << 24) | ((height - 1) << 10) |
2963 pitch_tile_max);
2964 radeon_emit(cs, (slice_tile_max << 12) | (z << 0));
2965 radeon_emit(cs, (x << 3) | (y << 17));
2966 radeon_emit(cs, addr & 0xfffffffc);
2967 radeon_emit(cs, (addr >> 32UL) & 0xff);
2968 copy_height -= cheight;
2969 addr += cheight * pitch;
2970 y += cheight;
2971 }
2972 return true;
2973 }
2974
r600_dma_copy(struct pipe_context * ctx,struct pipe_resource * dst,unsigned dst_level,unsigned dstx,unsigned dsty,unsigned dstz,struct pipe_resource * src,unsigned src_level,const struct pipe_box * src_box)2975 static void r600_dma_copy(struct pipe_context *ctx,
2976 struct pipe_resource *dst,
2977 unsigned dst_level,
2978 unsigned dstx, unsigned dsty, unsigned dstz,
2979 struct pipe_resource *src,
2980 unsigned src_level,
2981 const struct pipe_box *src_box)
2982 {
2983 struct r600_context *rctx = (struct r600_context *)ctx;
2984 struct r600_texture *rsrc = (struct r600_texture*)src;
2985 struct r600_texture *rdst = (struct r600_texture*)dst;
2986 unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
2987 unsigned src_w, dst_w;
2988 unsigned src_x, src_y;
2989 unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
2990
2991 if (rctx->b.dma.cs.priv == NULL) {
2992 goto fallback;
2993 }
2994
2995 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
2996 if (dst_x % 4 || src_box->x % 4 || src_box->width % 4)
2997 goto fallback;
2998
2999 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3000 return;
3001 }
3002
3003 if (src_box->depth > 1 ||
3004 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3005 dstz, rsrc, src_level, src_box))
3006 goto fallback;
3007
3008 src_x = util_format_get_nblocksx(src->format, src_box->x);
3009 dst_x = util_format_get_nblocksx(src->format, dst_x);
3010 src_y = util_format_get_nblocksy(src->format, src_box->y);
3011 dst_y = util_format_get_nblocksy(src->format, dst_y);
3012
3013 bpp = rdst->surface.bpe;
3014 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
3015 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3016 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3017 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
3018 copy_height = src_box->height / rsrc->surface.blk_h;
3019
3020 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3021 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3022
3023 if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
3024 /* strict requirement on r6xx/r7xx */
3025 goto fallback;
3026 }
3027 /* lot of constraint on alignment this should capture them all */
3028 if (src_pitch % 8 || src_box->y % 8 || dst_y % 8) {
3029 goto fallback;
3030 }
3031
3032 if (src_mode == dst_mode) {
3033 uint64_t dst_offset, src_offset, size;
3034
3035 /* simple dma blit would do NOTE code here assume :
3036 * src_box.x/y == 0
3037 * dst_x/y == 0
3038 * dst_pitch == src_pitch
3039 */
3040 src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
3041 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
3042 src_offset += src_y * src_pitch + src_x * bpp;
3043 dst_offset = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
3044 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
3045 dst_offset += dst_y * dst_pitch + dst_x * bpp;
3046 size = src_box->height * src_pitch;
3047 /* must be dw aligned */
3048 if (dst_offset % 4 || src_offset % 4 || size % 4) {
3049 goto fallback;
3050 }
3051 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3052 } else {
3053 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3054 src, src_level, src_x, src_y, src_box->z,
3055 copy_height, dst_pitch, bpp)) {
3056 goto fallback;
3057 }
3058 }
3059 return;
3060
3061 fallback:
3062 r600_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
3063 src, src_level, src_box);
3064 }
3065
r600_init_state_functions(struct r600_context * rctx)3066 void r600_init_state_functions(struct r600_context *rctx)
3067 {
3068 unsigned id = 1;
3069 unsigned i;
3070 /* !!!
3071 * To avoid GPU lockup registers must be emitted in a specific order
3072 * (no kidding ...). The order below is important and have been
3073 * partially inferred from analyzing fglrx command stream.
3074 *
3075 * Don't reorder atom without carefully checking the effect (GPU lockup
3076 * or piglit regression).
3077 * !!!
3078 */
3079
3080 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3081
3082 /* shader const */
3083 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3084 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3085 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3086
3087 /* sampler must be emitted before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
3088 * does not take effect (TA_CNTL_AUX emitted by r600_emit_seamless_cube_map)
3089 */
3090 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3091 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3092 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3093 /* resource */
3094 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3095 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3096 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3097 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3098
3099 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3100
3101 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3102 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3103 rctx->sample_mask.sample_mask = ~0;
3104
3105 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3106 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3107 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3108 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3109 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3110 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3111 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3112 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3113 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3114 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 9);
3115 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3116 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3117 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3118 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3119 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3120 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3121 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3122 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3123 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3124 for (i = 0; i < R600_NUM_HW_STAGES; i++)
3125 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3126 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3127 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3128
3129 rctx->b.b.create_blend_state = r600_create_blend_state;
3130 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3131 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3132 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3133 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3134 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3135 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3136 rctx->b.b.set_min_samples = r600_set_min_samples;
3137 rctx->b.b.get_sample_position = r600_get_sample_position;
3138 rctx->b.dma_copy = r600_dma_copy;
3139 }
3140 /* this function must be last */
3141