1 /*
2 * Copyright 2010 Red Hat Inc.
3 * 2010 Jerome Glisse
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
26 */
27 #include "r600_formats.h"
28 #include "r600_shader.h"
29 #include "r600d.h"
30
31 #include "util/format/u_format_s3tc.h"
32 #include "util/u_draw.h"
33 #include "util/u_endian.h"
34 #include "util/u_index_modify.h"
35 #include "util/u_memory.h"
36 #include "util/u_upload_mgr.h"
37 #include "util/u_math.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_scan.h"
40 #include "tgsi/tgsi_ureg.h"
41
42 #include "nir.h"
43 #include "nir/nir_to_tgsi_info.h"
44
r600_init_command_buffer(struct r600_command_buffer * cb,unsigned num_dw)45 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
46 {
47 assert(!cb->buf);
48 cb->buf = CALLOC(1, 4 * num_dw);
49 cb->max_num_dw = num_dw;
50 }
51
r600_release_command_buffer(struct r600_command_buffer * cb)52 void r600_release_command_buffer(struct r600_command_buffer *cb)
53 {
54 FREE(cb->buf);
55 }
56
r600_add_atom(struct r600_context * rctx,struct r600_atom * atom,unsigned id)57 void r600_add_atom(struct r600_context *rctx,
58 struct r600_atom *atom,
59 unsigned id)
60 {
61 assert(id < R600_NUM_ATOMS);
62 assert(rctx->atoms[id] == NULL);
63 rctx->atoms[id] = atom;
64 atom->id = id;
65 }
66
r600_init_atom(struct r600_context * rctx,struct r600_atom * atom,unsigned id,void (* emit)(struct r600_context * ctx,struct r600_atom * state),unsigned num_dw)67 void r600_init_atom(struct r600_context *rctx,
68 struct r600_atom *atom,
69 unsigned id,
70 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
71 unsigned num_dw)
72 {
73 atom->emit = (void*)emit;
74 atom->num_dw = num_dw;
75 r600_add_atom(rctx, atom, id);
76 }
77
r600_emit_cso_state(struct r600_context * rctx,struct r600_atom * atom)78 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
79 {
80 r600_emit_command_buffer(&rctx->b.gfx.cs, ((struct r600_cso_state*)atom)->cb);
81 }
82
r600_emit_alphatest_state(struct r600_context * rctx,struct r600_atom * atom)83 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
84 {
85 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
86 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
87 unsigned alpha_ref = a->sx_alpha_ref;
88
89 if (rctx->b.gfx_level >= EVERGREEN && a->cb0_export_16bpc) {
90 alpha_ref &= ~0x1FFF;
91 }
92
93 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
94 a->sx_alpha_test_control |
95 S_028410_ALPHA_TEST_BYPASS(a->bypass));
96 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
97 }
98
r600_memory_barrier(struct pipe_context * ctx,unsigned flags)99 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
100 {
101 struct r600_context *rctx = (struct r600_context *)ctx;
102
103 if (!(flags & ~PIPE_BARRIER_UPDATE))
104 return;
105
106 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
107 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
108
109 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
110 PIPE_BARRIER_SHADER_BUFFER |
111 PIPE_BARRIER_TEXTURE |
112 PIPE_BARRIER_IMAGE |
113 PIPE_BARRIER_STREAMOUT_BUFFER |
114 PIPE_BARRIER_GLOBAL_BUFFER)) {
115 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE|
116 R600_CONTEXT_INV_TEX_CACHE;
117 }
118
119 if (flags & (PIPE_BARRIER_FRAMEBUFFER|
120 PIPE_BARRIER_IMAGE))
121 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV;
122
123 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
124 }
125
r600_texture_barrier(struct pipe_context * ctx,unsigned flags)126 static void r600_texture_barrier(struct pipe_context *ctx, unsigned flags)
127 {
128 struct r600_context *rctx = (struct r600_context *)ctx;
129
130 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
131 R600_CONTEXT_FLUSH_AND_INV_CB |
132 R600_CONTEXT_FLUSH_AND_INV |
133 R600_CONTEXT_WAIT_3D_IDLE;
134 rctx->framebuffer.do_update_surf_dirtiness = true;
135 }
136
r600_conv_pipe_prim(unsigned prim)137 static unsigned r600_conv_pipe_prim(unsigned prim)
138 {
139 static const unsigned prim_conv[] = {
140 [MESA_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
141 [MESA_PRIM_LINES] = V_008958_DI_PT_LINELIST,
142 [MESA_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
143 [MESA_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
144 [MESA_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
145 [MESA_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
146 [MESA_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
147 [MESA_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
148 [MESA_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
149 [MESA_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
150 [MESA_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
151 [MESA_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
152 [MESA_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
153 [MESA_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
154 [MESA_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
155 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
156 };
157 assert(prim < ARRAY_SIZE(prim_conv));
158 return prim_conv[prim];
159 }
160
r600_conv_prim_to_gs_out(unsigned mode)161 unsigned r600_conv_prim_to_gs_out(unsigned mode)
162 {
163 static const int prim_conv[] = {
164 [MESA_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
165 [MESA_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
166 [MESA_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
167 [MESA_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
168 [MESA_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
169 [MESA_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
170 [MESA_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
171 [MESA_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
172 [MESA_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
173 [MESA_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
174 [MESA_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
175 [MESA_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
176 [MESA_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
177 [MESA_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
178 [MESA_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
179 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
180 };
181 assert(mode < ARRAY_SIZE(prim_conv));
182
183 return prim_conv[mode];
184 }
185
186 /* common state between evergreen and r600 */
187
r600_bind_blend_state_internal(struct r600_context * rctx,struct r600_blend_state * blend,bool blend_disable)188 static void r600_bind_blend_state_internal(struct r600_context *rctx,
189 struct r600_blend_state *blend, bool blend_disable)
190 {
191 unsigned color_control;
192 bool update_cb = false;
193
194 rctx->alpha_to_one = blend->alpha_to_one;
195 rctx->dual_src_blend = blend->dual_src_blend;
196
197 if (!blend_disable) {
198 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer);
199 color_control = blend->cb_color_control;
200 } else {
201 /* Blending is disabled. */
202 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, blend, &blend->buffer_no_blend);
203 color_control = blend->cb_color_control_no_blend;
204 }
205
206 /* Update derived states. */
207 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
208 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
209 update_cb = true;
210 }
211 if (rctx->b.gfx_level <= R700 &&
212 rctx->cb_misc_state.cb_color_control != color_control) {
213 rctx->cb_misc_state.cb_color_control = color_control;
214 update_cb = true;
215 }
216 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
217 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
218 update_cb = true;
219 }
220 if (update_cb) {
221 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
222 }
223 if (rctx->framebuffer.dual_src_blend != blend->dual_src_blend) {
224 rctx->framebuffer.dual_src_blend = blend->dual_src_blend;
225 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
226 }
227 }
228
r600_bind_blend_state(struct pipe_context * ctx,void * state)229 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
230 {
231 struct r600_context *rctx = (struct r600_context *)ctx;
232 struct r600_blend_state *blend = (struct r600_blend_state *)state;
233
234 if (!blend) {
235 r600_set_cso_state_with_cb(rctx, &rctx->blend_state, NULL, NULL);
236 return;
237 }
238
239 r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
240 }
241
r600_set_blend_color(struct pipe_context * ctx,const struct pipe_blend_color * state)242 static void r600_set_blend_color(struct pipe_context *ctx,
243 const struct pipe_blend_color *state)
244 {
245 struct r600_context *rctx = (struct r600_context *)ctx;
246
247 rctx->blend_color.state = *state;
248 r600_mark_atom_dirty(rctx, &rctx->blend_color.atom);
249 }
250
r600_emit_blend_color(struct r600_context * rctx,struct r600_atom * atom)251 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
252 {
253 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
254 struct pipe_blend_color *state = &rctx->blend_color.state;
255
256 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
257 radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
258 radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
259 radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
260 radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
261 }
262
r600_emit_vgt_state(struct r600_context * rctx,struct r600_atom * atom)263 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
264 {
265 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
266 struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
267
268 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
269 radeon_set_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
270 radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
271 radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
272 if (a->last_draw_was_indirect) {
273 a->last_draw_was_indirect = false;
274 radeon_set_ctl_const(cs, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
275 }
276 }
277
r600_set_clip_state(struct pipe_context * ctx,const struct pipe_clip_state * state)278 static void r600_set_clip_state(struct pipe_context *ctx,
279 const struct pipe_clip_state *state)
280 {
281 struct r600_context *rctx = (struct r600_context *)ctx;
282
283 rctx->clip_state.state = *state;
284 r600_mark_atom_dirty(rctx, &rctx->clip_state.atom);
285 rctx->driver_consts[PIPE_SHADER_VERTEX].vs_ucp_dirty = true;
286 rctx->driver_consts[PIPE_SHADER_GEOMETRY].vs_ucp_dirty = true;
287 if (rctx->b.family >= CHIP_CEDAR)
288 rctx->driver_consts[PIPE_SHADER_TESS_EVAL].vs_ucp_dirty = true;
289 }
290
r600_set_stencil_ref(struct pipe_context * ctx,const struct r600_stencil_ref state)291 static void r600_set_stencil_ref(struct pipe_context *ctx,
292 const struct r600_stencil_ref state)
293 {
294 struct r600_context *rctx = (struct r600_context *)ctx;
295
296 rctx->stencil_ref.state = state;
297 r600_mark_atom_dirty(rctx, &rctx->stencil_ref.atom);
298 }
299
r600_emit_stencil_ref(struct r600_context * rctx,struct r600_atom * atom)300 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
301 {
302 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
303 struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
304
305 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
306 radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
307 S_028430_STENCILREF(a->state.ref_value[0]) |
308 S_028430_STENCILMASK(a->state.valuemask[0]) |
309 S_028430_STENCILWRITEMASK(a->state.writemask[0]));
310 radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
311 S_028434_STENCILREF_BF(a->state.ref_value[1]) |
312 S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
313 S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
314 }
315
r600_set_pipe_stencil_ref(struct pipe_context * ctx,const struct pipe_stencil_ref state)316 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
317 const struct pipe_stencil_ref state)
318 {
319 struct r600_context *rctx = (struct r600_context *)ctx;
320 struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
321 struct r600_stencil_ref ref;
322
323 rctx->stencil_ref.pipe_state = state;
324
325 if (!dsa)
326 return;
327
328 ref.ref_value[0] = state.ref_value[0];
329 ref.ref_value[1] = state.ref_value[1];
330 ref.valuemask[0] = dsa->valuemask[0];
331 ref.valuemask[1] = dsa->valuemask[1];
332 ref.writemask[0] = dsa->writemask[0];
333 ref.writemask[1] = dsa->writemask[1];
334
335 r600_set_stencil_ref(ctx, ref);
336 }
337
r600_bind_dsa_state(struct pipe_context * ctx,void * state)338 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
339 {
340 struct r600_context *rctx = (struct r600_context *)ctx;
341 struct r600_dsa_state *dsa = state;
342 struct r600_stencil_ref ref;
343
344 if (!state) {
345 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, NULL, NULL);
346 return;
347 }
348
349 r600_set_cso_state_with_cb(rctx, &rctx->dsa_state, dsa, &dsa->buffer);
350
351 ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
352 ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
353 ref.valuemask[0] = dsa->valuemask[0];
354 ref.valuemask[1] = dsa->valuemask[1];
355 ref.writemask[0] = dsa->writemask[0];
356 ref.writemask[1] = dsa->writemask[1];
357 if (rctx->zwritemask != dsa->zwritemask) {
358 rctx->zwritemask = dsa->zwritemask;
359 if (rctx->b.gfx_level >= EVERGREEN) {
360 /* work around some issue when not writing to zbuffer
361 * we are having lockup on evergreen so do not enable
362 * hyperz when not writing zbuffer
363 */
364 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
365 }
366 }
367
368 r600_set_stencil_ref(ctx, ref);
369
370 /* Update alphatest state. */
371 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
372 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
373 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
374 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
375 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
376 }
377 }
378
r600_bind_rs_state(struct pipe_context * ctx,void * state)379 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
380 {
381 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
382 struct r600_context *rctx = (struct r600_context *)ctx;
383
384 if (!state)
385 return;
386
387 rctx->rasterizer = rs;
388
389 r600_set_cso_state_with_cb(rctx, &rctx->rasterizer_state, rs, &rs->buffer);
390
391 if (rs->offset_enable &&
392 (rs->offset_units != rctx->poly_offset_state.offset_units ||
393 rs->offset_scale != rctx->poly_offset_state.offset_scale ||
394 rs->offset_units_unscaled != rctx->poly_offset_state.offset_units_unscaled)) {
395 rctx->poly_offset_state.offset_units = rs->offset_units;
396 rctx->poly_offset_state.offset_scale = rs->offset_scale;
397 rctx->poly_offset_state.offset_units_unscaled = rs->offset_units_unscaled;
398 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
399 }
400
401 /* Update clip_misc_state. */
402 if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
403 rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
404 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
405 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
406 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
407 }
408
409 r600_viewport_set_rast_deps(&rctx->b, rs->scissor_enable, rs->clip_halfz);
410
411 /* Re-emit PA_SC_LINE_STIPPLE. */
412 rctx->last_primitive_type = -1;
413 }
414
r600_delete_rs_state(struct pipe_context * ctx,void * state)415 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
416 {
417 struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
418
419 r600_release_command_buffer(&rs->buffer);
420 FREE(rs);
421 }
422
r600_sampler_view_destroy(struct pipe_context * ctx,struct pipe_sampler_view * state)423 static void r600_sampler_view_destroy(struct pipe_context *ctx,
424 struct pipe_sampler_view *state)
425 {
426 struct r600_pipe_sampler_view *view = (struct r600_pipe_sampler_view *)state;
427
428 if (view->tex_resource->gpu_address &&
429 view->tex_resource->b.b.target == PIPE_BUFFER)
430 list_delinit(&view->list);
431
432 pipe_resource_reference(&state->texture, NULL);
433 FREE(view);
434 }
435
r600_sampler_states_dirty(struct r600_context * rctx,struct r600_sampler_states * state)436 void r600_sampler_states_dirty(struct r600_context *rctx,
437 struct r600_sampler_states *state)
438 {
439 if (state->dirty_mask) {
440 if (state->dirty_mask & state->has_bordercolor_mask) {
441 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
442 }
443 state->atom.num_dw =
444 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
445 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
446 r600_mark_atom_dirty(rctx, &state->atom);
447 }
448 }
449
r600_bind_sampler_states(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned count,void ** states)450 static void r600_bind_sampler_states(struct pipe_context *pipe,
451 enum pipe_shader_type shader,
452 unsigned start,
453 unsigned count, void **states)
454 {
455 struct r600_context *rctx = (struct r600_context *)pipe;
456 struct r600_textures_info *dst = &rctx->samplers[shader];
457 struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
458 int seamless_cube_map = -1;
459 unsigned i;
460 /* This sets 1-bit for states with index >= count. */
461 uint32_t disable_mask = ~((1ull << count) - 1);
462 /* These are the new states set by this function. */
463 uint32_t new_mask = 0;
464
465 assert(start == 0); /* XXX fix below */
466
467 if (!states) {
468 disable_mask = ~0u;
469 count = 0;
470 }
471
472 for (i = 0; i < count; i++) {
473 struct r600_pipe_sampler_state *rstate = rstates[i];
474
475 if (rstate == dst->states.states[i]) {
476 continue;
477 }
478
479 if (rstate) {
480 if (rstate->border_color_use) {
481 dst->states.has_bordercolor_mask |= 1 << i;
482 } else {
483 dst->states.has_bordercolor_mask &= ~(1 << i);
484 }
485 seamless_cube_map = rstate->seamless_cube_map;
486
487 new_mask |= 1 << i;
488 } else {
489 disable_mask |= 1 << i;
490 }
491 }
492
493 memcpy(dst->states.states, rstates, sizeof(void*) * count);
494 memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
495
496 dst->states.enabled_mask &= ~disable_mask;
497 dst->states.dirty_mask &= dst->states.enabled_mask;
498 dst->states.enabled_mask |= new_mask;
499 dst->states.dirty_mask |= new_mask;
500 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
501
502 r600_sampler_states_dirty(rctx, &dst->states);
503
504 /* Seamless cubemap state. */
505 if (rctx->b.gfx_level <= R700 &&
506 seamless_cube_map != -1 &&
507 seamless_cube_map != rctx->seamless_cube_map.enabled) {
508 /* change in TA_CNTL_AUX need a pipeline flush */
509 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
510 rctx->seamless_cube_map.enabled = seamless_cube_map;
511 r600_mark_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
512 }
513 }
514
r600_delete_sampler_state(struct pipe_context * ctx,void * state)515 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
516 {
517 free(state);
518 }
519
r600_delete_blend_state(struct pipe_context * ctx,void * state)520 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
521 {
522 struct r600_context *rctx = (struct r600_context *)ctx;
523 struct r600_blend_state *blend = (struct r600_blend_state*)state;
524
525 if (rctx->blend_state.cso == state) {
526 ctx->bind_blend_state(ctx, NULL);
527 }
528
529 r600_release_command_buffer(&blend->buffer);
530 r600_release_command_buffer(&blend->buffer_no_blend);
531 FREE(blend);
532 }
533
r600_delete_dsa_state(struct pipe_context * ctx,void * state)534 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
535 {
536 struct r600_context *rctx = (struct r600_context *)ctx;
537 struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
538
539 if (rctx->dsa_state.cso == state) {
540 ctx->bind_depth_stencil_alpha_state(ctx, NULL);
541 }
542
543 r600_release_command_buffer(&dsa->buffer);
544 free(dsa);
545 }
546
r600_delete_vertex_elements(struct pipe_context * ctx,void * state)547 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
548 {
549 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
550 if (shader)
551 r600_resource_reference(&shader->buffer, NULL);
552 FREE(shader);
553 }
554
r600_vertex_buffers_dirty(struct r600_context * rctx)555 void r600_vertex_buffers_dirty(struct r600_context *rctx)
556 {
557 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)rctx->vertex_fetch_shader.cso;
558 if (shader && (rctx->vertex_buffer_state.dirty_mask & shader->buffer_mask)) {
559 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.gfx_level >= EVERGREEN ? 12 : 11) *
560 util_bitcount(rctx->vertex_buffer_state.dirty_mask & shader->buffer_mask);
561 r600_mark_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
562 }
563 }
564
r600_bind_vertex_elements(struct pipe_context * ctx,void * state)565 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
566 {
567 struct r600_context *rctx = (struct r600_context *)ctx;
568 struct r600_fetch_shader *prev = (struct r600_fetch_shader*)rctx->vertex_fetch_shader.cso;
569 struct r600_fetch_shader *cso = state;
570
571 r600_set_cso_state(rctx, &rctx->vertex_fetch_shader, state);
572 if (!prev || (cso && cso->buffer_mask &&
573 (prev->buffer_mask != cso->buffer_mask || memcmp(cso->strides, prev->strides, util_last_bit(cso->buffer_mask))))) {
574 rctx->vertex_buffer_state.dirty_mask |= cso ? cso->buffer_mask : 0;
575 r600_vertex_buffers_dirty(rctx);
576 }
577 }
578
r600_set_vertex_buffers(struct pipe_context * ctx,unsigned count,const struct pipe_vertex_buffer * input)579 static void r600_set_vertex_buffers(struct pipe_context *ctx,
580 unsigned count,
581 const struct pipe_vertex_buffer *input)
582 {
583 struct r600_context *rctx = (struct r600_context *)ctx;
584 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
585 struct pipe_vertex_buffer *vb = state->vb;
586 unsigned i;
587 uint32_t disable_mask = 0;
588 /* These are the new buffers set by this function. */
589 uint32_t new_buffer_mask = 0;
590
591 /* Set vertex buffers. */
592 for (i = 0; i < count; i++) {
593 if (likely((input[i].buffer.resource != vb[i].buffer.resource) ||
594 (vb[i].buffer_offset != input[i].buffer_offset) ||
595 (vb[i].is_user_buffer != input[i].is_user_buffer))) {
596 if (input[i].buffer.resource) {
597 vb[i].buffer_offset = input[i].buffer_offset;
598 pipe_resource_reference(&vb[i].buffer.resource, NULL);
599 vb[i].buffer.resource = input[i].buffer.resource;
600 new_buffer_mask |= 1 << i;
601 r600_context_add_resource_size(ctx, input[i].buffer.resource);
602 } else {
603 pipe_resource_reference(&vb[i].buffer.resource, NULL);
604 disable_mask |= 1 << i;
605 }
606 } else if (input[i].buffer.resource) {
607 pipe_resource_reference(&vb[i].buffer.resource, NULL);
608 vb[i].buffer.resource = input[i].buffer.resource;
609 }
610 }
611
612 unsigned last_count = util_last_bit(rctx->vertex_buffer_state.enabled_mask);
613 for (; i < last_count; i++)
614 pipe_resource_reference(&vb[i].buffer.resource, NULL);
615
616 if (last_count > count)
617 disable_mask |= BITFIELD_RANGE(count, last_count - count);
618
619 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
620 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
621 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
622 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
623
624 r600_vertex_buffers_dirty(rctx);
625 }
626
r600_sampler_views_dirty(struct r600_context * rctx,struct r600_samplerview_state * state)627 void r600_sampler_views_dirty(struct r600_context *rctx,
628 struct r600_samplerview_state *state)
629 {
630 if (state->dirty_mask) {
631 state->atom.num_dw = (rctx->b.gfx_level >= EVERGREEN ? 14 : 13) *
632 util_bitcount(state->dirty_mask);
633 r600_mark_atom_dirty(rctx, &state->atom);
634 }
635 }
636
r600_set_sampler_views(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned count,unsigned unbind_num_trailing_slots,bool take_ownership,struct pipe_sampler_view ** views)637 static void r600_set_sampler_views(struct pipe_context *pipe,
638 enum pipe_shader_type shader,
639 unsigned start, unsigned count,
640 unsigned unbind_num_trailing_slots,
641 bool take_ownership,
642 struct pipe_sampler_view **views)
643 {
644 struct r600_context *rctx = (struct r600_context *) pipe;
645 struct r600_textures_info *dst = &rctx->samplers[shader];
646 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
647 uint32_t dirty_sampler_states_mask = 0;
648 unsigned i;
649 /* This sets 1-bit for textures with index >= count. */
650 uint32_t disable_mask = ~((1ull << count) - 1);
651 /* These are the new textures set by this function. */
652 uint32_t new_mask = 0;
653
654 /* Set textures with index >= count to NULL. */
655 uint32_t remaining_mask;
656
657 assert(start == 0); /* XXX fix below */
658
659 if (!views) {
660 disable_mask = ~0u;
661 count = 0;
662 }
663
664 remaining_mask = dst->views.enabled_mask & disable_mask;
665
666 while (remaining_mask) {
667 i = u_bit_scan(&remaining_mask);
668 assert(dst->views.views[i]);
669
670 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
671 }
672
673 for (i = 0; i < count; i++) {
674 if (rviews[i] == dst->views.views[i]) {
675 if (take_ownership) {
676 struct pipe_sampler_view *view = views[i];
677 pipe_sampler_view_reference(&view, NULL);
678 }
679 continue;
680 }
681
682 if (rviews[i]) {
683 struct r600_texture *rtex =
684 (struct r600_texture*)rviews[i]->base.texture;
685 bool is_buffer = rviews[i]->base.texture->target == PIPE_BUFFER;
686
687 if (!is_buffer && rtex->db_compatible) {
688 dst->views.compressed_depthtex_mask |= 1 << i;
689 } else {
690 dst->views.compressed_depthtex_mask &= ~(1 << i);
691 }
692
693 /* Track compressed colorbuffers. */
694 if (!is_buffer && rtex->cmask.size) {
695 dst->views.compressed_colortex_mask |= 1 << i;
696 } else {
697 dst->views.compressed_colortex_mask &= ~(1 << i);
698 }
699
700 /* Changing from array to non-arrays textures and vice versa requires
701 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
702 if (rctx->b.gfx_level <= R700 &&
703 (dst->states.enabled_mask & (1 << i)) &&
704 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
705 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
706 dirty_sampler_states_mask |= 1 << i;
707 }
708
709 if (take_ownership) {
710 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
711 dst->views.views[i] = (struct r600_pipe_sampler_view*)views[i];
712 } else {
713 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
714 }
715 new_mask |= 1 << i;
716 r600_context_add_resource_size(pipe, views[i]->texture);
717 } else {
718 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
719 disable_mask |= 1 << i;
720 }
721 }
722
723 dst->views.enabled_mask &= ~disable_mask;
724 dst->views.dirty_mask &= dst->views.enabled_mask;
725 dst->views.enabled_mask |= new_mask;
726 dst->views.dirty_mask |= new_mask;
727 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
728 dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
729 dst->views.dirty_buffer_constants = true;
730 r600_sampler_views_dirty(rctx, &dst->views);
731
732 if (dirty_sampler_states_mask) {
733 dst->states.dirty_mask |= dirty_sampler_states_mask;
734 r600_sampler_states_dirty(rctx, &dst->states);
735 }
736 }
737
r600_update_compressed_colortex_mask(struct r600_samplerview_state * views)738 static void r600_update_compressed_colortex_mask(struct r600_samplerview_state *views)
739 {
740 uint32_t mask = views->enabled_mask;
741
742 while (mask) {
743 unsigned i = u_bit_scan(&mask);
744 struct pipe_resource *res = views->views[i]->base.texture;
745
746 if (res && res->target != PIPE_BUFFER) {
747 struct r600_texture *rtex = (struct r600_texture *)res;
748
749 if (rtex->cmask.size) {
750 views->compressed_colortex_mask |= 1 << i;
751 } else {
752 views->compressed_colortex_mask &= ~(1 << i);
753 }
754 }
755 }
756 }
757
r600_get_hw_atomic_count(const struct pipe_context * ctx,enum pipe_shader_type shader)758 static int r600_get_hw_atomic_count(const struct pipe_context *ctx,
759 enum pipe_shader_type shader)
760 {
761 const struct r600_context *rctx = (struct r600_context *)ctx;
762 int value = 0;
763 switch (shader) {
764 case PIPE_SHADER_FRAGMENT:
765 case PIPE_SHADER_COMPUTE:
766 default:
767 break;
768 case PIPE_SHADER_VERTEX:
769 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
770 break;
771 case PIPE_SHADER_GEOMETRY:
772 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
773 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
774 break;
775 case PIPE_SHADER_TESS_EVAL:
776 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
777 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
778 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0);
779 break;
780 case PIPE_SHADER_TESS_CTRL:
781 value = rctx->ps_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
782 rctx->vs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] +
783 (rctx->gs_shader ? rctx->gs_shader->info.file_count[TGSI_FILE_HW_ATOMIC] : 0) +
784 rctx->tes_shader->info.file_count[TGSI_FILE_HW_ATOMIC];
785 break;
786 }
787 return value;
788 }
789
r600_update_compressed_colortex_mask_images(struct r600_image_state * images)790 static void r600_update_compressed_colortex_mask_images(struct r600_image_state *images)
791 {
792 uint32_t mask = images->enabled_mask;
793
794 while (mask) {
795 unsigned i = u_bit_scan(&mask);
796 struct pipe_resource *res = images->views[i].base.resource;
797
798 if (res && res->target != PIPE_BUFFER) {
799 struct r600_texture *rtex = (struct r600_texture *)res;
800
801 if (rtex->cmask.size) {
802 images->compressed_colortex_mask |= 1 << i;
803 } else {
804 images->compressed_colortex_mask &= ~(1 << i);
805 }
806 }
807 }
808 }
809
810 /* Compute the key for the hw shader variant */
r600_shader_selector_key(const struct pipe_context * ctx,const struct r600_pipe_shader_selector * sel,union r600_shader_key * key)811 static inline void r600_shader_selector_key(const struct pipe_context *ctx,
812 const struct r600_pipe_shader_selector *sel,
813 union r600_shader_key *key)
814 {
815 const struct r600_context *rctx = (struct r600_context *)ctx;
816 memset(key, 0, sizeof(*key));
817
818 switch (sel->type) {
819 case PIPE_SHADER_VERTEX: {
820 key->vs.as_ls = (rctx->tes_shader != NULL);
821 if (!key->vs.as_ls)
822 key->vs.as_es = (rctx->gs_shader != NULL);
823
824 if (rctx->ps_shader->current->shader.gs_prim_id_input && !rctx->gs_shader) {
825 key->vs.as_gs_a = true;
826 }
827 key->vs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_VERTEX);
828 break;
829 }
830 case PIPE_SHADER_GEOMETRY:
831 key->gs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_GEOMETRY);
832 key->gs.tri_strip_adj_fix = rctx->gs_tri_strip_adj_fix;
833 break;
834 case PIPE_SHADER_FRAGMENT: {
835 if (rctx->ps_shader->info.images_declared)
836 key->ps.image_size_const_offset = util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask);
837 key->ps.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_FRAGMENT);
838 key->ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
839 key->ps.alpha_to_one = rctx->alpha_to_one &&
840 rctx->rasterizer && rctx->rasterizer->multisample_enable &&
841 !rctx->framebuffer.cb0_is_integer;
842 key->ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
843 key->ps.apply_sample_id_mask = (rctx->ps_iter_samples > 1) || !rctx->rasterizer->multisample_enable;
844 /* Dual-source blending only makes sense with nr_cbufs == 1. */
845 if (key->ps.nr_cbufs == 1 && rctx->dual_src_blend) {
846 key->ps.nr_cbufs = 2;
847 key->ps.dual_source_blend = 1;
848 }
849 break;
850 }
851 case PIPE_SHADER_TESS_EVAL:
852 key->tes.as_es = (rctx->gs_shader != NULL);
853 key->tes.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_EVAL);
854 break;
855 case PIPE_SHADER_TESS_CTRL:
856 key->tcs.prim_mode = rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
857 key->tcs.first_atomic_counter = r600_get_hw_atomic_count(ctx, PIPE_SHADER_TESS_CTRL);
858 break;
859 case PIPE_SHADER_COMPUTE:
860 break;
861 default:
862 assert(0);
863 }
864 }
865
866 static void
r600_shader_precompile_key(const struct pipe_context * ctx,const struct r600_pipe_shader_selector * sel,union r600_shader_key * key)867 r600_shader_precompile_key(const struct pipe_context *ctx,
868 const struct r600_pipe_shader_selector *sel,
869 union r600_shader_key *key)
870 {
871 memset(key, 0, sizeof(*key));
872
873 switch (sel->type) {
874 case PIPE_SHADER_VERTEX:
875 case PIPE_SHADER_TESS_EVAL:
876 /* Assume no tess or GS for setting .as_es. In order to
877 * precompile with es, we'd need the other shaders we're linked
878 * with (see the link_shader screen method)
879 */
880 break;
881
882 case PIPE_SHADER_GEOMETRY:
883 break;
884
885 case PIPE_SHADER_FRAGMENT:
886 key->ps.image_size_const_offset = sel->info.file_max[TGSI_FILE_IMAGE];
887
888 /* This is used for gl_FragColor output expansion to the number
889 * of color buffers bound, but also with sb it'll drop outputs
890 * to unused cbufs.
891 */
892 key->ps.nr_cbufs = sel->info.file_max[TGSI_FILE_OUTPUT] + 1;
893 break;
894
895 case PIPE_SHADER_TESS_CTRL:
896 /* Prim mode comes from the TES, but we need some valid value. */
897 key->tcs.prim_mode = MESA_PRIM_TRIANGLES;
898 break;
899
900 case PIPE_SHADER_COMPUTE:
901 break;
902
903 default:
904 unreachable("bad shader stage");
905 break;
906 }
907 }
908
909 /* Select the hw shader variant depending on the current state.
910 * (*dirty) is set to 1 if current variant was changed */
r600_shader_select(struct pipe_context * ctx,struct r600_pipe_shader_selector * sel,bool * dirty,bool precompile)911 int r600_shader_select(struct pipe_context *ctx,
912 struct r600_pipe_shader_selector* sel,
913 bool *dirty, bool precompile)
914 {
915 union r600_shader_key key;
916 struct r600_pipe_shader * shader = NULL;
917 int r;
918
919 if (precompile)
920 r600_shader_precompile_key(ctx, sel, &key);
921 else
922 r600_shader_selector_key(ctx, sel, &key);
923
924 /* Check if we don't need to change anything.
925 * This path is also used for most shaders that don't need multiple
926 * variants, it will cost just a computation of the key and this
927 * test. */
928 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
929 return 0;
930 }
931
932 /* lookup if we have other variants in the list */
933 if (sel->num_shaders > 1) {
934 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
935
936 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
937 p = c;
938 c = c->next_variant;
939 }
940
941 if (c) {
942 p->next_variant = c->next_variant;
943 shader = c;
944 }
945 }
946
947 if (unlikely(!shader)) {
948 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
949 shader->selector = sel;
950
951 r = r600_pipe_shader_create(ctx, shader, key);
952 if (unlikely(r)) {
953 R600_ERR("Failed to build shader variant (type=%u) %d\n",
954 sel->type, r);
955 sel->current = NULL;
956 FREE(shader);
957 return r;
958 }
959
960 memcpy(&shader->key, &key, sizeof(key));
961 sel->num_shaders++;
962 }
963
964 if (dirty)
965 *dirty = true;
966
967 shader->next_variant = sel->current;
968 sel->current = shader;
969
970 return 0;
971 }
972
r600_create_shader_state_tokens(struct pipe_context * ctx,const void * prog,enum pipe_shader_ir ir,unsigned pipe_shader_type)973 struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx,
974 const void *prog, enum pipe_shader_ir ir,
975 unsigned pipe_shader_type)
976 {
977 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
978
979 sel->type = pipe_shader_type;
980 if (ir == PIPE_SHADER_IR_TGSI) {
981 sel->tokens = tgsi_dup_tokens((const struct tgsi_token *)prog);
982 tgsi_scan_shader(sel->tokens, &sel->info);
983 } else if (ir == PIPE_SHADER_IR_NIR){
984 sel->nir = (nir_shader *)prog;
985 nir_tgsi_scan_shader(sel->nir, &sel->info, true);
986 }
987 sel->ir_type = ir;
988 return sel;
989 }
990
r600_create_shader_state(struct pipe_context * ctx,const struct pipe_shader_state * state,unsigned pipe_shader_type)991 static void *r600_create_shader_state(struct pipe_context *ctx,
992 const struct pipe_shader_state *state,
993 unsigned pipe_shader_type)
994 {
995 int i;
996 struct r600_pipe_shader_selector *sel;
997
998 if (state->type == PIPE_SHADER_IR_TGSI)
999 sel = r600_create_shader_state_tokens(ctx, state->tokens, state->type, pipe_shader_type);
1000 else if (state->type == PIPE_SHADER_IR_NIR) {
1001 sel = r600_create_shader_state_tokens(ctx, state->ir.nir, state->type, pipe_shader_type);
1002 } else
1003 unreachable("Unknown shader type");
1004
1005 sel->so = state->stream_output;
1006
1007 switch (pipe_shader_type) {
1008 case PIPE_SHADER_GEOMETRY:
1009 sel->gs_output_prim =
1010 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1011 sel->gs_max_out_vertices =
1012 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1013 sel->gs_num_invocations =
1014 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1015 break;
1016 case PIPE_SHADER_VERTEX:
1017 case PIPE_SHADER_TESS_CTRL:
1018 sel->lds_patch_outputs_written_mask = 0;
1019 sel->lds_outputs_written_mask = 0;
1020
1021 for (i = 0; i < sel->info.num_outputs; i++) {
1022 unsigned name = sel->info.output_semantic_name[i];
1023 unsigned index = sel->info.output_semantic_index[i];
1024
1025 switch (name) {
1026 case TGSI_SEMANTIC_TESSINNER:
1027 case TGSI_SEMANTIC_TESSOUTER:
1028 case TGSI_SEMANTIC_PATCH:
1029 sel->lds_patch_outputs_written_mask |=
1030 1ull << r600_get_lds_unique_index(name, index);
1031 break;
1032 default:
1033 sel->lds_outputs_written_mask |=
1034 1ull << r600_get_lds_unique_index(name, index);
1035 }
1036 }
1037 break;
1038 default:
1039 break;
1040 }
1041
1042 /* Precompile the shader with the expected shader key, to reduce jank at
1043 * draw time. Also produces output for shader-db.
1044 */
1045 bool dirty;
1046 r600_shader_select(ctx, sel, &dirty, true);
1047
1048 return sel;
1049 }
1050
r600_create_ps_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1051 static void *r600_create_ps_state(struct pipe_context *ctx,
1052 const struct pipe_shader_state *state)
1053 {
1054 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
1055 }
1056
r600_create_vs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1057 static void *r600_create_vs_state(struct pipe_context *ctx,
1058 const struct pipe_shader_state *state)
1059 {
1060 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
1061 }
1062
r600_create_gs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1063 static void *r600_create_gs_state(struct pipe_context *ctx,
1064 const struct pipe_shader_state *state)
1065 {
1066 return r600_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
1067 }
1068
r600_create_tcs_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1069 static void *r600_create_tcs_state(struct pipe_context *ctx,
1070 const struct pipe_shader_state *state)
1071 {
1072 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
1073 }
1074
r600_create_tes_state(struct pipe_context * ctx,const struct pipe_shader_state * state)1075 static void *r600_create_tes_state(struct pipe_context *ctx,
1076 const struct pipe_shader_state *state)
1077 {
1078 return r600_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
1079 }
1080
r600_bind_ps_state(struct pipe_context * ctx,void * state)1081 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
1082 {
1083 struct r600_context *rctx = (struct r600_context *)ctx;
1084
1085 if (!state)
1086 state = rctx->dummy_pixel_shader;
1087
1088 rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
1089 }
1090
r600_get_vs_info(struct r600_context * rctx)1091 static struct tgsi_shader_info *r600_get_vs_info(struct r600_context *rctx)
1092 {
1093 if (rctx->gs_shader)
1094 return &rctx->gs_shader->info;
1095 else if (rctx->tes_shader)
1096 return &rctx->tes_shader->info;
1097 else if (rctx->vs_shader)
1098 return &rctx->vs_shader->info;
1099 else
1100 return NULL;
1101 }
1102
r600_bind_vs_state(struct pipe_context * ctx,void * state)1103 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
1104 {
1105 struct r600_context *rctx = (struct r600_context *)ctx;
1106
1107 if (!state || rctx->vs_shader == state)
1108 return;
1109
1110 rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
1111 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1112
1113 if (rctx->vs_shader->so.num_outputs)
1114 rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
1115 }
1116
r600_bind_gs_state(struct pipe_context * ctx,void * state)1117 static void r600_bind_gs_state(struct pipe_context *ctx, void *state)
1118 {
1119 struct r600_context *rctx = (struct r600_context *)ctx;
1120
1121 if (state == rctx->gs_shader)
1122 return;
1123
1124 rctx->gs_shader = (struct r600_pipe_shader_selector *)state;
1125 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1126
1127 if (!state)
1128 return;
1129
1130 if (rctx->gs_shader->so.num_outputs)
1131 rctx->b.streamout.stride_in_dw = rctx->gs_shader->so.stride;
1132 }
1133
r600_bind_tcs_state(struct pipe_context * ctx,void * state)1134 static void r600_bind_tcs_state(struct pipe_context *ctx, void *state)
1135 {
1136 struct r600_context *rctx = (struct r600_context *)ctx;
1137
1138 rctx->tcs_shader = (struct r600_pipe_shader_selector *)state;
1139 }
1140
r600_bind_tes_state(struct pipe_context * ctx,void * state)1141 static void r600_bind_tes_state(struct pipe_context *ctx, void *state)
1142 {
1143 struct r600_context *rctx = (struct r600_context *)ctx;
1144
1145 if (state == rctx->tes_shader)
1146 return;
1147
1148 rctx->tes_shader = (struct r600_pipe_shader_selector *)state;
1149 r600_update_vs_writes_viewport_index(&rctx->b, r600_get_vs_info(rctx));
1150
1151 if (!state)
1152 return;
1153
1154 if (rctx->tes_shader->so.num_outputs)
1155 rctx->b.streamout.stride_in_dw = rctx->tes_shader->so.stride;
1156 }
1157
r600_delete_shader_selector(struct pipe_context * ctx,struct r600_pipe_shader_selector * sel)1158 void r600_delete_shader_selector(struct pipe_context *ctx,
1159 struct r600_pipe_shader_selector *sel)
1160 {
1161 struct r600_pipe_shader *p = sel->current, *c;
1162 while (p) {
1163 c = p->next_variant;
1164 if (p->gs_copy_shader) {
1165 r600_pipe_shader_destroy(ctx, p->gs_copy_shader);
1166 free(p->gs_copy_shader);
1167 }
1168 r600_pipe_shader_destroy(ctx, p);
1169 free(p);
1170 p = c;
1171 }
1172
1173 if (sel->ir_type == PIPE_SHADER_IR_TGSI) {
1174 free(sel->tokens);
1175 /* We might have converted the TGSI shader to a NIR shader */
1176 if (sel->nir)
1177 ralloc_free(sel->nir);
1178 }
1179 else if (sel->ir_type == PIPE_SHADER_IR_NIR)
1180 ralloc_free(sel->nir);
1181 if (sel->nir_blob)
1182 free(sel->nir_blob);
1183 free(sel);
1184 }
1185
1186
r600_delete_ps_state(struct pipe_context * ctx,void * state)1187 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
1188 {
1189 struct r600_context *rctx = (struct r600_context *)ctx;
1190 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1191
1192 if (rctx->ps_shader == sel) {
1193 rctx->ps_shader = NULL;
1194 }
1195
1196 r600_delete_shader_selector(ctx, sel);
1197 }
1198
r600_delete_vs_state(struct pipe_context * ctx,void * state)1199 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
1200 {
1201 struct r600_context *rctx = (struct r600_context *)ctx;
1202 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1203
1204 if (rctx->vs_shader == sel) {
1205 rctx->vs_shader = NULL;
1206 }
1207
1208 r600_delete_shader_selector(ctx, sel);
1209 }
1210
1211
r600_delete_gs_state(struct pipe_context * ctx,void * state)1212 static void r600_delete_gs_state(struct pipe_context *ctx, void *state)
1213 {
1214 struct r600_context *rctx = (struct r600_context *)ctx;
1215 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1216
1217 if (rctx->gs_shader == sel) {
1218 rctx->gs_shader = NULL;
1219 }
1220
1221 r600_delete_shader_selector(ctx, sel);
1222 }
1223
r600_delete_tcs_state(struct pipe_context * ctx,void * state)1224 static void r600_delete_tcs_state(struct pipe_context *ctx, void *state)
1225 {
1226 struct r600_context *rctx = (struct r600_context *)ctx;
1227 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1228
1229 if (rctx->tcs_shader == sel) {
1230 rctx->tcs_shader = NULL;
1231 }
1232
1233 r600_delete_shader_selector(ctx, sel);
1234 }
1235
r600_delete_tes_state(struct pipe_context * ctx,void * state)1236 static void r600_delete_tes_state(struct pipe_context *ctx, void *state)
1237 {
1238 struct r600_context *rctx = (struct r600_context *)ctx;
1239 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
1240
1241 if (rctx->tes_shader == sel) {
1242 rctx->tes_shader = NULL;
1243 }
1244
1245 r600_delete_shader_selector(ctx, sel);
1246 }
1247
r600_constant_buffers_dirty(struct r600_context * rctx,struct r600_constbuf_state * state)1248 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
1249 {
1250 if (state->dirty_mask) {
1251 state->atom.num_dw = rctx->b.gfx_level >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
1252 : util_bitcount(state->dirty_mask)*19;
1253 r600_mark_atom_dirty(rctx, &state->atom);
1254 }
1255 }
1256
r600_set_constant_buffer(struct pipe_context * ctx,enum pipe_shader_type shader,uint index,bool take_ownership,const struct pipe_constant_buffer * input)1257 static void r600_set_constant_buffer(struct pipe_context *ctx,
1258 enum pipe_shader_type shader, uint index,
1259 bool take_ownership,
1260 const struct pipe_constant_buffer *input)
1261 {
1262 struct r600_context *rctx = (struct r600_context *)ctx;
1263 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
1264 struct pipe_constant_buffer *cb;
1265 const uint8_t *ptr;
1266
1267 /* Note that the gallium frontend can unbind constant buffers by
1268 * passing NULL here.
1269 */
1270 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
1271 state->enabled_mask &= ~(1 << index);
1272 state->dirty_mask &= ~(1 << index);
1273 pipe_resource_reference(&state->cb[index].buffer, NULL);
1274 return;
1275 }
1276
1277 cb = &state->cb[index];
1278 cb->buffer_size = input->buffer_size;
1279
1280 ptr = input->user_buffer;
1281
1282 if (ptr) {
1283 /* Upload the user buffer. */
1284 if (UTIL_ARCH_BIG_ENDIAN) {
1285 uint32_t *tmpPtr;
1286 unsigned i, size = input->buffer_size;
1287
1288 if (!(tmpPtr = malloc(size))) {
1289 R600_ERR("Failed to allocate BE swap buffer.\n");
1290 return;
1291 }
1292
1293 for (i = 0; i < size / 4; ++i) {
1294 tmpPtr[i] = util_cpu_to_le32(((uint32_t *)ptr)[i]);
1295 }
1296
1297 u_upload_data(ctx->stream_uploader, 0, size, 256,
1298 tmpPtr, &cb->buffer_offset, &cb->buffer);
1299 free(tmpPtr);
1300 } else {
1301 u_upload_data(ctx->stream_uploader, 0,
1302 input->buffer_size, 256, ptr,
1303 &cb->buffer_offset, &cb->buffer);
1304 }
1305 /* account it in gtt */
1306 rctx->b.gtt += input->buffer_size;
1307 } else {
1308 /* Setup the hw buffer. */
1309 cb->buffer_offset = input->buffer_offset;
1310 if (take_ownership) {
1311 pipe_resource_reference(&cb->buffer, NULL);
1312 cb->buffer = input->buffer;
1313 } else {
1314 pipe_resource_reference(&cb->buffer, input->buffer);
1315 }
1316 r600_context_add_resource_size(ctx, input->buffer);
1317 }
1318
1319 state->enabled_mask |= 1 << index;
1320 state->dirty_mask |= 1 << index;
1321 r600_constant_buffers_dirty(rctx, state);
1322 }
1323
r600_set_sample_mask(struct pipe_context * pipe,unsigned sample_mask)1324 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1325 {
1326 struct r600_context *rctx = (struct r600_context*)pipe;
1327
1328 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
1329 return;
1330
1331 rctx->sample_mask.sample_mask = sample_mask;
1332 r600_mark_atom_dirty(rctx, &rctx->sample_mask.atom);
1333 }
1334
r600_update_driver_const_buffers(struct r600_context * rctx,bool compute_only)1335 void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only)
1336 {
1337 int sh, size;
1338 void *ptr;
1339 struct pipe_constant_buffer cb;
1340 int start, end;
1341
1342 start = compute_only ? PIPE_SHADER_COMPUTE : 0;
1343 end = compute_only ? PIPE_SHADER_TYPES : PIPE_SHADER_COMPUTE;
1344
1345 int last_vertex_stage = PIPE_SHADER_VERTEX;
1346 if (rctx->tes_shader)
1347 last_vertex_stage = PIPE_SHADER_TESS_EVAL;
1348 if (rctx->gs_shader)
1349 last_vertex_stage = PIPE_SHADER_GEOMETRY;
1350
1351 for (sh = start; sh < end; sh++) {
1352 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[sh];
1353 if (!info->vs_ucp_dirty &&
1354 !info->texture_const_dirty &&
1355 !info->ps_sample_pos_dirty &&
1356 !info->tcs_default_levels_dirty &&
1357 !info->cs_block_grid_size_dirty)
1358 continue;
1359
1360 ptr = info->constants;
1361 size = info->alloc_size;
1362 if (info->vs_ucp_dirty) {
1363 assert(sh == PIPE_SHADER_VERTEX ||
1364 sh == PIPE_SHADER_GEOMETRY ||
1365 sh == PIPE_SHADER_TESS_EVAL);
1366 if (!size) {
1367 ptr = rctx->clip_state.state.ucp;
1368 size = R600_UCP_SIZE;
1369 } else {
1370 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1371 }
1372 info->vs_ucp_dirty = false;
1373 }
1374
1375 else if (info->ps_sample_pos_dirty) {
1376 assert(sh == PIPE_SHADER_FRAGMENT);
1377 if (!size) {
1378 ptr = rctx->sample_positions;
1379 size = R600_UCP_SIZE;
1380 } else {
1381 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1382 }
1383 info->ps_sample_pos_dirty = false;
1384 }
1385
1386 else if (info->cs_block_grid_size_dirty) {
1387 assert(sh == PIPE_SHADER_COMPUTE);
1388 if (!size) {
1389 ptr = rctx->cs_block_grid_sizes;
1390 size = R600_CS_BLOCK_GRID_SIZE;
1391 } else {
1392 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1393 }
1394 info->cs_block_grid_size_dirty = false;
1395 }
1396
1397 else if (info->tcs_default_levels_dirty) {
1398 /*
1399 * We'd only really need this for default tcs shader.
1400 */
1401 assert(sh == PIPE_SHADER_TESS_CTRL);
1402 if (!size) {
1403 ptr = rctx->tess_state;
1404 size = R600_TCS_DEFAULT_LEVELS_SIZE;
1405 } else {
1406 memcpy(ptr, rctx->tess_state, R600_TCS_DEFAULT_LEVELS_SIZE);
1407 }
1408 info->tcs_default_levels_dirty = false;
1409 }
1410
1411 if (info->texture_const_dirty) {
1412 assert (ptr);
1413 assert (size);
1414 if (sh == last_vertex_stage)
1415 memcpy(ptr, rctx->clip_state.state.ucp, R600_UCP_SIZE);
1416 if (sh == PIPE_SHADER_FRAGMENT)
1417 memcpy(ptr, rctx->sample_positions, R600_UCP_SIZE);
1418 if (sh == PIPE_SHADER_COMPUTE)
1419 memcpy(ptr, rctx->cs_block_grid_sizes, R600_CS_BLOCK_GRID_SIZE);
1420 if (sh == PIPE_SHADER_TESS_CTRL)
1421 memcpy(ptr, rctx->tess_state, R600_TCS_DEFAULT_LEVELS_SIZE);
1422 }
1423 info->texture_const_dirty = false;
1424
1425 cb.buffer = NULL;
1426 cb.user_buffer = ptr;
1427 cb.buffer_offset = 0;
1428 cb.buffer_size = size;
1429 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, false, &cb);
1430 pipe_resource_reference(&cb.buffer, NULL);
1431 }
1432 }
1433
r600_alloc_buf_consts(struct r600_context * rctx,int shader_type,unsigned array_size,uint32_t * base_offset)1434 static void *r600_alloc_buf_consts(struct r600_context *rctx, int shader_type,
1435 unsigned array_size, uint32_t *base_offset)
1436 {
1437 struct r600_shader_driver_constants_info *info = &rctx->driver_consts[shader_type];
1438 if (array_size + R600_UCP_SIZE > info->alloc_size) {
1439 info->constants = realloc(info->constants, array_size + R600_UCP_SIZE);
1440 info->alloc_size = array_size + R600_UCP_SIZE;
1441 }
1442 memset(info->constants + (R600_UCP_SIZE / 4), 0, array_size);
1443 info->texture_const_dirty = true;
1444 *base_offset = R600_UCP_SIZE;
1445 return info->constants;
1446 }
1447 /*
1448 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
1449 * doesn't require full swizzles it does need masking and setting alpha
1450 * to one, so we setup a set of 5 constants with the masks + alpha value
1451 * then in the shader, we AND the 4 components with 0xffffffff or 0,
1452 * then OR the alpha with the value given here.
1453 * We use a 6th constant to store the txq buffer size in
1454 * we use 7th slot for number of cube layers in a cube map array.
1455 */
r600_setup_buffer_constants(struct r600_context * rctx,int shader_type)1456 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1457 {
1458 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1459 int bits;
1460 uint32_t array_size;
1461 int i, j;
1462 uint32_t *constants;
1463 uint32_t base_offset;
1464 if (!samplers->views.dirty_buffer_constants)
1465 return;
1466
1467 samplers->views.dirty_buffer_constants = false;
1468
1469 bits = util_last_bit(samplers->views.enabled_mask);
1470 array_size = bits * 8 * sizeof(uint32_t);
1471
1472 constants = r600_alloc_buf_consts(rctx, shader_type, array_size, &base_offset);
1473
1474 for (i = 0; i < bits; i++) {
1475 if (samplers->views.enabled_mask & (1 << i)) {
1476 int offset = (base_offset / 4) + i * 8;
1477 const struct util_format_description *desc;
1478 desc = util_format_description(samplers->views.views[i]->base.format);
1479
1480 for (j = 0; j < 4; j++)
1481 if (j < desc->nr_channels)
1482 constants[offset+j] = 0xffffffff;
1483 else
1484 constants[offset+j] = 0x0;
1485 if (desc->nr_channels < 4) {
1486 if (desc->channel[0].pure_integer)
1487 constants[offset+4] = 1;
1488 else
1489 constants[offset+4] = fui(1.0);
1490 } else
1491 constants[offset + 4] = 0;
1492
1493 constants[offset + 5] = samplers->views.views[i]->base.u.buf.size /
1494 util_format_get_blocksize(samplers->views.views[i]->base.format);
1495 constants[offset + 6] = samplers->views.views[i]->base.texture->array_size / 6;
1496 }
1497 }
1498
1499 }
1500
1501 /* On evergreen we store one value
1502 * 1. number of cube layers in a cube map array.
1503 */
eg_setup_buffer_constants(struct r600_context * rctx,int shader_type)1504 void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1505 {
1506 struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1507 struct r600_image_state *images = NULL;
1508 int bits, sview_bits, img_bits;
1509 uint32_t array_size;
1510 int i;
1511 uint32_t *constants;
1512 uint32_t base_offset;
1513
1514 if (shader_type == PIPE_SHADER_FRAGMENT) {
1515 images = &rctx->fragment_images;
1516 } else if (shader_type == PIPE_SHADER_COMPUTE) {
1517 images = &rctx->compute_images;
1518 }
1519
1520 if (!samplers->views.dirty_buffer_constants &&
1521 !(images && images->dirty_buffer_constants))
1522 return;
1523
1524 if (images)
1525 images->dirty_buffer_constants = false;
1526 samplers->views.dirty_buffer_constants = false;
1527
1528 bits = sview_bits = util_last_bit(samplers->views.enabled_mask);
1529 if (images)
1530 bits += util_last_bit(images->enabled_mask);
1531 img_bits = bits;
1532
1533 array_size = bits * sizeof(uint32_t);
1534
1535 constants = r600_alloc_buf_consts(rctx, shader_type, array_size,
1536 &base_offset);
1537
1538 for (i = 0; i < sview_bits; i++) {
1539 if (samplers->views.enabled_mask & (1 << i)) {
1540 uint32_t offset = (base_offset / 4) + i;
1541 constants[offset] = samplers->views.views[i]->base.texture->array_size / 6;
1542 }
1543 }
1544 if (images) {
1545 for (i = sview_bits; i < img_bits; i++) {
1546 int idx = i - sview_bits;
1547 if (images->enabled_mask & (1 << idx)) {
1548 uint32_t offset = (base_offset / 4) + i;
1549 constants[offset] = images->views[idx].base.resource->array_size / 6;
1550 }
1551 }
1552 }
1553 }
1554
1555 /* set sample xy locations as array of fragment shader constants */
r600_set_sample_locations_constant_buffer(struct r600_context * rctx)1556 void r600_set_sample_locations_constant_buffer(struct r600_context *rctx)
1557 {
1558 struct pipe_context *ctx = &rctx->b.b;
1559
1560 assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE);
1561 assert(rctx->framebuffer.nr_samples <= ARRAY_SIZE(rctx->sample_positions)/4);
1562
1563 memset(rctx->sample_positions, 0, 4 * 4 * 16);
1564 for (unsigned i = 0; i < rctx->framebuffer.nr_samples; i++) {
1565 ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]);
1566 /* Also fill in center-zeroed positions used for interpolateAtSample */
1567 rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f;
1568 rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f;
1569 }
1570
1571 rctx->driver_consts[PIPE_SHADER_FRAGMENT].ps_sample_pos_dirty = true;
1572 }
1573
update_shader_atom(struct pipe_context * ctx,struct r600_shader_state * state,struct r600_pipe_shader * shader)1574 static void update_shader_atom(struct pipe_context *ctx,
1575 struct r600_shader_state *state,
1576 struct r600_pipe_shader *shader)
1577 {
1578 struct r600_context *rctx = (struct r600_context *)ctx;
1579
1580 state->shader = shader;
1581 if (shader) {
1582 state->atom.num_dw = shader->command_buffer.num_dw;
1583 r600_context_add_resource_size(ctx, (struct pipe_resource *)shader->bo);
1584 } else {
1585 state->atom.num_dw = 0;
1586 }
1587 r600_mark_atom_dirty(rctx, &state->atom);
1588 }
1589
update_gs_block_state(struct r600_context * rctx,unsigned enable)1590 static void update_gs_block_state(struct r600_context *rctx, unsigned enable)
1591 {
1592 if (rctx->shader_stages.geom_enable != enable) {
1593 rctx->shader_stages.geom_enable = enable;
1594 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1595 }
1596
1597 if (rctx->gs_rings.enable != enable) {
1598 rctx->gs_rings.enable = enable;
1599 r600_mark_atom_dirty(rctx, &rctx->gs_rings.atom);
1600
1601 if (enable && !rctx->gs_rings.esgs_ring.buffer) {
1602 unsigned size = 0x1C000;
1603 rctx->gs_rings.esgs_ring.buffer =
1604 pipe_buffer_create(rctx->b.b.screen, 0,
1605 PIPE_USAGE_DEFAULT, size);
1606 rctx->gs_rings.esgs_ring.buffer_size = size;
1607
1608 size = 0x4000000;
1609
1610 rctx->gs_rings.gsvs_ring.buffer =
1611 pipe_buffer_create(rctx->b.b.screen, 0,
1612 PIPE_USAGE_DEFAULT, size);
1613 rctx->gs_rings.gsvs_ring.buffer_size = size;
1614 }
1615
1616 if (enable) {
1617 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1618 R600_GS_RING_CONST_BUFFER, false, &rctx->gs_rings.esgs_ring);
1619 if (rctx->tes_shader) {
1620 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1621 R600_GS_RING_CONST_BUFFER, false, &rctx->gs_rings.gsvs_ring);
1622 } else {
1623 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1624 R600_GS_RING_CONST_BUFFER, false, &rctx->gs_rings.gsvs_ring);
1625 }
1626 } else {
1627 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_GEOMETRY,
1628 R600_GS_RING_CONST_BUFFER, false, NULL);
1629 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
1630 R600_GS_RING_CONST_BUFFER, false, NULL);
1631 r600_set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
1632 R600_GS_RING_CONST_BUFFER, false, NULL);
1633 }
1634 }
1635 }
1636
r600_update_clip_state(struct r600_context * rctx,struct r600_pipe_shader * current)1637 static void r600_update_clip_state(struct r600_context *rctx,
1638 struct r600_pipe_shader *current)
1639 {
1640 if (current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
1641 current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write ||
1642 current->shader.cull_dist_write != rctx->clip_misc_state.cull_dist_write ||
1643 current->shader.vs_position_window_space != rctx->clip_misc_state.clip_disable ||
1644 current->shader.vs_out_viewport != rctx->clip_misc_state.vs_out_viewport) {
1645 rctx->clip_misc_state.pa_cl_vs_out_cntl = current->pa_cl_vs_out_cntl;
1646 rctx->clip_misc_state.clip_dist_write = current->shader.clip_dist_write;
1647 rctx->clip_misc_state.cull_dist_write = current->shader.cull_dist_write;
1648 rctx->clip_misc_state.clip_disable = current->shader.vs_position_window_space;
1649 rctx->clip_misc_state.vs_out_viewport = current->shader.vs_out_viewport;
1650 r600_mark_atom_dirty(rctx, &rctx->clip_misc_state.atom);
1651 }
1652 }
1653
r600_generate_fixed_func_tcs(struct r600_context * rctx)1654 static void r600_generate_fixed_func_tcs(struct r600_context *rctx)
1655 {
1656 struct ureg_src const0, const1;
1657 struct ureg_dst tessouter, tessinner;
1658 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1659
1660 if (!ureg)
1661 return; /* if we get here, we're screwed */
1662
1663 assert(!rctx->fixed_func_tcs_shader);
1664
1665 ureg_DECL_constant2D(ureg, 0, 1, R600_BUFFER_INFO_CONST_BUFFER);
1666 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1667 R600_BUFFER_INFO_CONST_BUFFER);
1668 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1669 R600_BUFFER_INFO_CONST_BUFFER);
1670
1671 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1672 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1673
1674 ureg_MOV(ureg, tessouter, const0);
1675 ureg_MOV(ureg, tessinner, const1);
1676 ureg_END(ureg);
1677
1678 rctx->fixed_func_tcs_shader =
1679 ureg_create_shader_and_destroy(ureg, &rctx->b.b);
1680 }
1681
r600_update_compressed_resource_state(struct r600_context * rctx,bool compute_only)1682 void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only)
1683 {
1684 unsigned i;
1685 unsigned counter;
1686
1687 counter = p_atomic_read(&rctx->screen->b.compressed_colortex_counter);
1688 if (counter != rctx->b.last_compressed_colortex_counter) {
1689 rctx->b.last_compressed_colortex_counter = counter;
1690
1691 if (compute_only) {
1692 r600_update_compressed_colortex_mask(&rctx->samplers[PIPE_SHADER_COMPUTE].views);
1693 } else {
1694 for (i = 0; i < PIPE_SHADER_TYPES; ++i) {
1695 r600_update_compressed_colortex_mask(&rctx->samplers[i].views);
1696 }
1697 }
1698 if (!compute_only)
1699 r600_update_compressed_colortex_mask_images(&rctx->fragment_images);
1700 r600_update_compressed_colortex_mask_images(&rctx->compute_images);
1701 }
1702
1703 /* Decompress textures if needed. */
1704 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1705 struct r600_samplerview_state *views = &rctx->samplers[i].views;
1706
1707 if (compute_only)
1708 if (i != PIPE_SHADER_COMPUTE)
1709 continue;
1710 if (views->compressed_depthtex_mask) {
1711 r600_decompress_depth_textures(rctx, views);
1712 }
1713 if (views->compressed_colortex_mask) {
1714 r600_decompress_color_textures(rctx, views);
1715 }
1716 }
1717
1718 {
1719 struct r600_image_state *istate;
1720
1721 if (!compute_only) {
1722 istate = &rctx->fragment_images;
1723 if (istate->compressed_depthtex_mask)
1724 r600_decompress_depth_images(rctx, istate);
1725 if (istate->compressed_colortex_mask)
1726 r600_decompress_color_images(rctx, istate);
1727 }
1728
1729 istate = &rctx->compute_images;
1730 if (istate->compressed_depthtex_mask)
1731 r600_decompress_depth_images(rctx, istate);
1732 if (istate->compressed_colortex_mask)
1733 r600_decompress_color_images(rctx, istate);
1734 }
1735 }
1736
1737 /* update MEM_SCRATCH buffers if needed */
r600_setup_scratch_area_for_shader(struct r600_context * rctx,struct r600_pipe_shader * shader,struct r600_scratch_buffer * scratch,unsigned ring_base_reg,unsigned item_size_reg,unsigned ring_size_reg)1738 void r600_setup_scratch_area_for_shader(struct r600_context *rctx,
1739 struct r600_pipe_shader *shader, struct r600_scratch_buffer *scratch,
1740 unsigned ring_base_reg, unsigned item_size_reg, unsigned ring_size_reg)
1741 {
1742 unsigned num_ses = rctx->screen->b.info.max_se;
1743 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
1744 unsigned nthreads = 128;
1745
1746 unsigned itemsize = shader->scratch_space_needed * 4;
1747 unsigned size = align(itemsize * nthreads * num_pipes * num_ses * 4, 256);
1748
1749 if (scratch->dirty ||
1750 unlikely(shader->scratch_space_needed != scratch->item_size ||
1751 size > scratch->size)) {
1752 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1753
1754 scratch->dirty = false;
1755
1756 if (size > scratch->size) {
1757 // Release prior one if any
1758 if (scratch->buffer) {
1759 pipe_resource_reference((struct pipe_resource**)&scratch->buffer, NULL);
1760 }
1761
1762 scratch->buffer = (struct r600_resource *)pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
1763 PIPE_USAGE_DEFAULT, size);
1764 if (scratch->buffer) {
1765 scratch->size = size;
1766 }
1767 }
1768
1769 scratch->item_size = shader->scratch_space_needed;
1770
1771 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1772 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1773 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1774
1775 // multi-SE chips need programming per SE
1776 for (unsigned se = 0; se < num_ses; se++) {
1777 struct r600_resource *rbuffer = scratch->buffer;
1778 unsigned size_per_se = size / num_ses;
1779
1780 // Direct to particular SE
1781 if (num_ses > 1) {
1782 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1783 S_0802C_INSTANCE_INDEX(0) |
1784 S_0802C_SE_INDEX(se) |
1785 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1786 S_0802C_SE_BROADCAST_WRITES(0));
1787 }
1788
1789 radeon_set_config_reg(cs, ring_base_reg, (rbuffer->gpu_address + size_per_se * se) >> 8);
1790 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1791 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1792 RADEON_USAGE_READWRITE |
1793 RADEON_PRIO_SCRATCH_BUFFER));
1794 radeon_set_context_reg(cs, item_size_reg, itemsize);
1795 radeon_set_config_reg(cs, ring_size_reg, size_per_se >> 8);
1796 }
1797
1798 // Restore broadcast mode
1799 if (num_ses > 1) {
1800 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX,
1801 S_0802C_INSTANCE_INDEX(0) |
1802 S_0802C_SE_INDEX(0) |
1803 S_0802C_INSTANCE_BROADCAST_WRITES(1) |
1804 S_0802C_SE_BROADCAST_WRITES(1));
1805 }
1806
1807 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
1808 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1809 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_VGT_FLUSH));
1810 }
1811 }
1812
r600_setup_scratch_buffers(struct r600_context * rctx)1813 void r600_setup_scratch_buffers(struct r600_context *rctx) {
1814 static const struct {
1815 unsigned ring_base;
1816 unsigned item_size;
1817 unsigned ring_size;
1818 } regs[R600_NUM_HW_STAGES] = {
1819 [R600_HW_STAGE_PS] = { R_008C68_SQ_PSTMP_RING_BASE, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, R_008C6C_SQ_PSTMP_RING_SIZE },
1820 [R600_HW_STAGE_VS] = { R_008C60_SQ_VSTMP_RING_BASE, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, R_008C64_SQ_VSTMP_RING_SIZE },
1821 [R600_HW_STAGE_GS] = { R_008C58_SQ_GSTMP_RING_BASE, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, R_008C5C_SQ_GSTMP_RING_SIZE },
1822 [R600_HW_STAGE_ES] = { R_008C50_SQ_ESTMP_RING_BASE, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, R_008C54_SQ_ESTMP_RING_SIZE }
1823 };
1824
1825 for (unsigned i = 0; i < R600_NUM_HW_STAGES; i++) {
1826 struct r600_pipe_shader *stage = rctx->hw_shader_stages[i].shader;
1827
1828 if (stage && unlikely(stage->scratch_space_needed)) {
1829 r600_setup_scratch_area_for_shader(rctx, stage,
1830 &rctx->scratch_buffers[i], regs[i].ring_base, regs[i].item_size, regs[i].ring_size);
1831 }
1832 }
1833 }
1834
1835 #define SELECT_SHADER_OR_FAIL(x) do { \
1836 r600_shader_select(ctx, rctx->x##_shader, &x##_dirty, false); \
1837 if (unlikely(!rctx->x##_shader->current)) \
1838 return false; \
1839 } while(0)
1840
1841 #define UPDATE_SHADER(hw, sw) do { \
1842 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) \
1843 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1844 } while(0)
1845
1846 #define UPDATE_SHADER_CLIP(hw, sw) do { \
1847 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1848 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1849 clip_so_current = rctx->sw##_shader->current; \
1850 } \
1851 } while(0)
1852
1853 #define UPDATE_SHADER_GS(hw, hw2, sw) do { \
1854 if (sw##_dirty || (rctx->hw_shader_stages[(hw)].shader != rctx->sw##_shader->current)) { \
1855 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], rctx->sw##_shader->current); \
1856 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw2)], rctx->sw##_shader->current->gs_copy_shader); \
1857 clip_so_current = rctx->sw##_shader->current->gs_copy_shader; \
1858 } \
1859 } while(0)
1860
1861 #define SET_NULL_SHADER(hw) do { \
1862 if (rctx->hw_shader_stages[(hw)].shader) \
1863 update_shader_atom(ctx, &rctx->hw_shader_stages[(hw)], NULL); \
1864 } while (0)
1865
r600_update_derived_state(struct r600_context * rctx)1866 static bool r600_update_derived_state(struct r600_context *rctx)
1867 {
1868 struct pipe_context * ctx = (struct pipe_context*)rctx;
1869 bool ps_dirty = false, vs_dirty = false, gs_dirty = false;
1870 bool tcs_dirty = false, tes_dirty = false, fixed_func_tcs_dirty = false;
1871 bool blend_disable;
1872 bool need_buf_const;
1873 struct r600_pipe_shader *clip_so_current = NULL;
1874
1875 if (!rctx->blitter->running)
1876 r600_update_compressed_resource_state(rctx, false);
1877
1878 SELECT_SHADER_OR_FAIL(ps);
1879
1880 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1881
1882 update_gs_block_state(rctx, rctx->gs_shader != NULL);
1883
1884 if (rctx->gs_shader)
1885 SELECT_SHADER_OR_FAIL(gs);
1886
1887 /* Hull Shader */
1888 if (rctx->tcs_shader) {
1889 SELECT_SHADER_OR_FAIL(tcs);
1890
1891 UPDATE_SHADER(EG_HW_STAGE_HS, tcs);
1892 } else if (rctx->tes_shader) {
1893 if (!rctx->fixed_func_tcs_shader) {
1894 r600_generate_fixed_func_tcs(rctx);
1895 if (!rctx->fixed_func_tcs_shader)
1896 return false;
1897
1898 }
1899 SELECT_SHADER_OR_FAIL(fixed_func_tcs);
1900
1901 UPDATE_SHADER(EG_HW_STAGE_HS, fixed_func_tcs);
1902 } else
1903 SET_NULL_SHADER(EG_HW_STAGE_HS);
1904
1905 if (rctx->tes_shader) {
1906 SELECT_SHADER_OR_FAIL(tes);
1907 }
1908
1909 SELECT_SHADER_OR_FAIL(vs);
1910
1911 if (rctx->gs_shader) {
1912 if (!rctx->shader_stages.geom_enable) {
1913 rctx->shader_stages.geom_enable = true;
1914 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1915 }
1916
1917 /* gs_shader provides GS and VS (copy shader) */
1918 UPDATE_SHADER_GS(R600_HW_STAGE_GS, R600_HW_STAGE_VS, gs);
1919
1920 /* vs_shader is used as ES */
1921
1922 if (rctx->tes_shader) {
1923 /* VS goes to LS, TES goes to ES */
1924 UPDATE_SHADER(R600_HW_STAGE_ES, tes);
1925 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1926 } else {
1927 /* vs_shader is used as ES */
1928 UPDATE_SHADER(R600_HW_STAGE_ES, vs);
1929 SET_NULL_SHADER(EG_HW_STAGE_LS);
1930 }
1931 } else {
1932 if (unlikely(rctx->hw_shader_stages[R600_HW_STAGE_GS].shader)) {
1933 SET_NULL_SHADER(R600_HW_STAGE_GS);
1934 SET_NULL_SHADER(R600_HW_STAGE_ES);
1935 rctx->shader_stages.geom_enable = false;
1936 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
1937 }
1938
1939 if (rctx->tes_shader) {
1940 /* if TES is loaded and no geometry, TES runs on hw VS, VS runs on hw LS */
1941 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, tes);
1942 UPDATE_SHADER(EG_HW_STAGE_LS, vs);
1943 } else {
1944 SET_NULL_SHADER(EG_HW_STAGE_LS);
1945 UPDATE_SHADER_CLIP(R600_HW_STAGE_VS, vs);
1946 }
1947 }
1948
1949 /*
1950 * XXX: I believe there's some fatal flaw in the dirty state logic when
1951 * enabling/disabling tes.
1952 * VS/ES share all buffer/resource/sampler slots. If TES is enabled,
1953 * it will therefore overwrite the VS slots. If it now gets disabled,
1954 * the VS needs to rebind all buffer/resource/sampler slots - not only
1955 * has TES overwritten the corresponding slots, but when the VS was
1956 * operating as LS the things with corresponding dirty bits got bound
1957 * to LS slots and won't reflect what is dirty as VS stage even if the
1958 * TES didn't overwrite it. The story for re-enabled TES is similar.
1959 * In any case, we're not allowed to submit any TES state when
1960 * TES is disabled (the gallium frontend may not do this but this looks
1961 * like an optimization to me, not something which can be relied on).
1962 */
1963
1964 /* Update clip misc state. */
1965 if (clip_so_current) {
1966 r600_update_clip_state(rctx, clip_so_current);
1967 rctx->b.streamout.enabled_stream_buffers_mask = clip_so_current->enabled_stream_buffers_mask;
1968 }
1969
1970 if (unlikely(ps_dirty || rctx->hw_shader_stages[R600_HW_STAGE_PS].shader != rctx->ps_shader->current ||
1971 rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable ||
1972 rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) {
1973
1974 bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0;
1975 if (unlikely(rctx->ps_shader &&
1976 ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1977 (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade) ||
1978 (msaa != rctx->ps_shader->current->msaa)))) {
1979
1980 if (rctx->b.gfx_level >= EVERGREEN)
1981 evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1982 else
1983 r600_update_ps_state(ctx, rctx->ps_shader->current);
1984 }
1985
1986 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs ||
1987 rctx->cb_misc_state.ps_color_export_mask != rctx->ps_shader->current->ps_color_export_mask) {
1988 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
1989 rctx->cb_misc_state.ps_color_export_mask = rctx->ps_shader->current->ps_color_export_mask;
1990 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1991 }
1992
1993 if (rctx->b.gfx_level <= R700) {
1994 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
1995
1996 if (rctx->cb_misc_state.multiwrite != multiwrite) {
1997 rctx->cb_misc_state.multiwrite = multiwrite;
1998 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1999 }
2000 }
2001
2002 r600_mark_atom_dirty(rctx, &rctx->shader_stages.atom);
2003 }
2004 UPDATE_SHADER(R600_HW_STAGE_PS, ps);
2005
2006 if (rctx->b.gfx_level >= EVERGREEN) {
2007 evergreen_update_db_shader_control(rctx);
2008 } else {
2009 r600_update_db_shader_control(rctx);
2010 }
2011
2012 /* on R600 we stuff masks + txq info into one constant buffer */
2013 /* on evergreen we only need a txq info one */
2014 if (rctx->ps_shader) {
2015 need_buf_const = rctx->ps_shader->current->shader.uses_tex_buffers || rctx->ps_shader->current->shader.has_txq_cube_array_z_comp;
2016 if (need_buf_const) {
2017 if (rctx->b.gfx_level < EVERGREEN)
2018 r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
2019 else
2020 eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
2021 }
2022 }
2023
2024 if (rctx->vs_shader) {
2025 need_buf_const = rctx->vs_shader->current->shader.uses_tex_buffers || rctx->vs_shader->current->shader.has_txq_cube_array_z_comp;
2026 if (need_buf_const) {
2027 if (rctx->b.gfx_level < EVERGREEN)
2028 r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
2029 else
2030 eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
2031 }
2032 }
2033
2034 if (rctx->gs_shader) {
2035 need_buf_const = rctx->gs_shader->current->shader.uses_tex_buffers || rctx->gs_shader->current->shader.has_txq_cube_array_z_comp;
2036 if (need_buf_const) {
2037 if (rctx->b.gfx_level < EVERGREEN)
2038 r600_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
2039 else
2040 eg_setup_buffer_constants(rctx, PIPE_SHADER_GEOMETRY);
2041 }
2042 }
2043
2044 if (rctx->tes_shader) {
2045 assert(rctx->b.gfx_level >= EVERGREEN);
2046 need_buf_const = rctx->tes_shader->current->shader.uses_tex_buffers ||
2047 rctx->tes_shader->current->shader.has_txq_cube_array_z_comp;
2048 if (need_buf_const) {
2049 eg_setup_buffer_constants(rctx, PIPE_SHADER_TESS_EVAL);
2050 }
2051 if (rctx->tcs_shader) {
2052 need_buf_const = rctx->tcs_shader->current->shader.uses_tex_buffers ||
2053 rctx->tcs_shader->current->shader.has_txq_cube_array_z_comp;
2054 if (need_buf_const) {
2055 eg_setup_buffer_constants(rctx, PIPE_SHADER_TESS_CTRL);
2056 }
2057 }
2058 }
2059
2060 r600_update_driver_const_buffers(rctx, false);
2061
2062 if (rctx->b.gfx_level < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
2063 if (!r600_adjust_gprs(rctx)) {
2064 /* discard rendering */
2065 return false;
2066 }
2067 }
2068
2069 if (rctx->b.gfx_level == EVERGREEN) {
2070 if (!evergreen_adjust_gprs(rctx)) {
2071 /* discard rendering */
2072 return false;
2073 }
2074 }
2075
2076 blend_disable = (rctx->dual_src_blend &&
2077 rctx->ps_shader->current->nr_ps_color_outputs < 2);
2078
2079 if (blend_disable != rctx->force_blend_disable) {
2080 rctx->force_blend_disable = blend_disable;
2081 r600_bind_blend_state_internal(rctx,
2082 rctx->blend_state.cso,
2083 blend_disable);
2084 }
2085
2086 return true;
2087 }
2088
r600_emit_clip_misc_state(struct r600_context * rctx,struct r600_atom * atom)2089 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2090 {
2091 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2092 struct r600_clip_misc_state *state = &rctx->clip_misc_state;
2093
2094 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
2095 state->pa_cl_clip_cntl |
2096 (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F) |
2097 S_028810_CLIP_DISABLE(state->clip_disable));
2098 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
2099 state->pa_cl_vs_out_cntl |
2100 (state->clip_plane_enable & state->clip_dist_write) |
2101 (state->cull_dist_write << 8));
2102 /* reuse needs to be set off if we write oViewport */
2103 if (rctx->b.gfx_level >= EVERGREEN)
2104 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
2105 S_028AB4_REUSE_OFF(state->vs_out_viewport));
2106 }
2107
2108 /* rast_prim is the primitive type after GS. */
r600_emit_rasterizer_prim_state(struct r600_context * rctx)2109 static inline void r600_emit_rasterizer_prim_state(struct r600_context *rctx)
2110 {
2111 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2112 enum mesa_prim rast_prim = rctx->current_rast_prim;
2113
2114 /* Skip this if not rendering lines. */
2115 if (rast_prim != MESA_PRIM_LINES &&
2116 rast_prim != MESA_PRIM_LINE_LOOP &&
2117 rast_prim != MESA_PRIM_LINE_STRIP &&
2118 rast_prim != MESA_PRIM_LINES_ADJACENCY &&
2119 rast_prim != MESA_PRIM_LINE_STRIP_ADJACENCY)
2120 return;
2121
2122 if (rast_prim == rctx->last_rast_prim)
2123 return;
2124
2125 /* For lines, reset the stipple pattern at each primitive. Otherwise,
2126 * reset the stipple pattern at each packet (line strips, line loops).
2127 */
2128 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
2129 S_028A0C_AUTO_RESET_CNTL(rast_prim == MESA_PRIM_LINES ? 1 : 2) |
2130 (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
2131 rctx->last_rast_prim = rast_prim;
2132 }
2133
r600_draw_vbo(struct pipe_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)2134 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,
2135 unsigned drawid_offset,
2136 const struct pipe_draw_indirect_info *indirect,
2137 const struct pipe_draw_start_count_bias *draws,
2138 unsigned num_draws)
2139 {
2140 if (num_draws > 1) {
2141 util_draw_multi(ctx, info, drawid_offset, indirect, draws, num_draws);
2142 return;
2143 }
2144
2145 struct r600_context *rctx = (struct r600_context *)ctx;
2146 struct pipe_resource *indexbuf = !info->index_size || info->has_user_indices ? NULL : info->index.resource;
2147 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2148 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
2149 bool has_user_indices = info->index_size && info->has_user_indices;
2150 uint64_t mask;
2151 unsigned num_patches, dirty_tex_counter, index_offset = 0;
2152 unsigned index_size = info->index_size;
2153 int index_bias;
2154 struct r600_shader_atomic combined_atomics[8];
2155 uint8_t atomic_used_mask = 0;
2156 struct pipe_stream_output_target *count_from_so = NULL;
2157
2158 if (indirect && indirect->count_from_stream_output) {
2159 count_from_so = indirect->count_from_stream_output;
2160 indirect = NULL;
2161 }
2162
2163 if (!indirect && !draws[0].count && (index_size || !count_from_so)) {
2164 return;
2165 }
2166
2167 if (unlikely(!rctx->vs_shader)) {
2168 assert(0);
2169 return;
2170 }
2171 if (unlikely(!rctx->ps_shader &&
2172 (!rctx->rasterizer || !rctx->rasterizer->rasterizer_discard))) {
2173 assert(0);
2174 return;
2175 }
2176
2177 /* make sure that the gfx ring is only one active */
2178 if (radeon_emitted(&rctx->b.dma.cs, 0)) {
2179 rctx->b.dma.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
2180 }
2181
2182 if (rctx->cmd_buf_is_compute) {
2183 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
2184 rctx->cmd_buf_is_compute = false;
2185 }
2186
2187 /* Re-emit the framebuffer state if needed. */
2188 dirty_tex_counter = p_atomic_read(&rctx->b.screen->dirty_tex_counter);
2189 if (unlikely(dirty_tex_counter != rctx->b.last_dirty_tex_counter)) {
2190 rctx->b.last_dirty_tex_counter = dirty_tex_counter;
2191 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
2192 rctx->framebuffer.do_update_surf_dirtiness = true;
2193 }
2194
2195 if (rctx->gs_shader) {
2196 /* Determine whether the GS triangle strip adjacency fix should
2197 * be applied. Rotate every other triangle if
2198 * - triangle strips with adjacency are fed to the GS and
2199 * - primitive restart is disabled (the rotation doesn't help
2200 * when the restart occurs after an odd number of triangles).
2201 */
2202 bool gs_tri_strip_adj_fix =
2203 !rctx->tes_shader &&
2204 info->mode == MESA_PRIM_TRIANGLE_STRIP_ADJACENCY &&
2205 !info->primitive_restart;
2206 if (gs_tri_strip_adj_fix != rctx->gs_tri_strip_adj_fix)
2207 rctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
2208 }
2209 if (!r600_update_derived_state(rctx)) {
2210 /* useless to render because current rendering command
2211 * can't be achieved
2212 */
2213 return;
2214 }
2215
2216 rctx->current_rast_prim = (rctx->gs_shader)? rctx->gs_shader->gs_output_prim
2217 : (rctx->tes_shader)? rctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE]
2218 : info->mode;
2219
2220 if (rctx->b.gfx_level >= EVERGREEN) {
2221 evergreen_emit_atomic_buffer_setup_count(rctx, NULL, combined_atomics, &atomic_used_mask);
2222 }
2223
2224 if (index_size) {
2225 index_offset += draws[0].start * index_size;
2226
2227 /* Translate 8-bit indices to 16-bit. */
2228 if (unlikely(index_size == 1)) {
2229 struct pipe_resource *out_buffer = NULL;
2230 unsigned out_offset;
2231 void *ptr;
2232 unsigned start, count;
2233
2234 if (likely(!indirect)) {
2235 start = 0;
2236 count = draws[0].count;
2237 }
2238 else {
2239 /* Have to get start/count from indirect buffer, slow path ahead... */
2240 struct r600_resource *indirect_resource = (struct r600_resource *)indirect->buffer;
2241 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource,
2242 PIPE_MAP_READ);
2243 if (data) {
2244 data += indirect->offset / sizeof(unsigned);
2245 start = data[2] * index_size;
2246 count = data[0];
2247 }
2248 else {
2249 start = 0;
2250 count = 0;
2251 }
2252 }
2253
2254 u_upload_alloc(ctx->stream_uploader, start, count * 2,
2255 256, &out_offset, &out_buffer, &ptr);
2256 if (unlikely(!ptr))
2257 return;
2258
2259 util_shorten_ubyte_elts_to_userptr(
2260 &rctx->b.b, info, 0, 0, index_offset, count, ptr);
2261
2262 indexbuf = out_buffer;
2263 index_offset = out_offset;
2264 index_size = 2;
2265 has_user_indices = false;
2266 }
2267
2268 /* Upload the index buffer.
2269 * The upload is skipped for small index counts on little-endian machines
2270 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
2271 * Indirect draws never use immediate indices.
2272 * Note: Instanced rendering in combination with immediate indices hangs. */
2273 if (has_user_indices && (UTIL_ARCH_BIG_ENDIAN || indirect ||
2274 info->instance_count > 1 ||
2275 draws[0].count*index_size > 20)) {
2276 unsigned start_offset = draws[0].start * index_size;
2277 indexbuf = NULL;
2278 u_upload_data(ctx->stream_uploader, start_offset,
2279 draws[0].count * index_size, 256,
2280 (char*)info->index.user + start_offset,
2281 &index_offset, &indexbuf);
2282 index_offset -= start_offset;
2283 has_user_indices = false;
2284 }
2285 index_bias = draws->index_bias;
2286 } else {
2287 index_bias = indirect ? 0 : draws[0].start;
2288 }
2289
2290 /* Set the index offset and primitive restart. */
2291 bool restart_index_changed = info->primitive_restart &&
2292 rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info->restart_index;
2293
2294 if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info->primitive_restart ||
2295 restart_index_changed ||
2296 rctx->vgt_state.vgt_indx_offset != index_bias ||
2297 (rctx->vgt_state.last_draw_was_indirect && !indirect)) {
2298 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info->primitive_restart;
2299 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info->restart_index;
2300 rctx->vgt_state.vgt_indx_offset = index_bias;
2301 r600_mark_atom_dirty(rctx, &rctx->vgt_state.atom);
2302 }
2303
2304 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
2305 if (rctx->b.gfx_level == R600) {
2306 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
2307 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2308 }
2309
2310 if (rctx->b.gfx_level >= EVERGREEN)
2311 evergreen_setup_tess_constants(rctx, info, &num_patches);
2312
2313 /* Emit states. */
2314 r600_need_cs_space(rctx, has_user_indices ? 5 : 0, true, util_bitcount(atomic_used_mask));
2315 r600_flush_emit(rctx);
2316
2317 mask = rctx->dirty_atoms;
2318 while (mask != 0) {
2319 r600_emit_atom(rctx, rctx->atoms[u_bit_scan64(&mask)]);
2320 }
2321
2322 if (rctx->b.gfx_level >= EVERGREEN) {
2323 evergreen_emit_atomic_buffer_setup(rctx, false, combined_atomics, atomic_used_mask);
2324 }
2325
2326 if (rctx->b.gfx_level == CAYMAN) {
2327 /* Copied from radeonsi. */
2328 unsigned primgroup_size = 128; /* recommended without a GS */
2329 bool ia_switch_on_eop = false;
2330 bool partial_vs_wave = false;
2331
2332 if (rctx->gs_shader)
2333 primgroup_size = 64; /* recommended with a GS */
2334
2335 if ((rctx->rasterizer && rctx->rasterizer->pa_sc_line_stipple) ||
2336 (rctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
2337 ia_switch_on_eop = true;
2338 }
2339
2340 if (r600_get_strmout_en(&rctx->b))
2341 partial_vs_wave = true;
2342
2343 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM,
2344 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
2345 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
2346 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1));
2347 }
2348
2349 if (rctx->b.gfx_level >= EVERGREEN) {
2350 uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, info,
2351 num_patches);
2352
2353 evergreen_set_ls_hs_config(rctx, cs, ls_hs_config);
2354 evergreen_set_lds_alloc(rctx, cs, rctx->lds_alloc);
2355 }
2356
2357 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
2358 * even though it should have no effect on those. */
2359 if (rctx->b.gfx_level == R600 && rctx->rasterizer) {
2360 unsigned su_sc_mode_cntl = rctx->rasterizer->pa_su_sc_mode_cntl;
2361 unsigned prim = info->mode;
2362
2363 if (rctx->gs_shader) {
2364 prim = rctx->gs_shader->gs_output_prim;
2365 }
2366 prim = r600_conv_prim_to_gs_out(prim); /* decrease the number of types to 3 */
2367
2368 if (prim == V_028A6C_OUTPRIM_TYPE_POINTLIST ||
2369 prim == V_028A6C_OUTPRIM_TYPE_LINESTRIP ||
2370 info->mode == R600_PRIM_RECTANGLE_LIST) {
2371 su_sc_mode_cntl &= C_028814_CULL_FRONT;
2372 }
2373 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl);
2374 }
2375
2376 /* Update start instance. */
2377 if (!indirect && rctx->last_start_instance != info->start_instance) {
2378 radeon_set_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
2379 rctx->last_start_instance = info->start_instance;
2380 }
2381
2382 /* Update the primitive type. */
2383 if (rctx->last_primitive_type != info->mode) {
2384 r600_emit_rasterizer_prim_state(rctx);
2385 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
2386 r600_conv_pipe_prim(info->mode));
2387
2388 rctx->last_primitive_type = info->mode;
2389 }
2390
2391 /* For each shader stage that needs to spill, set up buffer for MEM_SCRATCH */
2392 if (rctx->b.gfx_level >= EVERGREEN) {
2393 evergreen_setup_scratch_buffers(rctx);
2394 } else {
2395 r600_setup_scratch_buffers(rctx);
2396 }
2397
2398 /* Draw packets. */
2399 if (likely(!indirect)) {
2400 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
2401 radeon_emit(cs, info->instance_count);
2402 } else {
2403 uint64_t va = r600_resource(indirect->buffer)->gpu_address;
2404 assert(rctx->b.gfx_level >= EVERGREEN);
2405
2406 // Invalidate so non-indirect draw calls reset this state
2407 rctx->vgt_state.last_draw_was_indirect = true;
2408 rctx->last_start_instance = -1;
2409
2410 radeon_emit(cs, PKT3(EG_PKT3_SET_BASE, 2, 0));
2411 radeon_emit(cs, EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE);
2412 radeon_emit(cs, va);
2413 radeon_emit(cs, (va >> 32UL) & 0xFF);
2414
2415 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2416 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2417 (struct r600_resource*)indirect->buffer,
2418 RADEON_USAGE_READ |
2419 RADEON_PRIO_DRAW_INDIRECT));
2420 }
2421
2422 if (index_size) {
2423 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
2424 radeon_emit(cs, index_size == 4 ?
2425 (VGT_INDEX_32 | (UTIL_ARCH_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
2426 (VGT_INDEX_16 | (UTIL_ARCH_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)));
2427
2428 if (has_user_indices) {
2429 unsigned size_bytes = draws[0].count*index_size;
2430 unsigned size_dw = align(size_bytes, 4) / 4;
2431 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, render_cond_bit));
2432 radeon_emit(cs, draws[0].count);
2433 radeon_emit(cs, V_0287F0_DI_SRC_SEL_IMMEDIATE);
2434 memcpy(cs->current.buf + cs->current.cdw,
2435 info->index.user + draws[0].start * index_size, size_bytes);
2436 cs->current.cdw += size_dw;
2437 } else {
2438 uint64_t va = r600_resource(indexbuf)->gpu_address + index_offset;
2439
2440 if (likely(!indirect)) {
2441 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX, 3, render_cond_bit));
2442 radeon_emit(cs, va);
2443 radeon_emit(cs, (va >> 32UL) & 0xFF);
2444 radeon_emit(cs, draws[0].count);
2445 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2446 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2447 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2448 (struct r600_resource*)indexbuf,
2449 RADEON_USAGE_READ |
2450 RADEON_PRIO_INDEX_BUFFER));
2451 }
2452 else {
2453 uint32_t max_size = (indexbuf->width0 - index_offset) / index_size;
2454
2455 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BASE, 1, 0));
2456 radeon_emit(cs, va);
2457 radeon_emit(cs, (va >> 32UL) & 0xFF);
2458
2459 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2460 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2461 (struct r600_resource*)indexbuf,
2462 RADEON_USAGE_READ |
2463 RADEON_PRIO_INDEX_BUFFER));
2464
2465 radeon_emit(cs, PKT3(EG_PKT3_INDEX_BUFFER_SIZE, 0, 0));
2466 radeon_emit(cs, max_size);
2467
2468 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDEX_INDIRECT, 1, render_cond_bit));
2469 radeon_emit(cs, indirect->offset);
2470 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
2471 }
2472 }
2473 } else {
2474 if (unlikely(count_from_so)) {
2475 struct r600_so_target *t = (struct r600_so_target*)count_from_so;
2476 uint64_t va = t->buf_filled_size->gpu_address + t->buf_filled_size_offset;
2477
2478 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
2479
2480 radeon_emit(cs, PKT3(PKT3_COPY_DW, 4, 0));
2481 radeon_emit(cs, COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG);
2482 radeon_emit(cs, va & 0xFFFFFFFFUL); /* src address lo */
2483 radeon_emit(cs, (va >> 32UL) & 0xFFUL); /* src address hi */
2484 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2); /* dst register */
2485 radeon_emit(cs, 0); /* unused */
2486
2487 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2488 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
2489 t->buf_filled_size, RADEON_USAGE_READ |
2490 RADEON_PRIO_SO_FILLED_SIZE));
2491 }
2492
2493 if (likely(!indirect)) {
2494 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
2495 radeon_emit(cs, draws[0].count);
2496 }
2497 else {
2498 radeon_emit(cs, PKT3(EG_PKT3_DRAW_INDIRECT, 1, render_cond_bit));
2499 radeon_emit(cs, indirect->offset);
2500 }
2501 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2502 (count_from_so ? S_0287F0_USE_OPAQUE(1) : 0));
2503 }
2504
2505 /* SMX returns CONTEXT_DONE too early workaround */
2506 if (rctx->b.family == CHIP_R600 ||
2507 rctx->b.family == CHIP_RV610 ||
2508 rctx->b.family == CHIP_RV630 ||
2509 rctx->b.family == CHIP_RV635) {
2510 /* if we have gs shader or streamout
2511 we need to do a wait idle after every draw */
2512 if (rctx->gs_shader || r600_get_strmout_en(&rctx->b)) {
2513 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1));
2514 }
2515 }
2516
2517 /* ES ring rolling over at EOP - workaround */
2518 if (rctx->b.gfx_level == R600) {
2519 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2520 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SQ_NON_EVENT));
2521 }
2522
2523
2524 if (rctx->b.gfx_level >= EVERGREEN)
2525 evergreen_emit_atomic_buffer_save(rctx, false, combined_atomics, &atomic_used_mask);
2526
2527 if (rctx->trace_buf)
2528 eg_trace_emit(rctx);
2529
2530 if (rctx->framebuffer.do_update_surf_dirtiness) {
2531 /* Set the depth buffer as dirty. */
2532 if (rctx->framebuffer.state.zsbuf) {
2533 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
2534 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2535
2536 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2537
2538 if (rtex->surface.has_stencil)
2539 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2540 }
2541 if (rctx->framebuffer.compressed_cb_mask) {
2542 struct pipe_surface *surf;
2543 struct r600_texture *rtex;
2544 unsigned mask = rctx->framebuffer.compressed_cb_mask;
2545
2546 do {
2547 unsigned i = u_bit_scan(&mask);
2548 surf = rctx->framebuffer.state.cbufs[i];
2549 rtex = (struct r600_texture*)surf->texture;
2550
2551 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2552
2553 } while (mask);
2554 }
2555 rctx->framebuffer.do_update_surf_dirtiness = false;
2556 }
2557
2558 if (index_size && indexbuf != info->index.resource)
2559 pipe_resource_reference(&indexbuf, NULL);
2560 rctx->b.num_draw_calls++;
2561 }
2562
r600_translate_stencil_op(int s_op)2563 uint32_t r600_translate_stencil_op(int s_op)
2564 {
2565 switch (s_op) {
2566 case PIPE_STENCIL_OP_KEEP:
2567 return V_028800_STENCIL_KEEP;
2568 case PIPE_STENCIL_OP_ZERO:
2569 return V_028800_STENCIL_ZERO;
2570 case PIPE_STENCIL_OP_REPLACE:
2571 return V_028800_STENCIL_REPLACE;
2572 case PIPE_STENCIL_OP_INCR:
2573 return V_028800_STENCIL_INCR;
2574 case PIPE_STENCIL_OP_DECR:
2575 return V_028800_STENCIL_DECR;
2576 case PIPE_STENCIL_OP_INCR_WRAP:
2577 return V_028800_STENCIL_INCR_WRAP;
2578 case PIPE_STENCIL_OP_DECR_WRAP:
2579 return V_028800_STENCIL_DECR_WRAP;
2580 case PIPE_STENCIL_OP_INVERT:
2581 return V_028800_STENCIL_INVERT;
2582 default:
2583 R600_ERR("Unknown stencil op %d", s_op);
2584 assert(0);
2585 break;
2586 }
2587 return 0;
2588 }
2589
r600_translate_fill(uint32_t func)2590 uint32_t r600_translate_fill(uint32_t func)
2591 {
2592 switch(func) {
2593 case PIPE_POLYGON_MODE_FILL:
2594 return 2;
2595 case PIPE_POLYGON_MODE_LINE:
2596 return 1;
2597 case PIPE_POLYGON_MODE_POINT:
2598 return 0;
2599 default:
2600 assert(0);
2601 return 0;
2602 }
2603 }
2604
r600_tex_wrap(unsigned wrap)2605 unsigned r600_tex_wrap(unsigned wrap)
2606 {
2607 switch (wrap) {
2608 default:
2609 case PIPE_TEX_WRAP_REPEAT:
2610 return V_03C000_SQ_TEX_WRAP;
2611 case PIPE_TEX_WRAP_CLAMP:
2612 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
2613 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2614 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
2615 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2616 return V_03C000_SQ_TEX_CLAMP_BORDER;
2617 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2618 return V_03C000_SQ_TEX_MIRROR;
2619 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2620 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2621 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2622 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2623 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2624 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
2625 }
2626 }
2627
r600_tex_mipfilter(unsigned filter)2628 unsigned r600_tex_mipfilter(unsigned filter)
2629 {
2630 switch (filter) {
2631 case PIPE_TEX_MIPFILTER_NEAREST:
2632 return V_03C000_SQ_TEX_Z_FILTER_POINT;
2633 case PIPE_TEX_MIPFILTER_LINEAR:
2634 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
2635 default:
2636 case PIPE_TEX_MIPFILTER_NONE:
2637 return V_03C000_SQ_TEX_Z_FILTER_NONE;
2638 }
2639 }
2640
r600_tex_compare(unsigned compare)2641 unsigned r600_tex_compare(unsigned compare)
2642 {
2643 switch (compare) {
2644 default:
2645 case PIPE_FUNC_NEVER:
2646 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
2647 case PIPE_FUNC_LESS:
2648 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
2649 case PIPE_FUNC_EQUAL:
2650 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
2651 case PIPE_FUNC_LEQUAL:
2652 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2653 case PIPE_FUNC_GREATER:
2654 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
2655 case PIPE_FUNC_NOTEQUAL:
2656 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2657 case PIPE_FUNC_GEQUAL:
2658 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2659 case PIPE_FUNC_ALWAYS:
2660 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2661 }
2662 }
2663
wrap_mode_uses_border_color(unsigned wrap,bool linear_filter)2664 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2665 {
2666 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2667 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2668 (linear_filter &&
2669 (wrap == PIPE_TEX_WRAP_CLAMP ||
2670 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2671 }
2672
sampler_state_needs_border_color(const struct pipe_sampler_state * state)2673 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2674 {
2675 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2676 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2677
2678 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2679 state->border_color.ui[2] || state->border_color.ui[3]) &&
2680 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2681 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2682 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2683 }
2684
r600_emit_shader(struct r600_context * rctx,struct r600_atom * a)2685 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
2686 {
2687
2688 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2689 struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader;
2690
2691 if (!shader)
2692 return;
2693
2694 r600_emit_command_buffer(cs, &shader->command_buffer);
2695 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2696 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->bo,
2697 RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY));
2698 }
2699
r600_get_swizzle_combined(const unsigned char * swizzle_format,const unsigned char * swizzle_view,bool vtx)2700 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
2701 const unsigned char *swizzle_view,
2702 bool vtx)
2703 {
2704 unsigned i;
2705 unsigned char swizzle[4];
2706 unsigned result = 0;
2707 const uint32_t tex_swizzle_shift[4] = {
2708 16, 19, 22, 25,
2709 };
2710 const uint32_t vtx_swizzle_shift[4] = {
2711 3, 6, 9, 12,
2712 };
2713 const uint32_t swizzle_bit[4] = {
2714 0, 1, 2, 3,
2715 };
2716 const uint32_t *swizzle_shift = tex_swizzle_shift;
2717
2718 if (vtx)
2719 swizzle_shift = vtx_swizzle_shift;
2720
2721 if (swizzle_view) {
2722 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
2723 } else {
2724 memcpy(swizzle, swizzle_format, 4);
2725 }
2726
2727 /* Get swizzle. */
2728 for (i = 0; i < 4; i++) {
2729 switch (swizzle[i]) {
2730 case PIPE_SWIZZLE_Y:
2731 result |= swizzle_bit[1] << swizzle_shift[i];
2732 break;
2733 case PIPE_SWIZZLE_Z:
2734 result |= swizzle_bit[2] << swizzle_shift[i];
2735 break;
2736 case PIPE_SWIZZLE_W:
2737 result |= swizzle_bit[3] << swizzle_shift[i];
2738 break;
2739 case PIPE_SWIZZLE_0:
2740 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
2741 break;
2742 case PIPE_SWIZZLE_1:
2743 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
2744 break;
2745 default: /* PIPE_SWIZZLE_X */
2746 result |= swizzle_bit[0] << swizzle_shift[i];
2747 }
2748 }
2749 return result;
2750 }
2751
2752 /* texture format translate */
r600_translate_texformat(struct pipe_screen * screen,enum pipe_format format,const unsigned char * swizzle_view,uint32_t * word4_p,uint32_t * yuv_format_p,bool do_endian_swap)2753 uint32_t r600_translate_texformat(struct pipe_screen *screen,
2754 enum pipe_format format,
2755 const unsigned char *swizzle_view,
2756 uint32_t *word4_p, uint32_t *yuv_format_p,
2757 bool do_endian_swap)
2758 {
2759 struct r600_screen *rscreen = (struct r600_screen *)screen;
2760 uint32_t result = 0, word4 = 0, yuv_format = 0;
2761 const struct util_format_description *desc;
2762 bool uniform = true;
2763 bool is_srgb_valid = false;
2764 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2765 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2766 const unsigned char swizzle_xxxy[4] = {0, 0, 0, 1};
2767 const unsigned char swizzle_zyx1[4] = {2, 1, 0, 5};
2768 const unsigned char swizzle_zyxw[4] = {2, 1, 0, 3};
2769
2770 int i;
2771 const uint32_t sign_bit[4] = {
2772 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
2773 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
2774 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
2775 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
2776 };
2777
2778 /* Need to replace the specified texture formats in case of big-endian.
2779 * These formats are formats that have channels with number of bits
2780 * not divisible by 8.
2781 * Mesa conversion functions don't swap bits for those formats, and because
2782 * we transmit this over a serial bus to the GPU (PCIe), the
2783 * bit-endianness is important!!!
2784 * In case we have an "opposite" format, just use that for the swizzling
2785 * information. If we don't have such an "opposite" format, we need
2786 * to use a fixed swizzle info instead (see below)
2787 */
2788 if (format == PIPE_FORMAT_R4A4_UNORM && do_endian_swap)
2789 format = PIPE_FORMAT_A4R4_UNORM;
2790
2791 desc = util_format_description(format);
2792
2793 /* Depth and stencil swizzling is handled separately. */
2794 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
2795 /* Need to check for specific texture formats that don't have
2796 * an "opposite" format we can use. For those formats, we directly
2797 * specify the swizzling, which is the LE swizzling as defined in
2798 * u_format.csv
2799 */
2800 if (do_endian_swap) {
2801 if (format == PIPE_FORMAT_L4A4_UNORM)
2802 word4 |= r600_get_swizzle_combined(swizzle_xxxy, swizzle_view, false);
2803 else if (format == PIPE_FORMAT_B4G4R4A4_UNORM)
2804 word4 |= r600_get_swizzle_combined(swizzle_zyxw, swizzle_view, false);
2805 else if (format == PIPE_FORMAT_B4G4R4X4_UNORM || format == PIPE_FORMAT_B5G6R5_UNORM)
2806 word4 |= r600_get_swizzle_combined(swizzle_zyx1, swizzle_view, false);
2807 else
2808 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, false);
2809 } else {
2810 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, false);
2811 }
2812 }
2813
2814 /* Colorspace (return non-RGB formats directly). */
2815 switch (desc->colorspace) {
2816 /* Depth stencil formats */
2817 case UTIL_FORMAT_COLORSPACE_ZS:
2818 switch (format) {
2819 /* Depth sampler formats. */
2820 case PIPE_FORMAT_Z16_UNORM:
2821 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2822 result = FMT_16;
2823 goto out_word4;
2824 case PIPE_FORMAT_Z24X8_UNORM:
2825 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2826 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2827 result = FMT_8_24;
2828 goto out_word4;
2829 case PIPE_FORMAT_X8Z24_UNORM:
2830 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2831 if (rscreen->b.gfx_level < EVERGREEN)
2832 goto out_unknown;
2833 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, false);
2834 result = FMT_24_8;
2835 goto out_word4;
2836 case PIPE_FORMAT_Z32_FLOAT:
2837 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2838 result = FMT_32_FLOAT;
2839 goto out_word4;
2840 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2841 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2842 result = FMT_X24_8_32_FLOAT;
2843 goto out_word4;
2844 /* Stencil sampler formats. */
2845 case PIPE_FORMAT_S8_UINT:
2846 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2847 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2848 result = FMT_8;
2849 goto out_word4;
2850 case PIPE_FORMAT_X24S8_UINT:
2851 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2852 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, false);
2853 result = FMT_8_24;
2854 goto out_word4;
2855 case PIPE_FORMAT_S8X24_UINT:
2856 if (rscreen->b.gfx_level < EVERGREEN)
2857 goto out_unknown;
2858 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2859 word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, false);
2860 result = FMT_24_8;
2861 goto out_word4;
2862 case PIPE_FORMAT_X32_S8X24_UINT:
2863 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2864 word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, false);
2865 result = FMT_X24_8_32_FLOAT;
2866 goto out_word4;
2867 default:
2868 goto out_unknown;
2869 }
2870
2871 case UTIL_FORMAT_COLORSPACE_YUV:
2872 yuv_format |= (1 << 30);
2873 switch (format) {
2874 case PIPE_FORMAT_UYVY:
2875 case PIPE_FORMAT_YUYV:
2876 default:
2877 break;
2878 }
2879 goto out_unknown; /* XXX */
2880
2881 case UTIL_FORMAT_COLORSPACE_SRGB:
2882 word4 |= S_038010_FORCE_DEGAMMA(1);
2883 break;
2884
2885 default:
2886 break;
2887 }
2888
2889 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
2890 switch (format) {
2891 case PIPE_FORMAT_RGTC1_SNORM:
2892 case PIPE_FORMAT_LATC1_SNORM:
2893 word4 |= sign_bit[0];
2894 FALLTHROUGH;
2895 case PIPE_FORMAT_RGTC1_UNORM:
2896 case PIPE_FORMAT_LATC1_UNORM:
2897 result = FMT_BC4;
2898 goto out_word4;
2899 case PIPE_FORMAT_RGTC2_SNORM:
2900 case PIPE_FORMAT_LATC2_SNORM:
2901 word4 |= sign_bit[0] | sign_bit[1];
2902 FALLTHROUGH;
2903 case PIPE_FORMAT_RGTC2_UNORM:
2904 case PIPE_FORMAT_LATC2_UNORM:
2905 result = FMT_BC5;
2906 goto out_word4;
2907 default:
2908 goto out_unknown;
2909 }
2910 }
2911
2912 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
2913 switch (format) {
2914 case PIPE_FORMAT_DXT1_RGB:
2915 case PIPE_FORMAT_DXT1_RGBA:
2916 case PIPE_FORMAT_DXT1_SRGB:
2917 case PIPE_FORMAT_DXT1_SRGBA:
2918 result = FMT_BC1;
2919 is_srgb_valid = true;
2920 goto out_word4;
2921 case PIPE_FORMAT_DXT3_RGBA:
2922 case PIPE_FORMAT_DXT3_SRGBA:
2923 result = FMT_BC2;
2924 is_srgb_valid = true;
2925 goto out_word4;
2926 case PIPE_FORMAT_DXT5_RGBA:
2927 case PIPE_FORMAT_DXT5_SRGBA:
2928 result = FMT_BC3;
2929 is_srgb_valid = true;
2930 goto out_word4;
2931 default:
2932 goto out_unknown;
2933 }
2934 }
2935
2936 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
2937 if (rscreen->b.gfx_level < EVERGREEN)
2938 goto out_unknown;
2939
2940 switch (format) {
2941 case PIPE_FORMAT_BPTC_RGBA_UNORM:
2942 case PIPE_FORMAT_BPTC_SRGBA:
2943 result = FMT_BC7;
2944 is_srgb_valid = true;
2945 goto out_word4;
2946 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2947 word4 |= sign_bit[0] | sign_bit[1] | sign_bit[2];
2948 FALLTHROUGH;
2949 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
2950 result = FMT_BC6;
2951 goto out_word4;
2952 default:
2953 goto out_unknown;
2954 }
2955 }
2956
2957 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2958 switch (format) {
2959 case PIPE_FORMAT_R8G8_B8G8_UNORM:
2960 case PIPE_FORMAT_G8R8_B8R8_UNORM:
2961 result = FMT_GB_GR;
2962 goto out_word4;
2963 case PIPE_FORMAT_G8R8_G8B8_UNORM:
2964 case PIPE_FORMAT_R8G8_R8B8_UNORM:
2965 result = FMT_BG_RG;
2966 goto out_word4;
2967 default:
2968 goto out_unknown;
2969 }
2970 }
2971
2972 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
2973 result = FMT_5_9_9_9_SHAREDEXP;
2974 goto out_word4;
2975 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
2976 result = FMT_10_11_11_FLOAT;
2977 goto out_word4;
2978 }
2979
2980
2981 for (i = 0; i < desc->nr_channels; i++) {
2982 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2983 word4 |= sign_bit[i];
2984 }
2985 }
2986
2987 /* R8G8Bx_SNORM - XXX CxV8U8 */
2988
2989 /* See whether the components are of the same size. */
2990 for (i = 1; i < desc->nr_channels; i++) {
2991 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
2992 }
2993
2994 /* Non-uniform formats. */
2995 if (!uniform) {
2996 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
2997 desc->channel[0].pure_integer)
2998 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
2999 switch(desc->nr_channels) {
3000 case 3:
3001 if (desc->channel[0].size == 5 &&
3002 desc->channel[1].size == 6 &&
3003 desc->channel[2].size == 5) {
3004 result = FMT_5_6_5;
3005 goto out_word4;
3006 }
3007 goto out_unknown;
3008 case 4:
3009 if (desc->channel[0].size == 5 &&
3010 desc->channel[1].size == 5 &&
3011 desc->channel[2].size == 5 &&
3012 desc->channel[3].size == 1) {
3013 result = FMT_1_5_5_5;
3014 goto out_word4;
3015 }
3016 if (desc->channel[0].size == 10 &&
3017 desc->channel[1].size == 10 &&
3018 desc->channel[2].size == 10 &&
3019 desc->channel[3].size == 2) {
3020 result = FMT_2_10_10_10;
3021 goto out_word4;
3022 }
3023 goto out_unknown;
3024 }
3025 goto out_unknown;
3026 }
3027
3028 i = util_format_get_first_non_void_channel(format);
3029 if (i == -1)
3030 goto out_unknown;
3031
3032 /* uniform formats */
3033 switch (desc->channel[i].type) {
3034 case UTIL_FORMAT_TYPE_UNSIGNED:
3035 case UTIL_FORMAT_TYPE_SIGNED:
3036 #if 0
3037 if (!desc->channel[i].normalized &&
3038 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
3039 goto out_unknown;
3040 }
3041 #endif
3042 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
3043 desc->channel[i].pure_integer)
3044 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
3045
3046 switch (desc->channel[i].size) {
3047 case 4:
3048 switch (desc->nr_channels) {
3049 case 2:
3050 result = FMT_4_4;
3051 goto out_word4;
3052 case 4:
3053 result = FMT_4_4_4_4;
3054 goto out_word4;
3055 }
3056 goto out_unknown;
3057 case 8:
3058 switch (desc->nr_channels) {
3059 case 1:
3060 result = FMT_8;
3061 is_srgb_valid = true;
3062 goto out_word4;
3063 case 2:
3064 result = FMT_8_8;
3065 goto out_word4;
3066 case 4:
3067 result = FMT_8_8_8_8;
3068 is_srgb_valid = true;
3069 goto out_word4;
3070 }
3071 goto out_unknown;
3072 case 16:
3073 switch (desc->nr_channels) {
3074 case 1:
3075 result = FMT_16;
3076 goto out_word4;
3077 case 2:
3078 result = FMT_16_16;
3079 goto out_word4;
3080 case 4:
3081 result = FMT_16_16_16_16;
3082 goto out_word4;
3083 }
3084 goto out_unknown;
3085 case 32:
3086 switch (desc->nr_channels) {
3087 case 1:
3088 result = FMT_32;
3089 goto out_word4;
3090 case 2:
3091 result = FMT_32_32;
3092 goto out_word4;
3093 case 4:
3094 result = FMT_32_32_32_32;
3095 goto out_word4;
3096 }
3097 }
3098 goto out_unknown;
3099
3100 case UTIL_FORMAT_TYPE_FLOAT:
3101 switch (desc->channel[i].size) {
3102 case 16:
3103 switch (desc->nr_channels) {
3104 case 1:
3105 result = FMT_16_FLOAT;
3106 goto out_word4;
3107 case 2:
3108 result = FMT_16_16_FLOAT;
3109 goto out_word4;
3110 case 4:
3111 result = FMT_16_16_16_16_FLOAT;
3112 goto out_word4;
3113 }
3114 goto out_unknown;
3115 case 32:
3116 switch (desc->nr_channels) {
3117 case 1:
3118 result = FMT_32_FLOAT;
3119 goto out_word4;
3120 case 2:
3121 result = FMT_32_32_FLOAT;
3122 goto out_word4;
3123 case 4:
3124 result = FMT_32_32_32_32_FLOAT;
3125 goto out_word4;
3126 }
3127 }
3128 goto out_unknown;
3129 }
3130
3131 out_word4:
3132
3133 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
3134 return ~0;
3135 if (word4_p)
3136 *word4_p = word4;
3137 if (yuv_format_p)
3138 *yuv_format_p = yuv_format;
3139 return result;
3140 out_unknown:
3141 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
3142 return ~0;
3143 }
3144
r600_translate_colorformat(enum amd_gfx_level chip,enum pipe_format format,bool do_endian_swap)3145 uint32_t r600_translate_colorformat(enum amd_gfx_level chip, enum pipe_format format,
3146 bool do_endian_swap)
3147 {
3148 const struct util_format_description *desc = util_format_description(format);
3149 int channel = util_format_get_first_non_void_channel(format);
3150 bool is_float;
3151
3152 #define HAS_SIZE(x,y,z,w) \
3153 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
3154 desc->channel[2].size == (z) && desc->channel[3].size == (w))
3155
3156 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
3157 return V_0280A0_COLOR_10_11_11_FLOAT;
3158
3159 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
3160 channel == -1)
3161 return ~0U;
3162
3163 is_float = desc->channel[channel].type == UTIL_FORMAT_TYPE_FLOAT;
3164
3165 switch (desc->nr_channels) {
3166 case 1:
3167 switch (desc->channel[0].size) {
3168 case 8:
3169 return V_0280A0_COLOR_8;
3170 case 16:
3171 if (is_float)
3172 return V_0280A0_COLOR_16_FLOAT;
3173 else
3174 return V_0280A0_COLOR_16;
3175 case 32:
3176 if (is_float)
3177 return V_0280A0_COLOR_32_FLOAT;
3178 else
3179 return V_0280A0_COLOR_32;
3180 }
3181 break;
3182 case 2:
3183 if (desc->channel[0].size == desc->channel[1].size) {
3184 switch (desc->channel[0].size) {
3185 case 4:
3186 if (chip <= R700)
3187 return V_0280A0_COLOR_4_4;
3188 else
3189 return ~0U; /* removed on Evergreen */
3190 case 8:
3191 return V_0280A0_COLOR_8_8;
3192 case 16:
3193 if (is_float)
3194 return V_0280A0_COLOR_16_16_FLOAT;
3195 else
3196 return V_0280A0_COLOR_16_16;
3197 case 32:
3198 if (is_float)
3199 return V_0280A0_COLOR_32_32_FLOAT;
3200 else
3201 return V_0280A0_COLOR_32_32;
3202 }
3203 } else if (HAS_SIZE(8,24,0,0)) {
3204 return (do_endian_swap ? V_0280A0_COLOR_8_24 : V_0280A0_COLOR_24_8);
3205 } else if (HAS_SIZE(24,8,0,0)) {
3206 return V_0280A0_COLOR_8_24;
3207 }
3208 break;
3209 case 3:
3210 if (HAS_SIZE(5,6,5,0)) {
3211 return V_0280A0_COLOR_5_6_5;
3212 } else if (HAS_SIZE(32,8,24,0)) {
3213 return V_0280A0_COLOR_X24_8_32_FLOAT;
3214 }
3215 break;
3216 case 4:
3217 if (desc->channel[0].size == desc->channel[1].size &&
3218 desc->channel[0].size == desc->channel[2].size &&
3219 desc->channel[0].size == desc->channel[3].size) {
3220 switch (desc->channel[0].size) {
3221 case 4:
3222 return V_0280A0_COLOR_4_4_4_4;
3223 case 8:
3224 return V_0280A0_COLOR_8_8_8_8;
3225 case 16:
3226 if (is_float)
3227 return V_0280A0_COLOR_16_16_16_16_FLOAT;
3228 else
3229 return V_0280A0_COLOR_16_16_16_16;
3230 case 32:
3231 if (is_float)
3232 return V_0280A0_COLOR_32_32_32_32_FLOAT;
3233 else
3234 return V_0280A0_COLOR_32_32_32_32;
3235 }
3236 } else if (HAS_SIZE(5,5,5,1)) {
3237 return V_0280A0_COLOR_1_5_5_5;
3238 } else if (HAS_SIZE(10,10,10,2)) {
3239 return V_0280A0_COLOR_2_10_10_10;
3240 }
3241 break;
3242 }
3243 return ~0U;
3244 }
3245
r600_colorformat_endian_swap(uint32_t colorformat,bool do_endian_swap)3246 uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
3247 {
3248 if (UTIL_ARCH_BIG_ENDIAN) {
3249 switch(colorformat) {
3250 /* 8-bit buffers. */
3251 case V_0280A0_COLOR_4_4:
3252 case V_0280A0_COLOR_8:
3253 return ENDIAN_NONE;
3254
3255 /* 16-bit buffers. */
3256 case V_0280A0_COLOR_8_8:
3257 /*
3258 * No need to do endian swaps on array formats,
3259 * as mesa<-->pipe formats conversion take into account
3260 * the endianness
3261 */
3262 return ENDIAN_NONE;
3263
3264 case V_0280A0_COLOR_5_6_5:
3265 case V_0280A0_COLOR_1_5_5_5:
3266 case V_0280A0_COLOR_4_4_4_4:
3267 case V_0280A0_COLOR_16:
3268 return (do_endian_swap ? ENDIAN_8IN16 : ENDIAN_NONE);
3269
3270 /* 32-bit buffers. */
3271 case V_0280A0_COLOR_8_8_8_8:
3272 /*
3273 * No need to do endian swaps on array formats,
3274 * as mesa<-->pipe formats conversion take into account
3275 * the endianness
3276 */
3277 return ENDIAN_NONE;
3278
3279 case V_0280A0_COLOR_2_10_10_10:
3280 case V_0280A0_COLOR_8_24:
3281 case V_0280A0_COLOR_24_8:
3282 case V_0280A0_COLOR_32_FLOAT:
3283 return (do_endian_swap ? ENDIAN_8IN32 : ENDIAN_NONE);
3284
3285 case V_0280A0_COLOR_16_16_FLOAT:
3286 case V_0280A0_COLOR_16_16:
3287 return ENDIAN_8IN16;
3288
3289 /* 64-bit buffers. */
3290 case V_0280A0_COLOR_16_16_16_16:
3291 case V_0280A0_COLOR_16_16_16_16_FLOAT:
3292 return ENDIAN_8IN16;
3293
3294 case V_0280A0_COLOR_32_32_FLOAT:
3295 case V_0280A0_COLOR_32_32:
3296 case V_0280A0_COLOR_X24_8_32_FLOAT:
3297 return ENDIAN_8IN32;
3298
3299 /* 128-bit buffers. */
3300 case V_0280A0_COLOR_32_32_32_32_FLOAT:
3301 case V_0280A0_COLOR_32_32_32_32:
3302 return ENDIAN_8IN32;
3303 default:
3304 return ENDIAN_NONE; /* Unsupported. */
3305 }
3306 } else {
3307 return ENDIAN_NONE;
3308 }
3309 }
3310
r600_invalidate_buffer(struct pipe_context * ctx,struct pipe_resource * buf)3311 static void r600_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource *buf)
3312 {
3313 struct r600_context *rctx = (struct r600_context*)ctx;
3314 struct r600_resource *rbuffer = r600_resource(buf);
3315 unsigned i, shader, mask;
3316 struct r600_pipe_sampler_view *view;
3317
3318 /* Reallocate the buffer in the same pipe_resource. */
3319 r600_alloc_resource(&rctx->screen->b, rbuffer);
3320
3321 /* We changed the buffer, now we need to bind it where the old one was bound. */
3322 /* Vertex buffers. */
3323 mask = rctx->vertex_buffer_state.enabled_mask;
3324 while (mask) {
3325 i = u_bit_scan(&mask);
3326 if (rctx->vertex_buffer_state.vb[i].buffer.resource == &rbuffer->b.b) {
3327 rctx->vertex_buffer_state.dirty_mask |= 1 << i;
3328 r600_vertex_buffers_dirty(rctx);
3329 }
3330 }
3331 /* Streamout buffers. */
3332 for (i = 0; i < rctx->b.streamout.num_targets; i++) {
3333 if (rctx->b.streamout.targets[i] &&
3334 rctx->b.streamout.targets[i]->b.buffer == &rbuffer->b.b) {
3335 if (rctx->b.streamout.begin_emitted) {
3336 r600_emit_streamout_end(&rctx->b);
3337 }
3338 rctx->b.streamout.append_bitmask = rctx->b.streamout.enabled_mask;
3339 r600_streamout_buffers_dirty(&rctx->b);
3340 }
3341 }
3342
3343 /* Constant buffers. */
3344 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3345 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
3346 bool found = false;
3347 uint32_t mask = state->enabled_mask;
3348
3349 while (mask) {
3350 unsigned i = u_bit_scan(&mask);
3351 if (state->cb[i].buffer == &rbuffer->b.b) {
3352 found = true;
3353 state->dirty_mask |= 1 << i;
3354 }
3355 }
3356 if (found) {
3357 r600_constant_buffers_dirty(rctx, state);
3358 }
3359 }
3360
3361 /* Texture buffer objects - update the virtual addresses in descriptors. */
3362 LIST_FOR_EACH_ENTRY(view, &rctx->texture_buffers, list) {
3363 if (view->base.texture == &rbuffer->b.b) {
3364 uint64_t offset = view->base.u.buf.offset;
3365 uint64_t va = rbuffer->gpu_address + offset;
3366
3367 view->tex_resource_words[0] = va;
3368 view->tex_resource_words[2] &= C_038008_BASE_ADDRESS_HI;
3369 view->tex_resource_words[2] |= S_038008_BASE_ADDRESS_HI(va >> 32);
3370 }
3371 }
3372 /* Texture buffer objects - make bindings dirty if needed. */
3373 for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) {
3374 struct r600_samplerview_state *state = &rctx->samplers[shader].views;
3375 bool found = false;
3376 uint32_t mask = state->enabled_mask;
3377
3378 while (mask) {
3379 unsigned i = u_bit_scan(&mask);
3380 if (state->views[i]->base.texture == &rbuffer->b.b) {
3381 found = true;
3382 state->dirty_mask |= 1 << i;
3383 }
3384 }
3385 if (found) {
3386 r600_sampler_views_dirty(rctx, state);
3387 }
3388 }
3389
3390 /* SSBOs */
3391 struct r600_image_state *istate = &rctx->fragment_buffers;
3392 {
3393 uint32_t mask = istate->enabled_mask;
3394 bool found = false;
3395 while (mask) {
3396 unsigned i = u_bit_scan(&mask);
3397 if (istate->views[i].base.resource == &rbuffer->b.b) {
3398 found = true;
3399 istate->dirty_mask |= 1 << i;
3400 }
3401 }
3402 if (found) {
3403 r600_mark_atom_dirty(rctx, &istate->atom);
3404 }
3405 }
3406
3407 }
3408
r600_set_active_query_state(struct pipe_context * ctx,bool enable)3409 static void r600_set_active_query_state(struct pipe_context *ctx, bool enable)
3410 {
3411 struct r600_context *rctx = (struct r600_context*)ctx;
3412
3413 /* Pipeline stat & streamout queries. */
3414 if (enable) {
3415 rctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
3416 rctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
3417 } else {
3418 rctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
3419 rctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
3420 }
3421
3422 /* Occlusion queries. */
3423 if (rctx->db_misc_state.occlusion_queries_disabled != !enable) {
3424 rctx->db_misc_state.occlusion_queries_disabled = !enable;
3425 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3426 }
3427 }
3428
r600_need_gfx_cs_space(struct pipe_context * ctx,unsigned num_dw,bool include_draw_vbo)3429 static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3430 bool include_draw_vbo)
3431 {
3432 r600_need_cs_space((struct r600_context*)ctx, num_dw, include_draw_vbo, 0);
3433 }
3434
3435 /* keep this at the end of this file, please */
r600_init_common_state_functions(struct r600_context * rctx)3436 void r600_init_common_state_functions(struct r600_context *rctx)
3437 {
3438 rctx->b.b.create_fs_state = r600_create_ps_state;
3439 rctx->b.b.create_vs_state = r600_create_vs_state;
3440 rctx->b.b.create_gs_state = r600_create_gs_state;
3441 rctx->b.b.create_tcs_state = r600_create_tcs_state;
3442 rctx->b.b.create_tes_state = r600_create_tes_state;
3443 rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
3444 rctx->b.b.bind_blend_state = r600_bind_blend_state;
3445 rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
3446 rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
3447 rctx->b.b.bind_fs_state = r600_bind_ps_state;
3448 rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
3449 rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
3450 rctx->b.b.bind_vs_state = r600_bind_vs_state;
3451 rctx->b.b.bind_gs_state = r600_bind_gs_state;
3452 rctx->b.b.bind_tcs_state = r600_bind_tcs_state;
3453 rctx->b.b.bind_tes_state = r600_bind_tes_state;
3454 rctx->b.b.delete_blend_state = r600_delete_blend_state;
3455 rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
3456 rctx->b.b.delete_fs_state = r600_delete_ps_state;
3457 rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
3458 rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
3459 rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
3460 rctx->b.b.delete_vs_state = r600_delete_vs_state;
3461 rctx->b.b.delete_gs_state = r600_delete_gs_state;
3462 rctx->b.b.delete_tcs_state = r600_delete_tcs_state;
3463 rctx->b.b.delete_tes_state = r600_delete_tes_state;
3464 rctx->b.b.set_blend_color = r600_set_blend_color;
3465 rctx->b.b.set_clip_state = r600_set_clip_state;
3466 rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
3467 rctx->b.b.set_sample_mask = r600_set_sample_mask;
3468 rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
3469 rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
3470 rctx->b.b.set_sampler_views = r600_set_sampler_views;
3471 rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
3472 rctx->b.b.memory_barrier = r600_memory_barrier;
3473 rctx->b.b.texture_barrier = r600_texture_barrier;
3474 rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
3475 rctx->b.b.set_active_query_state = r600_set_active_query_state;
3476
3477 rctx->b.b.draw_vbo = r600_draw_vbo;
3478 rctx->b.invalidate_buffer = r600_invalidate_buffer;
3479 rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
3480 }
3481