1 /* -*- mesa-c++ -*- 2 * 3 * Copyright (c) 2018-2019 Collabora LTD 4 * 5 * Author: Gert Wollny <gert.wollny@collabora.com> 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * on the rights to use, copy, modify, merge, publish, distribute, sub 11 * license, and/or sell copies of the Software, and to permit persons to whom 12 * the Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 */ 26 27 #ifndef sfn_defines_h 28 #define sfn_defines_h 29 30 #include "../r600_isa.h" 31 #include "amd_family.h" 32 namespace r600 { 33 34 enum EGWSOpCode { 35 cf_sema_v = 0, 36 cf_sema_p = 1, 37 cf_gws_barrier = 2, 38 cf_gws_init = 3, 39 }; 40 41 /* CF ALU instructions [29:26], highest bit always set. */ 42 enum ECFAluOpCode { 43 cf_alu_undefined = 0, 44 cf_alu = CF_OP_ALU, 45 cf_alu_push_before = CF_OP_ALU_PUSH_BEFORE, 46 cf_alu_pop_after = CF_OP_ALU_POP_AFTER, 47 cf_alu_pop2_after = CF_OP_ALU_POP2_AFTER, 48 cf_alu_extended = CF_OP_ALU_EXT, 49 cf_alu_continue = CF_OP_ALU_CONTINUE, 50 cf_alu_break = CF_OP_ALU_BREAK, 51 cf_alu_else_after = CF_OP_ALU_ELSE_AFTER, 52 }; 53 54 enum ECFAluOpCodeEG { 55 eg_cf_alu_undefined = 0, 56 eg_cf_alu = 8, 57 eg_cf_alu_push_before = 9, 58 eg_cf_alu_pop_after = 10, 59 eg_cf_alu_pop2_after = 11, 60 eg_cf_alu_extended = 12, 61 eg_cf_alu_continue = 13, 62 eg_cf_alu_break = 14, 63 eg_cf_alu_else_after = 15, 64 }; 65 66 enum ECFOpCode { 67 cf_nop = CF_OP_NOP, 68 cf_tc = CF_OP_TEX, 69 cf_vc = CF_OP_VTX, 70 cf_gds = CF_OP_GDS, 71 cf_loop_start = CF_OP_LOOP_START, 72 cf_loop_end = CF_OP_LOOP_END, 73 cf_loop_start_dx10 = CF_OP_LOOP_START_DX10, 74 cf_loop_start_no_al = CF_OP_LOOP_START_NO_AL, 75 cf_loop_continue = CF_OP_LOOP_CONTINUE, 76 cf_loop_break = CF_OP_LOOP_BREAK, 77 cf_jump = CF_OP_JUMP, 78 cf_push = CF_OP_PUSH, 79 cf_else = CF_OP_ELSE, 80 cf_pop = CF_OP_POP, 81 /* 15 - 17 reserved */ 82 cf_call = CF_OP_CALL, 83 cf_call_fs = CF_OP_CALL_FS, 84 cf_return = CF_OP_RET, 85 cf_emit_vertex = CF_OP_EMIT_VERTEX, 86 cf_emit_cut_vertex = CF_OP_EMIT_CUT_VERTEX, 87 cf_cut_vertex = CF_OP_CUT_VERTEX, 88 cf_kill = CF_OP_KILL, 89 /* 25 reserved */ 90 cf_wait_ack = CF_OP_WAIT_ACK, 91 cf_tc_ack = CF_OP_TEX_ACK, 92 cf_vc_ack = CF_OP_VTX_ACK, 93 cf_jump_table = CF_OP_JUMPTABLE, 94 cf_global_wave_sync = CF_OP_WAVE_SYNC, 95 cf_halt = CF_OP_HALT, 96 /* gap 32-63*/ 97 cf_mem_stream0_buf0 = CF_OP_MEM_STREAM0_BUF0, 98 cf_mem_stream0_buf1 = CF_OP_MEM_STREAM0_BUF1, 99 cf_mem_stream0_buf2 = CF_OP_MEM_STREAM0_BUF2, 100 cf_mem_stream0_buf3 = CF_OP_MEM_STREAM0_BUF3, 101 102 cf_mem_stream1_buf0 = CF_OP_MEM_STREAM1_BUF0, 103 cf_mem_stream1_buf1 = CF_OP_MEM_STREAM1_BUF1, 104 cf_mem_stream1_buf2 = CF_OP_MEM_STREAM1_BUF2, 105 cf_mem_stream1_buf3 = CF_OP_MEM_STREAM1_BUF3, 106 107 cf_mem_stream2_buf0 = CF_OP_MEM_STREAM2_BUF0, 108 cf_mem_stream2_buf1 = CF_OP_MEM_STREAM2_BUF1, 109 cf_mem_stream2_buf2 = CF_OP_MEM_STREAM2_BUF2, 110 cf_mem_stream2_buf3 = CF_OP_MEM_STREAM2_BUF3, 111 112 cf_mem_stream3_buf0 = CF_OP_MEM_STREAM3_BUF0, 113 cf_mem_stream3_buf1 = CF_OP_MEM_STREAM3_BUF1, 114 cf_mem_stream3_buf2 = CF_OP_MEM_STREAM3_BUF2, 115 cf_mem_stream3_buf3 = CF_OP_MEM_STREAM3_BUF3, 116 117 cf_mem_write_scratch = CF_OP_MEM_SCRATCH, 118 /* reserved 81 */ 119 cf_mem_ring = CF_OP_MEM_RING, 120 cf_export = CF_OP_EXPORT, 121 cf_export_done = CF_OP_EXPORT_DONE, 122 cf_mem_export = CF_OP_MEM_EXPORT, 123 cf_mem_rat = CF_OP_MEM_RAT, 124 cf_mem_rat_cacheless = CF_OP_MEM_RAT_NOCACHE, 125 126 cf_mem_ring1 = CF_OP_MEM_RING1, 127 cf_mem_ring2 = CF_OP_MEM_RING2, 128 cf_mem_ring3 = CF_OP_MEM_RING3, 129 cf_mem_export_combined = CF_OP_MEM_MEM_COMBINED, 130 cf_mem_rat_combined_cacheless = CF_OP_MEM_RAT_COMBINED_NOCACHE 131 }; 132 133 enum ECFOpCodeEG { 134 eg_cf_nop = 0, 135 eg_cf_tc = 1, 136 eg_cf_vc = 2, 137 eg_cf_gds = 3, 138 eg_cf_loop_start = 4, 139 eg_cf_loop_end = 5, 140 eg_cf_loop_start_dx10 = 6, 141 eg_cf_loop_start_no_al = 7, 142 eg_cf_loop_continue = 8, 143 eg_cf_loop_break = 9, 144 eg_cf_jump = 10, 145 eg_cf_push = 11, 146 eg_cf_else = 13, 147 eg_cf_pop = 14, 148 /* 15 - 17 reserved */ 149 eg_cf_call = 18, 150 eg_cf_call_fs, 151 eg_cf_return, 152 eg_cf_emit_vertex, 153 eg_cf_emit_cut_vertex, 154 eg_cf_cut_vertex, 155 eg_cf_kill, 156 /* 25 reserved */ 157 eg_cf_wait_ack = 26, 158 eg_cf_tc_ack, 159 eg_cf_vc_ack, 160 eg_cf_jump_table, 161 eg_cf_global_wave_sync, 162 eg_cf_halt, 163 /* gap 32-63*/ 164 eg_cf_mem_stream0_buf0 = 64, 165 eg_cf_mem_stream0_buf1, 166 eg_cf_mem_stream0_buf2, 167 eg_cf_mem_stream0_buf3, 168 169 eg_cf_mem_stream1_buf0, 170 eg_cf_mem_stream1_buf1, 171 eg_cf_mem_stream1_buf2, 172 eg_cf_mem_stream1_buf3, 173 174 eg_cf_mem_stream2_buf0, 175 eg_cf_mem_stream2_buf1, 176 eg_cf_mem_stream2_buf2, 177 eg_cf_mem_stream2_buf3, 178 179 eg_cf_mem_stream3_buf0, 180 eg_cf_mem_stream3_buf1, 181 eg_cf_mem_stream3_buf2, 182 eg_cf_mem_stream3_buf3, 183 184 eg_cf_mem_write_scratch, 185 /* reserved 81 */ 186 eg_cf_mem_ring = 82, 187 eg_cf_export, 188 eg_cf_export_done, 189 eg_cf_mem_export, 190 eg_cf_mem_rat, 191 eg_cf_mem_rat_cacheless, 192 193 eg_cf_mem_ring1, 194 eg_cf_mem_ring2, 195 eg_cf_mem_ring3, 196 eg_cf_mem_export_combined, 197 eg_cf_mem_rat_combined_cacheless 198 }; 199 200 enum EVFetchInstr { 201 vc_fetch = FETCH_OP_VFETCH, 202 vc_semantic = FETCH_OP_SEMFETCH, 203 vc_get_buf_resinfo = FETCH_OP_GET_BUFFER_RESINFO, 204 vc_read_scratch = FETCH_OP_READ_SCRATCH, 205 vc_unknown 206 }; 207 208 enum EVFetchType { 209 vertex_data = 0, 210 instance_data = 1, 211 no_index_offset = 2 212 }; 213 214 enum EVTXDataFormat { 215 fmt_invalid = 0, 216 fmt_8 = 1, 217 fmt_4_4 = 2, 218 fmt_3_3_2 = 3, 219 fmt_reserved_4 = 4, 220 fmt_16 = 5, 221 fmt_16_float = 6, 222 fmt_8_8 = 7, 223 fmt_5_6_5 = 8, 224 fmt_6_5_5 = 9, 225 fmt_1_5_5_5 = 10, 226 fmt_4_4_4_4 = 11, 227 fmt_5_5_5_1 = 12, 228 fmt_32 = 13, 229 fmt_32_float = 14, 230 fmt_16_16 = 15, 231 fmt_16_16_float = 16, 232 fmt_8_24 = 17, 233 fmt_8_24_float = 18, 234 fmt_24_8 = 19, 235 fmt_24_8_float = 20, 236 fmt_10_11_11 = 21, 237 fmt_10_11_11_float = 22, 238 fmt_11_11_10 = 23, 239 fmt_11_11_10_float = 24, 240 fmt_2_10_10_10 = 25, 241 fmt_8_8_8_8 = 26, 242 fmt_10_10_10_2 = 27, 243 fmt_x24_8_32_float = 28, 244 fmt_32_32 = 29, 245 fmt_32_32_float = 30, 246 fmt_16_16_16_16 = 31, 247 fmt_16_16_16_16_float = 32, 248 fmt_reserved_33 = 33, 249 fmt_32_32_32_32 = 34, 250 fmt_32_32_32_32_float = 35, 251 fmt_reserved_36 = 36, 252 fmt_1 = 37, 253 fmt_1_reversed = 38, 254 fmt_gb_gr = 39, 255 fmt_bg_rg = 40, 256 fmt_32_as_8 = 41, 257 fmt_32_as_8_8 = 42, 258 fmt_5_9_9_9_sharedexp = 43, 259 fmt_8_8_8 = 44, 260 fmt_16_16_16 = 45, 261 fmt_16_16_16_float = 46, 262 fmt_32_32_32 = 47, 263 fmt_32_32_32_float = 48, 264 fmt_bc1 = 49, 265 fmt_bc2 = 50, 266 fmt_bc3 = 51, 267 fmt_bc4 = 52, 268 fmt_bc5 = 53, 269 fmt_apc0 = 54, 270 fmt_apc1 = 55, 271 fmt_apc2 = 56, 272 fmt_apc3 = 57, 273 fmt_apc4 = 58, 274 fmt_apc5 = 59, 275 fmt_apc6 = 60, 276 fmt_apc7 = 61, 277 fmt_ctx1 = 62, 278 fmt_reserved_63 = 63 279 }; 280 281 enum EVFetchNumFormat { 282 vtx_nf_norm = 0, 283 vtx_nf_int = 1, 284 vtx_nf_scaled = 2 285 }; 286 287 enum EVFetchEndianSwap { 288 vtx_es_none = 0, 289 vtx_es_8in16 = 1, 290 vtx_es_8in32 = 2 291 }; 292 293 enum EVFetchFlagShift { 294 vtx_fetch_whole_quad, 295 vtx_use_const_field, 296 vtx_format_comp_signed, 297 vtx_srf_mode, 298 vtx_buf_no_stride, 299 vtx_alt_const, 300 vtx_use_tc, 301 vtx_vpm, 302 vtx_is_mega_fetch, 303 vtx_uncached, 304 vtx_indexed, 305 vtx_unknown 306 }; 307 308 enum EBufferIndexMode { 309 bim_none, 310 bim_zero, 311 bim_one, 312 bim_invalid 313 }; 314 315 } // namespace r600 316 317 #endif // DEFINES_H 318