1 /* -*- mesa-c++ -*-
2 *
3 * Copyright (c) 2022 Collabora LTD
4 *
5 * Author: Gert Wollny <gert.wollny@collabora.com>
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include "sfn_shader_cs.h"
28
29 #include "sfn_instr_fetch.h"
30
31 namespace r600 {
32
ComputeShader(UNUSED const r600_shader_key & key,int num_samplers)33 ComputeShader::ComputeShader(UNUSED const r600_shader_key& key, int num_samplers):
34 Shader("CS", 0),
35 m_image_size_const_offset(num_samplers)
36 {
37 }
38
39 bool
do_scan_instruction(UNUSED nir_instr * instr)40 ComputeShader::do_scan_instruction(UNUSED nir_instr *instr)
41 {
42 return false;
43 }
44
45 int
do_allocate_reserved_registers()46 ComputeShader::do_allocate_reserved_registers()
47 {
48 auto& vf = value_factory();
49
50 const int thread_id_sel = 0;
51 const int wg_id_sel = 1;
52
53 for (int i = 0; i < 3; ++i) {
54 m_local_invocation_id[i] = vf.allocate_pinned_register(thread_id_sel, i);
55 m_local_invocation_id[i]->set_flag(Register::pin_end);
56 m_workgroup_id[i] = vf.allocate_pinned_register(wg_id_sel, i);
57 m_workgroup_id[i]->set_flag(Register::pin_end);
58 }
59 return 2;
60 }
61
62 bool
process_stage_intrinsic(nir_intrinsic_instr * instr)63 ComputeShader::process_stage_intrinsic(nir_intrinsic_instr *instr)
64 {
65 switch (instr->intrinsic) {
66 case nir_intrinsic_load_local_invocation_id:
67 return emit_load_3vec(instr, m_local_invocation_id);
68 case nir_intrinsic_load_workgroup_id:
69 return emit_load_3vec(instr, m_workgroup_id);
70 case nir_intrinsic_load_workgroup_size:
71 return emit_load_from_info_buffer(instr, 0);
72 case nir_intrinsic_load_num_workgroups:
73 return emit_load_from_info_buffer(instr, 16);
74 default:
75 return false;
76 }
77 }
78
79 void
do_get_shader_info(r600_shader * sh_info)80 ComputeShader::do_get_shader_info(r600_shader *sh_info)
81 {
82 sh_info->processor_type = PIPE_SHADER_COMPUTE;
83 }
84
85 bool
read_prop(UNUSED std::istream & is)86 ComputeShader::read_prop(UNUSED std::istream& is)
87 {
88 return true;
89 }
90
91 void
do_print_properties(UNUSED std::ostream & os) const92 ComputeShader::do_print_properties(UNUSED std::ostream& os) const
93 {
94 }
95
96 bool
emit_load_from_info_buffer(nir_intrinsic_instr * instr,int offset)97 ComputeShader::emit_load_from_info_buffer(nir_intrinsic_instr *instr, int offset)
98 {
99 if (!m_zero_register) {
100 m_zero_register = value_factory().temp_register();
101 emit_instruction(new AluInstr(op1_mov,
102 m_zero_register,
103 value_factory().inline_const(ALU_SRC_0, 0),
104 AluInstr::last_write));
105 }
106
107 auto dest = value_factory().dest_vec4(instr->def, pin_group);
108
109 auto ir = new LoadFromBuffer(dest,
110 {0, 1, 2, 7},
111 m_zero_register,
112 offset,
113 R600_BUFFER_INFO_CONST_BUFFER,
114 nullptr,
115 fmt_32_32_32_32);
116
117 ir->set_fetch_flag(LoadFromBuffer::srf_mode);
118 ir->reset_fetch_flag(LoadFromBuffer::format_comp_signed);
119 ir->set_num_format(vtx_nf_int);
120 emit_instruction(ir);
121 return true;
122 }
123
124 bool
emit_load_3vec(nir_intrinsic_instr * instr,const std::array<PRegister,3> & src)125 ComputeShader::emit_load_3vec(nir_intrinsic_instr *instr,
126 const std::array<PRegister, 3>& src)
127 {
128 auto& vf = value_factory();
129
130 for (int i = 0; i < 3; ++i) {
131 auto dest = vf.dest(instr->def, i, pin_none);
132 emit_instruction(new AluInstr(
133 op1_mov, dest, src[i], i == 2 ? AluInstr::last_write : AluInstr::write));
134 }
135 return true;
136 }
137
138 } // namespace r600
139