1 /**************************************************************************
2 *
3 * Copyright 2011 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "radeon_uvd.h"
10
11 #include "pipe/p_video_codec.h"
12 #include "radeon_video.h"
13 #include "radeonsi/si_pipe.h"
14 #include "util/u_memory.h"
15 #include "util/u_video.h"
16 #include "vl/vl_defines.h"
17 #include "vl/vl_mpeg12_decoder.h"
18 #include <sys/types.h>
19
20 #include <assert.h>
21 #include <errno.h>
22 #include <stdio.h>
23 #include <unistd.h>
24
25 #define NUM_BUFFERS 4
26
27 #define NUM_MPEG2_REFS 6
28 #define NUM_H264_REFS 17
29 #define NUM_VC1_REFS 5
30
31 #define FB_BUFFER_OFFSET 0x1000
32 #define FB_BUFFER_SIZE 2048
33 #define FB_BUFFER_SIZE_TONGA (2048 * 64)
34 #define IT_SCALING_TABLE_SIZE 992
35 #define UVD_SESSION_CONTEXT_SIZE (128 * 1024)
36
37 /* UVD decoder representation */
38 struct ruvd_decoder {
39 struct pipe_video_codec base;
40
41 ruvd_set_dtb set_dtb;
42
43 unsigned stream_handle;
44 unsigned stream_type;
45 unsigned frame_number;
46
47 struct pipe_screen *screen;
48 struct radeon_winsys *ws;
49 struct radeon_cmdbuf cs;
50
51 unsigned cur_buffer;
52
53 struct rvid_buffer msg_fb_it_buffers[NUM_BUFFERS];
54 struct ruvd_msg *msg;
55 uint32_t *fb;
56 unsigned fb_size;
57 uint8_t *it;
58
59 struct rvid_buffer bs_buffers[NUM_BUFFERS];
60 void *bs_ptr;
61 unsigned bs_size;
62
63 struct rvid_buffer dpb;
64 bool use_legacy;
65 struct rvid_buffer ctx;
66 struct rvid_buffer sessionctx;
67 struct {
68 unsigned data0;
69 unsigned data1;
70 unsigned cmd;
71 unsigned cntl;
72 } reg;
73
74 void *render_pic_list[16];
75 };
76
77 /* flush IB to the hardware */
flush(struct ruvd_decoder * dec,unsigned flags,struct pipe_fence_handle ** fence)78 static int flush(struct ruvd_decoder *dec, unsigned flags, struct pipe_fence_handle **fence)
79 {
80 return dec->ws->cs_flush(&dec->cs, flags, fence);
81 }
82
ruvd_dec_get_decoder_fence(struct pipe_video_codec * decoder,struct pipe_fence_handle * fence,uint64_t timeout)83 static int ruvd_dec_get_decoder_fence(struct pipe_video_codec *decoder,
84 struct pipe_fence_handle *fence,
85 uint64_t timeout) {
86 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
87 return dec->ws->fence_wait(dec->ws, fence, timeout);
88 }
89
ruvd_dec_destroy_fence(struct pipe_video_codec * decoder,struct pipe_fence_handle * fence)90 static void ruvd_dec_destroy_fence(struct pipe_video_codec *decoder,
91 struct pipe_fence_handle *fence)
92 {
93 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
94
95 dec->ws->fence_reference(dec->ws, &fence, NULL);
96 }
97
98 /* add a new set register command to the IB */
set_reg(struct ruvd_decoder * dec,unsigned reg,uint32_t val)99 static void set_reg(struct ruvd_decoder *dec, unsigned reg, uint32_t val)
100 {
101 radeon_emit(&dec->cs, RUVD_PKT0(reg >> 2, 0));
102 radeon_emit(&dec->cs, val);
103 }
104
105 /* send a command to the VCPU through the GPCOM registers */
send_cmd(struct ruvd_decoder * dec,unsigned cmd,struct pb_buffer_lean * buf,uint32_t off,unsigned usage,enum radeon_bo_domain domain)106 static void send_cmd(struct ruvd_decoder *dec, unsigned cmd, struct pb_buffer_lean *buf, uint32_t off,
107 unsigned usage, enum radeon_bo_domain domain)
108 {
109 int reloc_idx;
110
111 reloc_idx = dec->ws->cs_add_buffer(&dec->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
112 if (!dec->use_legacy) {
113 uint64_t addr;
114 addr = dec->ws->buffer_get_virtual_address(buf);
115 addr = addr + off;
116 set_reg(dec, dec->reg.data0, addr);
117 set_reg(dec, dec->reg.data1, addr >> 32);
118 } else {
119 off += dec->ws->buffer_get_reloc_offset(buf);
120 set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
121 set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
122 }
123 set_reg(dec, dec->reg.cmd, cmd << 1);
124 }
125
126 /* do the codec needs an IT buffer ?*/
have_it(struct ruvd_decoder * dec)127 static bool have_it(struct ruvd_decoder *dec)
128 {
129 return dec->stream_type == RUVD_CODEC_H264_PERF || dec->stream_type == RUVD_CODEC_H265;
130 }
131
132 /* map the next available message/feedback/itscaling buffer */
map_msg_fb_it_buf(struct ruvd_decoder * dec)133 static void map_msg_fb_it_buf(struct ruvd_decoder *dec)
134 {
135 struct rvid_buffer *buf;
136 uint8_t *ptr;
137
138 /* grab the current message/feedback buffer */
139 buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
140
141 /* and map it for CPU access */
142 ptr =
143 dec->ws->buffer_map(dec->ws, buf->res->buf, &dec->cs, PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
144
145 /* calc buffer offsets */
146 dec->msg = (struct ruvd_msg *)ptr;
147 memset(dec->msg, 0, sizeof(*dec->msg));
148
149 dec->fb = (uint32_t *)(ptr + FB_BUFFER_OFFSET);
150 if (have_it(dec))
151 dec->it = (uint8_t *)(ptr + FB_BUFFER_OFFSET + dec->fb_size);
152 }
153
154 /* unmap and send a message command to the VCPU */
send_msg_buf(struct ruvd_decoder * dec)155 static void send_msg_buf(struct ruvd_decoder *dec)
156 {
157 struct rvid_buffer *buf;
158
159 /* ignore the request if message/feedback buffer isn't mapped */
160 if (!dec->msg || !dec->fb)
161 return;
162
163 /* grab the current message buffer */
164 buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
165
166 /* unmap the buffer */
167 dec->ws->buffer_unmap(dec->ws, buf->res->buf);
168 dec->msg = NULL;
169 dec->fb = NULL;
170 dec->it = NULL;
171
172 if (dec->sessionctx.res)
173 send_cmd(dec, RUVD_CMD_SESSION_CONTEXT_BUFFER, dec->sessionctx.res->buf, 0,
174 RADEON_USAGE_READWRITE, RADEON_DOMAIN_VRAM);
175
176 /* and send it to the hardware */
177 send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
178 }
179
180 /* cycle to the next set of buffers */
next_buffer(struct ruvd_decoder * dec)181 static void next_buffer(struct ruvd_decoder *dec)
182 {
183 ++dec->cur_buffer;
184 dec->cur_buffer %= NUM_BUFFERS;
185 }
186
187 /* convert the profile into something UVD understands */
profile2stream_type(struct ruvd_decoder * dec,unsigned family)188 static uint32_t profile2stream_type(struct ruvd_decoder *dec, unsigned family)
189 {
190 switch (u_reduce_video_profile(dec->base.profile)) {
191 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
192 return (family >= CHIP_TONGA) ? RUVD_CODEC_H264_PERF : RUVD_CODEC_H264;
193
194 case PIPE_VIDEO_FORMAT_VC1:
195 return RUVD_CODEC_VC1;
196
197 case PIPE_VIDEO_FORMAT_MPEG12:
198 return RUVD_CODEC_MPEG2;
199
200 case PIPE_VIDEO_FORMAT_MPEG4:
201 return RUVD_CODEC_MPEG4;
202
203 case PIPE_VIDEO_FORMAT_HEVC:
204 return RUVD_CODEC_H265;
205
206 case PIPE_VIDEO_FORMAT_JPEG:
207 return RUVD_CODEC_MJPEG;
208
209 default:
210 assert(0);
211 return 0;
212 }
213 }
214
calc_ctx_size_h264_perf(struct ruvd_decoder * dec)215 static unsigned calc_ctx_size_h264_perf(struct ruvd_decoder *dec)
216 {
217 unsigned width_in_mb, height_in_mb, ctx_size;
218 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
219 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
220
221 unsigned max_references = dec->base.max_references + 1;
222
223 // picture width & height in 16 pixel units
224 width_in_mb = width / VL_MACROBLOCK_WIDTH;
225 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
226
227 if (!dec->use_legacy) {
228 unsigned fs_in_mb = width_in_mb * height_in_mb;
229 unsigned num_dpb_buffer_lean;
230 switch (dec->base.level) {
231 case 30:
232 num_dpb_buffer_lean = 8100 / fs_in_mb;
233 break;
234 case 31:
235 num_dpb_buffer_lean = 18000 / fs_in_mb;
236 break;
237 case 32:
238 num_dpb_buffer_lean = 20480 / fs_in_mb;
239 break;
240 case 41:
241 num_dpb_buffer_lean = 32768 / fs_in_mb;
242 break;
243 case 42:
244 num_dpb_buffer_lean = 34816 / fs_in_mb;
245 break;
246 case 50:
247 num_dpb_buffer_lean = 110400 / fs_in_mb;
248 break;
249 case 51:
250 num_dpb_buffer_lean = 184320 / fs_in_mb;
251 break;
252 default:
253 num_dpb_buffer_lean = 184320 / fs_in_mb;
254 break;
255 }
256 num_dpb_buffer_lean++;
257 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer_lean), max_references);
258 ctx_size = max_references * align(width_in_mb * height_in_mb * 192, 256);
259 } else {
260 // the firmware seems to always assume a minimum of ref frames
261 max_references = MAX2(NUM_H264_REFS, max_references);
262 // macroblock context buffer
263 ctx_size = align(width_in_mb * height_in_mb * max_references * 192, 256);
264 }
265
266 return ctx_size;
267 }
268
calc_ctx_size_h265_main(struct ruvd_decoder * dec)269 static unsigned calc_ctx_size_h265_main(struct ruvd_decoder *dec)
270 {
271 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
272 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
273
274 unsigned max_references = dec->base.max_references + 1;
275
276 if (dec->base.width * dec->base.height >= 4096 * 2000)
277 max_references = MAX2(max_references, 8);
278 else
279 max_references = MAX2(max_references, 17);
280
281 width = align(width, 16);
282 height = align(height, 16);
283 return ((width + 255) / 16) * ((height + 255) / 16) * 16 * max_references + 52 * 1024;
284 }
285
calc_ctx_size_h265_main10(struct ruvd_decoder * dec,struct pipe_h265_picture_desc * pic)286 static unsigned calc_ctx_size_h265_main10(struct ruvd_decoder *dec,
287 struct pipe_h265_picture_desc *pic)
288 {
289 unsigned log2_ctb_size, width_in_ctb, height_in_ctb, num_16x16_block_per_ctb;
290 unsigned context_buffer_size_per_ctb_row, cm_buffer_size, max_mb_address, db_left_tile_pxl_size;
291 unsigned db_left_tile_ctx_size = 4096 / 16 * (32 + 16 * 4);
292
293 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
294 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
295 unsigned coeff_10bit =
296 (pic->pps->sps->bit_depth_luma_minus8 || pic->pps->sps->bit_depth_chroma_minus8) ? 2 : 1;
297
298 unsigned max_references = dec->base.max_references + 1;
299
300 if (dec->base.width * dec->base.height >= 4096 * 2000)
301 max_references = MAX2(max_references, 8);
302 else
303 max_references = MAX2(max_references, 17);
304
305 log2_ctb_size = pic->pps->sps->log2_min_luma_coding_block_size_minus3 + 3 +
306 pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
307
308 width_in_ctb = (width + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
309 height_in_ctb = (height + ((1 << log2_ctb_size) - 1)) >> log2_ctb_size;
310
311 num_16x16_block_per_ctb = ((1 << log2_ctb_size) >> 4) * ((1 << log2_ctb_size) >> 4);
312 context_buffer_size_per_ctb_row = align(width_in_ctb * num_16x16_block_per_ctb * 16, 256);
313 max_mb_address = (unsigned)ceil(height * 8 / 2048.0);
314
315 cm_buffer_size = max_references * context_buffer_size_per_ctb_row * height_in_ctb;
316 db_left_tile_pxl_size = coeff_10bit * (max_mb_address * 2 * 2048 + 1024);
317
318 return cm_buffer_size + db_left_tile_ctx_size + db_left_tile_pxl_size;
319 }
320
get_db_pitch_alignment(struct ruvd_decoder * dec)321 static unsigned get_db_pitch_alignment(struct ruvd_decoder *dec)
322 {
323 if (((struct si_screen *)dec->screen)->info.family < CHIP_VEGA10)
324 return 16;
325 else
326 return 32;
327 }
328
329 /* calculate size of reference picture buffer */
calc_dpb_size(struct ruvd_decoder * dec)330 static unsigned calc_dpb_size(struct ruvd_decoder *dec)
331 {
332 unsigned width_in_mb, height_in_mb, image_size, dpb_size;
333
334 // always align them to MB size for dpb calculation
335 unsigned width = align(dec->base.width, VL_MACROBLOCK_WIDTH);
336 unsigned height = align(dec->base.height, VL_MACROBLOCK_HEIGHT);
337
338 // always one more for currently decoded picture
339 unsigned max_references = dec->base.max_references + 1;
340
341 // aligned size of a single frame
342 image_size = align(width, get_db_pitch_alignment(dec)) * height;
343 image_size += image_size / 2;
344 image_size = align(image_size, 1024);
345
346 // picture width & height in 16 pixel units
347 width_in_mb = width / VL_MACROBLOCK_WIDTH;
348 height_in_mb = align(height / VL_MACROBLOCK_HEIGHT, 2);
349
350 switch (u_reduce_video_profile(dec->base.profile)) {
351 case PIPE_VIDEO_FORMAT_MPEG4_AVC: {
352 if (!dec->use_legacy) {
353 unsigned fs_in_mb = width_in_mb * height_in_mb;
354 unsigned alignment = 64, num_dpb_buffer_lean;
355
356 if (dec->stream_type == RUVD_CODEC_H264_PERF)
357 alignment = 256;
358 switch (dec->base.level) {
359 case 30:
360 num_dpb_buffer_lean = 8100 / fs_in_mb;
361 break;
362 case 31:
363 num_dpb_buffer_lean = 18000 / fs_in_mb;
364 break;
365 case 32:
366 num_dpb_buffer_lean = 20480 / fs_in_mb;
367 break;
368 case 41:
369 num_dpb_buffer_lean = 32768 / fs_in_mb;
370 break;
371 case 42:
372 num_dpb_buffer_lean = 34816 / fs_in_mb;
373 break;
374 case 50:
375 num_dpb_buffer_lean = 110400 / fs_in_mb;
376 break;
377 case 51:
378 num_dpb_buffer_lean = 184320 / fs_in_mb;
379 break;
380 default:
381 num_dpb_buffer_lean = 184320 / fs_in_mb;
382 break;
383 }
384 num_dpb_buffer_lean++;
385 max_references = MAX2(MIN2(NUM_H264_REFS, num_dpb_buffer_lean), max_references);
386 dpb_size = image_size * max_references;
387 if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
388 (((struct si_screen *)dec->screen)->info.family < CHIP_POLARIS10)) {
389 dpb_size += max_references * align(width_in_mb * height_in_mb * 192, alignment);
390 dpb_size += align(width_in_mb * height_in_mb * 32, alignment);
391 }
392 } else {
393 // the firmware seems to always assume a minimum of ref frames
394 max_references = MAX2(NUM_H264_REFS, max_references);
395 // reference picture buffer
396 dpb_size = image_size * max_references;
397 if ((dec->stream_type != RUVD_CODEC_H264_PERF) ||
398 (((struct si_screen *)dec->screen)->info.family < CHIP_POLARIS10)) {
399 // macroblock context buffer
400 dpb_size += width_in_mb * height_in_mb * max_references * 192;
401 // IT surface buffer
402 dpb_size += width_in_mb * height_in_mb * 32;
403 }
404 }
405 break;
406 }
407
408 case PIPE_VIDEO_FORMAT_HEVC:
409 if (dec->base.width * dec->base.height >= 4096 * 2000)
410 max_references = MAX2(max_references, 8);
411 else
412 max_references = MAX2(max_references, 17);
413
414 width = align(width, 16);
415 height = align(height, 16);
416 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
417 dpb_size = align((align(width, get_db_pitch_alignment(dec)) * height * 9) / 4, 256) *
418 max_references;
419 else
420 dpb_size = align((align(width, get_db_pitch_alignment(dec)) * height * 3) / 2, 256) *
421 max_references;
422 break;
423
424 case PIPE_VIDEO_FORMAT_VC1:
425 // the firmware seems to always assume a minimum of ref frames
426 max_references = MAX2(NUM_VC1_REFS, max_references);
427
428 // reference picture buffer
429 dpb_size = image_size * max_references;
430
431 // CONTEXT_BUFFER
432 dpb_size += width_in_mb * height_in_mb * 128;
433
434 // IT surface buffer
435 dpb_size += width_in_mb * 64;
436
437 // DB surface buffer
438 dpb_size += width_in_mb * 128;
439
440 // BP
441 dpb_size += align(MAX2(width_in_mb, height_in_mb) * 7 * 16, 64);
442 break;
443
444 case PIPE_VIDEO_FORMAT_MPEG12:
445 // reference picture buffer, must be big enough for all frames
446 dpb_size = image_size * NUM_MPEG2_REFS;
447 break;
448
449 case PIPE_VIDEO_FORMAT_MPEG4:
450 // reference picture buffer
451 dpb_size = image_size * max_references;
452
453 // CM
454 dpb_size += width_in_mb * height_in_mb * 64;
455
456 // IT surface buffer
457 dpb_size += align(width_in_mb * height_in_mb * 32, 64);
458
459 dpb_size = MAX2(dpb_size, 30 * 1024 * 1024);
460 break;
461
462 case PIPE_VIDEO_FORMAT_JPEG:
463 dpb_size = 0;
464 break;
465
466 default:
467 // something is missing here
468 assert(0);
469
470 // at least use a sane default value
471 dpb_size = 32 * 1024 * 1024;
472 break;
473 }
474 return dpb_size;
475 }
476
477 /* free associated data in the video buffer callback */
ruvd_destroy_associated_data(void * data)478 static void ruvd_destroy_associated_data(void *data)
479 {
480 /* NOOP, since we only use an intptr */
481 }
482
483 /* get h264 specific message bits */
get_h264_msg(struct ruvd_decoder * dec,struct pipe_h264_picture_desc * pic)484 static struct ruvd_h264 get_h264_msg(struct ruvd_decoder *dec, struct pipe_h264_picture_desc *pic)
485 {
486 struct ruvd_h264 result;
487
488 memset(&result, 0, sizeof(result));
489 switch (pic->base.profile) {
490 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
491 case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
492 result.profile = RUVD_H264_PROFILE_BASELINE;
493 break;
494
495 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
496 result.profile = RUVD_H264_PROFILE_MAIN;
497 break;
498
499 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
500 result.profile = RUVD_H264_PROFILE_HIGH;
501 break;
502
503 default:
504 assert(0);
505 break;
506 }
507
508 result.level = dec->base.level;
509
510 result.sps_info_flags = 0;
511 result.sps_info_flags |= pic->pps->sps->direct_8x8_inference_flag << 0;
512 result.sps_info_flags |= pic->pps->sps->mb_adaptive_frame_field_flag << 1;
513 result.sps_info_flags |= pic->pps->sps->frame_mbs_only_flag << 2;
514 result.sps_info_flags |= pic->pps->sps->delta_pic_order_always_zero_flag << 3;
515
516 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
517 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
518 result.log2_max_frame_num_minus4 = pic->pps->sps->log2_max_frame_num_minus4;
519 result.pic_order_cnt_type = pic->pps->sps->pic_order_cnt_type;
520 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
521
522 switch (dec->base.chroma_format) {
523 case PIPE_VIDEO_CHROMA_FORMAT_NONE:
524 /* TODO: assert? */
525 break;
526 case PIPE_VIDEO_CHROMA_FORMAT_400:
527 result.chroma_format = 0;
528 break;
529 case PIPE_VIDEO_CHROMA_FORMAT_420:
530 result.chroma_format = 1;
531 break;
532 case PIPE_VIDEO_CHROMA_FORMAT_422:
533 result.chroma_format = 2;
534 break;
535 case PIPE_VIDEO_CHROMA_FORMAT_444:
536 result.chroma_format = 3;
537 break;
538 }
539
540 result.pps_info_flags = 0;
541 result.pps_info_flags |= pic->pps->transform_8x8_mode_flag << 0;
542 result.pps_info_flags |= pic->pps->redundant_pic_cnt_present_flag << 1;
543 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 2;
544 result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag << 3;
545 result.pps_info_flags |= pic->pps->weighted_bipred_idc << 4;
546 result.pps_info_flags |= pic->pps->weighted_pred_flag << 6;
547 result.pps_info_flags |= pic->pps->bottom_field_pic_order_in_frame_present_flag << 7;
548 result.pps_info_flags |= pic->pps->entropy_coding_mode_flag << 8;
549
550 result.num_slice_groups_minus1 = pic->pps->num_slice_groups_minus1;
551 result.slice_group_map_type = pic->pps->slice_group_map_type;
552 result.slice_group_change_rate_minus1 = pic->pps->slice_group_change_rate_minus1;
553 result.pic_init_qp_minus26 = pic->pps->pic_init_qp_minus26;
554 result.chroma_qp_index_offset = pic->pps->chroma_qp_index_offset;
555 result.second_chroma_qp_index_offset = pic->pps->second_chroma_qp_index_offset;
556
557 memcpy(result.scaling_list_4x4, pic->pps->ScalingList4x4, 6 * 16);
558 memcpy(result.scaling_list_8x8, pic->pps->ScalingList8x8, 2 * 64);
559
560 if (dec->stream_type == RUVD_CODEC_H264_PERF) {
561 memcpy(dec->it, result.scaling_list_4x4, 6 * 16);
562 memcpy((dec->it + 96), result.scaling_list_8x8, 2 * 64);
563 }
564
565 result.num_ref_frames = pic->num_ref_frames;
566
567 result.num_ref_idx_l0_active_minus1 = pic->num_ref_idx_l0_active_minus1;
568 result.num_ref_idx_l1_active_minus1 = pic->num_ref_idx_l1_active_minus1;
569
570 result.frame_num = pic->frame_num;
571 memcpy(result.frame_num_list, pic->frame_num_list, 4 * 16);
572 result.curr_field_order_cnt_list[0] = pic->field_order_cnt[0];
573 result.curr_field_order_cnt_list[1] = pic->field_order_cnt[1];
574 memcpy(result.field_order_cnt_list, pic->field_order_cnt_list, 4 * 16 * 2);
575
576 result.decoded_pic_idx = pic->frame_num;
577
578 return result;
579 }
580
581 /* get h265 specific message bits */
get_h265_msg(struct ruvd_decoder * dec,struct pipe_video_buffer * target,struct pipe_h265_picture_desc * pic)582 static struct ruvd_h265 get_h265_msg(struct ruvd_decoder *dec, struct pipe_video_buffer *target,
583 struct pipe_h265_picture_desc *pic)
584 {
585 struct ruvd_h265 result;
586 unsigned i, j;
587
588 memset(&result, 0, sizeof(result));
589
590 result.sps_info_flags = 0;
591 result.sps_info_flags |= pic->pps->sps->scaling_list_enabled_flag << 0;
592 result.sps_info_flags |= pic->pps->sps->amp_enabled_flag << 1;
593 result.sps_info_flags |= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2;
594 result.sps_info_flags |= pic->pps->sps->pcm_enabled_flag << 3;
595 result.sps_info_flags |= pic->pps->sps->pcm_loop_filter_disabled_flag << 4;
596 result.sps_info_flags |= pic->pps->sps->long_term_ref_pics_present_flag << 5;
597 result.sps_info_flags |= pic->pps->sps->sps_temporal_mvp_enabled_flag << 6;
598 result.sps_info_flags |= pic->pps->sps->strong_intra_smoothing_enabled_flag << 7;
599 result.sps_info_flags |= pic->pps->sps->separate_colour_plane_flag << 8;
600 if (((struct si_screen *)dec->screen)->info.family == CHIP_CARRIZO)
601 result.sps_info_flags |= 1 << 9;
602 if (pic->UseRefPicList == true)
603 result.sps_info_flags |= 1 << 10;
604
605 result.chroma_format = pic->pps->sps->chroma_format_idc;
606 result.bit_depth_luma_minus8 = pic->pps->sps->bit_depth_luma_minus8;
607 result.bit_depth_chroma_minus8 = pic->pps->sps->bit_depth_chroma_minus8;
608 result.log2_max_pic_order_cnt_lsb_minus4 = pic->pps->sps->log2_max_pic_order_cnt_lsb_minus4;
609 result.sps_max_dec_pic_buffering_minus1 = pic->pps->sps->sps_max_dec_pic_buffering_minus1;
610 result.log2_min_luma_coding_block_size_minus3 =
611 pic->pps->sps->log2_min_luma_coding_block_size_minus3;
612 result.log2_diff_max_min_luma_coding_block_size =
613 pic->pps->sps->log2_diff_max_min_luma_coding_block_size;
614 result.log2_min_transform_block_size_minus2 =
615 pic->pps->sps->log2_min_transform_block_size_minus2;
616 result.log2_diff_max_min_transform_block_size =
617 pic->pps->sps->log2_diff_max_min_transform_block_size;
618 result.max_transform_hierarchy_depth_inter = pic->pps->sps->max_transform_hierarchy_depth_inter;
619 result.max_transform_hierarchy_depth_intra = pic->pps->sps->max_transform_hierarchy_depth_intra;
620 result.pcm_sample_bit_depth_luma_minus1 = pic->pps->sps->pcm_sample_bit_depth_luma_minus1;
621 result.pcm_sample_bit_depth_chroma_minus1 = pic->pps->sps->pcm_sample_bit_depth_chroma_minus1;
622 result.log2_min_pcm_luma_coding_block_size_minus3 =
623 pic->pps->sps->log2_min_pcm_luma_coding_block_size_minus3;
624 result.log2_diff_max_min_pcm_luma_coding_block_size =
625 pic->pps->sps->log2_diff_max_min_pcm_luma_coding_block_size;
626 result.num_short_term_ref_pic_sets = pic->pps->sps->num_short_term_ref_pic_sets;
627
628 result.pps_info_flags = 0;
629 result.pps_info_flags |= pic->pps->dependent_slice_segments_enabled_flag << 0;
630 result.pps_info_flags |= pic->pps->output_flag_present_flag << 1;
631 result.pps_info_flags |= pic->pps->sign_data_hiding_enabled_flag << 2;
632 result.pps_info_flags |= pic->pps->cabac_init_present_flag << 3;
633 result.pps_info_flags |= pic->pps->constrained_intra_pred_flag << 4;
634 result.pps_info_flags |= pic->pps->transform_skip_enabled_flag << 5;
635 result.pps_info_flags |= pic->pps->cu_qp_delta_enabled_flag << 6;
636 result.pps_info_flags |= pic->pps->pps_slice_chroma_qp_offsets_present_flag << 7;
637 result.pps_info_flags |= pic->pps->weighted_pred_flag << 8;
638 result.pps_info_flags |= pic->pps->weighted_bipred_flag << 9;
639 result.pps_info_flags |= pic->pps->transquant_bypass_enabled_flag << 10;
640 result.pps_info_flags |= pic->pps->tiles_enabled_flag << 11;
641 result.pps_info_flags |= pic->pps->entropy_coding_sync_enabled_flag << 12;
642 result.pps_info_flags |= pic->pps->uniform_spacing_flag << 13;
643 result.pps_info_flags |= pic->pps->loop_filter_across_tiles_enabled_flag << 14;
644 result.pps_info_flags |= pic->pps->pps_loop_filter_across_slices_enabled_flag << 15;
645 result.pps_info_flags |= pic->pps->deblocking_filter_override_enabled_flag << 16;
646 result.pps_info_flags |= pic->pps->pps_deblocking_filter_disabled_flag << 17;
647 result.pps_info_flags |= pic->pps->lists_modification_present_flag << 18;
648 result.pps_info_flags |= pic->pps->slice_segment_header_extension_present_flag << 19;
649 // result.pps_info_flags |= pic->pps->deblocking_filter_control_present_flag; ???
650
651 result.num_extra_slice_header_bits = pic->pps->num_extra_slice_header_bits;
652 result.num_long_term_ref_pic_sps = pic->pps->sps->num_long_term_ref_pics_sps;
653 result.num_ref_idx_l0_default_active_minus1 = pic->pps->num_ref_idx_l0_default_active_minus1;
654 result.num_ref_idx_l1_default_active_minus1 = pic->pps->num_ref_idx_l1_default_active_minus1;
655 result.pps_cb_qp_offset = pic->pps->pps_cb_qp_offset;
656 result.pps_cr_qp_offset = pic->pps->pps_cr_qp_offset;
657 result.pps_beta_offset_div2 = pic->pps->pps_beta_offset_div2;
658 result.pps_tc_offset_div2 = pic->pps->pps_tc_offset_div2;
659 result.diff_cu_qp_delta_depth = pic->pps->diff_cu_qp_delta_depth;
660 result.num_tile_columns_minus1 = pic->pps->num_tile_columns_minus1;
661 result.num_tile_rows_minus1 = pic->pps->num_tile_rows_minus1;
662 result.log2_parallel_merge_level_minus2 = pic->pps->log2_parallel_merge_level_minus2;
663 result.init_qp_minus26 = pic->pps->init_qp_minus26;
664
665 for (i = 0; i < 19; ++i)
666 result.column_width_minus1[i] = pic->pps->column_width_minus1[i];
667
668 for (i = 0; i < 21; ++i)
669 result.row_height_minus1[i] = pic->pps->row_height_minus1[i];
670
671 result.num_delta_pocs_ref_rps_idx = pic->NumDeltaPocsOfRefRpsIdx;
672 result.curr_poc = pic->CurrPicOrderCntVal;
673
674 for (i = 0; i < 16; i++) {
675 for (j = 0; (pic->ref[j] != NULL) && (j < 16); j++) {
676 if (dec->render_pic_list[i] == pic->ref[j])
677 break;
678 if (j == 15)
679 dec->render_pic_list[i] = NULL;
680 else if (pic->ref[j + 1] == NULL)
681 dec->render_pic_list[i] = NULL;
682 }
683 }
684 for (i = 0; i < 16; i++) {
685 if (dec->render_pic_list[i] == NULL) {
686 dec->render_pic_list[i] = target;
687 result.curr_idx = i;
688 break;
689 }
690 }
691
692 vl_video_buffer_set_associated_data(target, &dec->base, (void *)(uintptr_t)result.curr_idx,
693 &ruvd_destroy_associated_data);
694
695 for (i = 0; i < 16; ++i) {
696 struct pipe_video_buffer *ref = pic->ref[i];
697 uintptr_t ref_pic = 0;
698
699 result.poc_list[i] = pic->PicOrderCntVal[i];
700
701 if (ref)
702 ref_pic = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
703 else
704 ref_pic = 0x7F;
705 result.ref_pic_list[i] = ref_pic;
706 }
707
708 for (i = 0; i < 8; ++i) {
709 result.ref_pic_set_st_curr_before[i] = 0xFF;
710 result.ref_pic_set_st_curr_after[i] = 0xFF;
711 result.ref_pic_set_lt_curr[i] = 0xFF;
712 }
713
714 for (i = 0; i < pic->NumPocStCurrBefore; ++i)
715 result.ref_pic_set_st_curr_before[i] = pic->RefPicSetStCurrBefore[i];
716
717 for (i = 0; i < pic->NumPocStCurrAfter; ++i)
718 result.ref_pic_set_st_curr_after[i] = pic->RefPicSetStCurrAfter[i];
719
720 for (i = 0; i < pic->NumPocLtCurr; ++i)
721 result.ref_pic_set_lt_curr[i] = pic->RefPicSetLtCurr[i];
722
723 for (i = 0; i < 6; ++i)
724 result.ucScalingListDCCoefSizeID2[i] = pic->pps->sps->ScalingListDCCoeff16x16[i];
725
726 for (i = 0; i < 2; ++i)
727 result.ucScalingListDCCoefSizeID3[i] = pic->pps->sps->ScalingListDCCoeff32x32[i];
728
729 memcpy(dec->it, pic->pps->sps->ScalingList4x4, 6 * 16);
730 memcpy(dec->it + 96, pic->pps->sps->ScalingList8x8, 6 * 64);
731 memcpy(dec->it + 480, pic->pps->sps->ScalingList16x16, 6 * 64);
732 memcpy(dec->it + 864, pic->pps->sps->ScalingList32x32, 2 * 64);
733
734 for (i = 0; i < 2; i++) {
735 for (j = 0; j < 15; j++)
736 result.direct_reflist[i][j] = pic->RefPicList[0][i][j];
737 }
738
739 if (pic->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
740 if (target->buffer_format == PIPE_FORMAT_P010 || target->buffer_format == PIPE_FORMAT_P016) {
741 result.p010_mode = 1;
742 result.msb_mode = 1;
743 } else {
744 result.luma_10to8 = 5;
745 result.chroma_10to8 = 5;
746 result.sclr_luma10to8 = 4;
747 result.sclr_chroma10to8 = 4;
748 }
749 }
750
751 /* TODO
752 result.highestTid;
753 result.isNonRef;
754
755 IDRPicFlag;
756 RAPPicFlag;
757 NumPocTotalCurr;
758 NumShortTermPictureSliceHeaderBits;
759 NumLongTermPictureSliceHeaderBits;
760
761 IsLongTerm[16];
762 */
763
764 return result;
765 }
766
767 /* get vc1 specific message bits */
get_vc1_msg(struct pipe_vc1_picture_desc * pic)768 static struct ruvd_vc1 get_vc1_msg(struct pipe_vc1_picture_desc *pic)
769 {
770 struct ruvd_vc1 result;
771
772 memset(&result, 0, sizeof(result));
773
774 switch (pic->base.profile) {
775 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
776 result.profile = RUVD_VC1_PROFILE_SIMPLE;
777 result.level = 1;
778 break;
779
780 case PIPE_VIDEO_PROFILE_VC1_MAIN:
781 result.profile = RUVD_VC1_PROFILE_MAIN;
782 result.level = 2;
783 break;
784
785 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
786 result.profile = RUVD_VC1_PROFILE_ADVANCED;
787 result.level = 4;
788 break;
789
790 default:
791 assert(0);
792 }
793
794 /* fields common for all profiles */
795 result.sps_info_flags |= pic->postprocflag << 7;
796 result.sps_info_flags |= pic->pulldown << 6;
797 result.sps_info_flags |= pic->interlace << 5;
798 result.sps_info_flags |= pic->tfcntrflag << 4;
799 result.sps_info_flags |= pic->finterpflag << 3;
800 result.sps_info_flags |= pic->psf << 1;
801
802 result.pps_info_flags |= pic->range_mapy_flag << 31;
803 result.pps_info_flags |= pic->range_mapy << 28;
804 result.pps_info_flags |= pic->range_mapuv_flag << 27;
805 result.pps_info_flags |= pic->range_mapuv << 24;
806 result.pps_info_flags |= pic->multires << 21;
807 result.pps_info_flags |= pic->maxbframes << 16;
808 result.pps_info_flags |= pic->overlap << 11;
809 result.pps_info_flags |= pic->quantizer << 9;
810 result.pps_info_flags |= pic->panscan_flag << 7;
811 result.pps_info_flags |= pic->refdist_flag << 6;
812 result.pps_info_flags |= pic->vstransform << 0;
813
814 /* some fields only apply to main/advanced profile */
815 if (pic->base.profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE) {
816 result.pps_info_flags |= pic->syncmarker << 20;
817 result.pps_info_flags |= pic->rangered << 19;
818 result.pps_info_flags |= pic->loopfilter << 5;
819 result.pps_info_flags |= pic->fastuvmc << 4;
820 result.pps_info_flags |= pic->extended_mv << 3;
821 result.pps_info_flags |= pic->extended_dmv << 8;
822 result.pps_info_flags |= pic->dquant << 1;
823 }
824
825 result.chroma_format = 1;
826
827 #if 0
828 //(((unsigned int)(pPicParams->advance.reserved1)) << SPS_INFO_VC1_RESERVED_SHIFT)
829 uint32_t slice_count
830 uint8_t picture_type
831 uint8_t frame_coding_mode
832 uint8_t deblockEnable
833 uint8_t pquant
834 #endif
835
836 return result;
837 }
838
839 /* extract the frame number from a referenced video buffer */
get_ref_pic_idx(struct ruvd_decoder * dec,struct pipe_video_buffer * ref)840 static uint32_t get_ref_pic_idx(struct ruvd_decoder *dec, struct pipe_video_buffer *ref)
841 {
842 uint32_t min = MAX2(dec->frame_number, NUM_MPEG2_REFS) - NUM_MPEG2_REFS;
843 uint32_t max = MAX2(dec->frame_number, 1) - 1;
844 uintptr_t frame;
845
846 /* seems to be the most sane fallback */
847 if (!ref)
848 return max;
849
850 /* get the frame number from the associated data */
851 frame = (uintptr_t)vl_video_buffer_get_associated_data(ref, &dec->base);
852
853 /* limit the frame number to a valid range */
854 return MAX2(MIN2(frame, max), min);
855 }
856
857 /* get mpeg2 specific msg bits */
get_mpeg2_msg(struct ruvd_decoder * dec,struct pipe_mpeg12_picture_desc * pic)858 static struct ruvd_mpeg2 get_mpeg2_msg(struct ruvd_decoder *dec,
859 struct pipe_mpeg12_picture_desc *pic)
860 {
861 const int *zscan = pic->alternate_scan ? vl_zscan_alternate : vl_zscan_normal;
862 struct ruvd_mpeg2 result;
863 unsigned i;
864
865 memset(&result, 0, sizeof(result));
866 result.decoded_pic_idx = dec->frame_number;
867 for (i = 0; i < 2; ++i)
868 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
869
870 if (pic->intra_matrix) {
871 result.load_intra_quantiser_matrix = 1;
872 for (i = 0; i < 64; ++i) {
873 result.intra_quantiser_matrix[i] = pic->intra_matrix[zscan[i]];
874 }
875 }
876 if (pic->non_intra_matrix) {
877 result.load_nonintra_quantiser_matrix = 1;
878 for (i = 0; i < 64; ++i) {
879 result.nonintra_quantiser_matrix[i] = pic->non_intra_matrix[zscan[i]];
880 }
881 }
882
883 result.profile_and_level_indication = 0;
884 result.chroma_format = 0x1;
885
886 result.picture_coding_type = pic->picture_coding_type;
887 result.f_code[0][0] = pic->f_code[0][0] + 1;
888 result.f_code[0][1] = pic->f_code[0][1] + 1;
889 result.f_code[1][0] = pic->f_code[1][0] + 1;
890 result.f_code[1][1] = pic->f_code[1][1] + 1;
891 result.intra_dc_precision = pic->intra_dc_precision;
892 result.pic_structure = pic->picture_structure;
893 result.top_field_first = pic->top_field_first;
894 result.frame_pred_frame_dct = pic->frame_pred_frame_dct;
895 result.concealment_motion_vectors = pic->concealment_motion_vectors;
896 result.q_scale_type = pic->q_scale_type;
897 result.intra_vlc_format = pic->intra_vlc_format;
898 result.alternate_scan = pic->alternate_scan;
899
900 return result;
901 }
902
903 /* get mpeg4 specific msg bits */
get_mpeg4_msg(struct ruvd_decoder * dec,struct pipe_mpeg4_picture_desc * pic)904 static struct ruvd_mpeg4 get_mpeg4_msg(struct ruvd_decoder *dec,
905 struct pipe_mpeg4_picture_desc *pic)
906 {
907 struct ruvd_mpeg4 result;
908 unsigned i;
909
910 memset(&result, 0, sizeof(result));
911 result.decoded_pic_idx = dec->frame_number;
912 for (i = 0; i < 2; ++i)
913 result.ref_pic_idx[i] = get_ref_pic_idx(dec, pic->ref[i]);
914
915 result.variant_type = 0;
916 result.profile_and_level_indication = 0xF0; // ASP Level0
917
918 result.video_object_layer_verid = 0x5; // advanced simple
919 result.video_object_layer_shape = 0x0; // rectangular
920
921 result.video_object_layer_width = dec->base.width;
922 result.video_object_layer_height = dec->base.height;
923
924 result.vop_time_increment_resolution = pic->vop_time_increment_resolution;
925
926 result.flags |= pic->short_video_header << 0;
927 // result.flags |= obmc_disable << 1;
928 result.flags |= pic->interlaced << 2;
929 result.flags |= 1 << 3; // load_intra_quant_mat
930 result.flags |= 1 << 4; // load_nonintra_quant_mat
931 result.flags |= pic->quarter_sample << 5;
932 result.flags |= 1 << 6; // complexity_estimation_disable
933 result.flags |= pic->resync_marker_disable << 7;
934 // result.flags |= data_partitioned << 8;
935 // result.flags |= reversible_vlc << 9;
936 result.flags |= 0 << 10; // newpred_enable
937 result.flags |= 0 << 11; // reduced_resolution_vop_enable
938 // result.flags |= scalability << 12;
939 // result.flags |= is_object_layer_identifier << 13;
940 // result.flags |= fixed_vop_rate << 14;
941 // result.flags |= newpred_segment_type << 15;
942
943 result.quant_type = pic->quant_type;
944
945 for (i = 0; i < 64; ++i) {
946 result.intra_quant_mat[i] = pic->intra_matrix[vl_zscan_normal[i]];
947 result.nonintra_quant_mat[i] = pic->non_intra_matrix[vl_zscan_normal[i]];
948 }
949
950 /*
951 int32_t trd [2]
952 int32_t trb [2]
953 uint8_t vop_coding_type
954 uint8_t vop_fcode_forward
955 uint8_t vop_fcode_backward
956 uint8_t rounding_control
957 uint8_t alternate_vertical_scan_flag
958 uint8_t top_field_first
959 */
960
961 return result;
962 }
963
964 /**
965 * destroy this video decoder
966 */
ruvd_destroy(struct pipe_video_codec * decoder)967 static void ruvd_destroy(struct pipe_video_codec *decoder)
968 {
969 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
970 unsigned i;
971
972 assert(decoder);
973
974 map_msg_fb_it_buf(dec);
975 dec->msg->size = sizeof(*dec->msg);
976 dec->msg->msg_type = RUVD_MSG_DESTROY;
977 dec->msg->stream_handle = dec->stream_handle;
978 send_msg_buf(dec);
979
980 flush(dec, 0, NULL);
981
982 dec->ws->cs_destroy(&dec->cs);
983
984 for (i = 0; i < NUM_BUFFERS; ++i) {
985 si_vid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
986 si_vid_destroy_buffer(&dec->bs_buffers[i]);
987 }
988
989 si_vid_destroy_buffer(&dec->dpb);
990 si_vid_destroy_buffer(&dec->ctx);
991 si_vid_destroy_buffer(&dec->sessionctx);
992
993 FREE(dec);
994 }
995
996 /**
997 * start decoding of a new frame
998 */
ruvd_begin_frame(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)999 static void ruvd_begin_frame(struct pipe_video_codec *decoder, struct pipe_video_buffer *target,
1000 struct pipe_picture_desc *picture)
1001 {
1002 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
1003 uintptr_t frame;
1004
1005 assert(decoder);
1006
1007 frame = ++dec->frame_number;
1008 vl_video_buffer_set_associated_data(target, decoder, (void *)frame,
1009 &ruvd_destroy_associated_data);
1010
1011 dec->bs_size = 0;
1012 dec->bs_ptr = dec->ws->buffer_map(dec->ws, dec->bs_buffers[dec->cur_buffer].res->buf, &dec->cs,
1013 PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
1014 }
1015
1016 /**
1017 * decode a macroblock
1018 */
ruvd_decode_macroblock(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture,const struct pipe_macroblock * macroblocks,unsigned num_macroblocks)1019 static void ruvd_decode_macroblock(struct pipe_video_codec *decoder,
1020 struct pipe_video_buffer *target,
1021 struct pipe_picture_desc *picture,
1022 const struct pipe_macroblock *macroblocks,
1023 unsigned num_macroblocks)
1024 {
1025 /* not supported (yet) */
1026 assert(0);
1027 }
1028
1029 /**
1030 * decode a bitstream
1031 */
ruvd_decode_bitstream(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture,unsigned num_buffers,const void * const * buffers,const unsigned * sizes)1032 static void ruvd_decode_bitstream(struct pipe_video_codec *decoder,
1033 struct pipe_video_buffer *target,
1034 struct pipe_picture_desc *picture, unsigned num_buffers,
1035 const void *const *buffers, const unsigned *sizes)
1036 {
1037 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
1038 unsigned i;
1039
1040 assert(decoder);
1041
1042 if (!dec->bs_ptr)
1043 return;
1044
1045 for (i = 0; i < num_buffers; ++i) {
1046 struct rvid_buffer *buf = &dec->bs_buffers[dec->cur_buffer];
1047 unsigned new_size = dec->bs_size + sizes[i];
1048
1049 if (new_size > buf->res->buf->size) {
1050 dec->ws->buffer_unmap(dec->ws, buf->res->buf);
1051 if (!si_vid_resize_buffer(dec->screen, &dec->cs, buf, new_size, NULL)) {
1052 RVID_ERR("Can't resize bitstream buffer!");
1053 return;
1054 }
1055
1056 dec->bs_ptr = dec->ws->buffer_map(dec->ws, buf->res->buf, &dec->cs,
1057 PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
1058 if (!dec->bs_ptr)
1059 return;
1060
1061 dec->bs_ptr += dec->bs_size;
1062 }
1063
1064 memcpy(dec->bs_ptr, buffers[i], sizes[i]);
1065 dec->bs_size += sizes[i];
1066 dec->bs_ptr += sizes[i];
1067 }
1068 }
1069
1070 /**
1071 * end decoding of the current frame
1072 */
ruvd_end_frame(struct pipe_video_codec * decoder,struct pipe_video_buffer * target,struct pipe_picture_desc * picture)1073 static void ruvd_end_frame(struct pipe_video_codec *decoder, struct pipe_video_buffer *target,
1074 struct pipe_picture_desc *picture)
1075 {
1076 struct ruvd_decoder *dec = (struct ruvd_decoder *)decoder;
1077 struct pb_buffer_lean *dt;
1078 struct rvid_buffer *msg_fb_it_buf, *bs_buf;
1079 unsigned bs_size;
1080
1081 assert(decoder);
1082
1083 if (!dec->bs_ptr)
1084 return;
1085
1086 msg_fb_it_buf = &dec->msg_fb_it_buffers[dec->cur_buffer];
1087 bs_buf = &dec->bs_buffers[dec->cur_buffer];
1088
1089 bs_size = align(dec->bs_size, 128);
1090 memset(dec->bs_ptr, 0, bs_size - dec->bs_size);
1091 dec->ws->buffer_unmap(dec->ws, bs_buf->res->buf);
1092
1093 map_msg_fb_it_buf(dec);
1094 dec->msg->size = sizeof(*dec->msg);
1095 dec->msg->msg_type = RUVD_MSG_DECODE;
1096 dec->msg->stream_handle = dec->stream_handle;
1097 dec->msg->status_report_feedback_number = dec->frame_number;
1098
1099 dec->msg->body.decode.stream_type = dec->stream_type;
1100 dec->msg->body.decode.decode_flags = 0x1;
1101 dec->msg->body.decode.width_in_samples = dec->base.width;
1102 dec->msg->body.decode.height_in_samples = dec->base.height;
1103
1104 if ((picture->profile == PIPE_VIDEO_PROFILE_VC1_SIMPLE) ||
1105 (picture->profile == PIPE_VIDEO_PROFILE_VC1_MAIN)) {
1106 dec->msg->body.decode.width_in_samples =
1107 align(dec->msg->body.decode.width_in_samples, 16) / 16;
1108 dec->msg->body.decode.height_in_samples =
1109 align(dec->msg->body.decode.height_in_samples, 16) / 16;
1110 }
1111
1112 if (dec->dpb.res)
1113 dec->msg->body.decode.dpb_size = dec->dpb.res->buf->size;
1114 dec->msg->body.decode.bsd_size = bs_size;
1115 dec->msg->body.decode.db_pitch = align(dec->base.width, get_db_pitch_alignment(dec));
1116
1117 if (dec->stream_type == RUVD_CODEC_H264_PERF &&
1118 ((struct si_screen *)dec->screen)->info.family >= CHIP_POLARIS10)
1119 dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
1120
1121 dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
1122 if (((struct si_screen *)dec->screen)->info.family >= CHIP_STONEY)
1123 dec->msg->body.decode.dt_wa_chroma_top_offset = dec->msg->body.decode.dt_pitch / 2;
1124
1125 switch (u_reduce_video_profile(picture->profile)) {
1126 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1127 dec->msg->body.decode.codec.h264 =
1128 get_h264_msg(dec, (struct pipe_h264_picture_desc *)picture);
1129 break;
1130
1131 case PIPE_VIDEO_FORMAT_HEVC:
1132 dec->msg->body.decode.codec.h265 =
1133 get_h265_msg(dec, target, (struct pipe_h265_picture_desc *)picture);
1134 if (dec->ctx.res == NULL) {
1135 unsigned ctx_size;
1136 if (dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
1137 ctx_size = calc_ctx_size_h265_main10(dec, (struct pipe_h265_picture_desc *)picture);
1138 else
1139 ctx_size = calc_ctx_size_h265_main(dec);
1140 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1141 RVID_ERR("Can't allocated context buffer.\n");
1142 }
1143 si_vid_clear_buffer(decoder->context, &dec->ctx);
1144 }
1145
1146 if (dec->ctx.res)
1147 dec->msg->body.decode.dpb_reserved = dec->ctx.res->buf->size;
1148 break;
1149
1150 case PIPE_VIDEO_FORMAT_VC1:
1151 dec->msg->body.decode.codec.vc1 = get_vc1_msg((struct pipe_vc1_picture_desc *)picture);
1152 break;
1153
1154 case PIPE_VIDEO_FORMAT_MPEG12:
1155 dec->msg->body.decode.codec.mpeg2 =
1156 get_mpeg2_msg(dec, (struct pipe_mpeg12_picture_desc *)picture);
1157 break;
1158
1159 case PIPE_VIDEO_FORMAT_MPEG4:
1160 dec->msg->body.decode.codec.mpeg4 =
1161 get_mpeg4_msg(dec, (struct pipe_mpeg4_picture_desc *)picture);
1162 break;
1163
1164 case PIPE_VIDEO_FORMAT_JPEG:
1165 break;
1166
1167 default:
1168 assert(0);
1169 return;
1170 }
1171
1172 dec->msg->body.decode.db_surf_tile_config = dec->msg->body.decode.dt_surf_tile_config;
1173 dec->msg->body.decode.extension_support = 0x1;
1174
1175 /* set at least the feedback buffer size */
1176 dec->fb[0] = dec->fb_size;
1177
1178 send_msg_buf(dec);
1179
1180 if (dec->dpb.res)
1181 send_cmd(dec, RUVD_CMD_DPB_BUFFER, dec->dpb.res->buf, 0, RADEON_USAGE_READWRITE,
1182 RADEON_DOMAIN_VRAM);
1183
1184 if (dec->ctx.res)
1185 send_cmd(dec, RUVD_CMD_CONTEXT_BUFFER, dec->ctx.res->buf, 0, RADEON_USAGE_READWRITE,
1186 RADEON_DOMAIN_VRAM);
1187 send_cmd(dec, RUVD_CMD_BITSTREAM_BUFFER, bs_buf->res->buf, 0, RADEON_USAGE_READ,
1188 RADEON_DOMAIN_GTT);
1189 send_cmd(dec, RUVD_CMD_DECODING_TARGET_BUFFER, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
1190 send_cmd(dec, RUVD_CMD_FEEDBACK_BUFFER, msg_fb_it_buf->res->buf, FB_BUFFER_OFFSET,
1191 RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT);
1192 if (have_it(dec))
1193 send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf,
1194 FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
1195 set_reg(dec, dec->reg.cntl, 1);
1196
1197 flush(dec, PIPE_FLUSH_ASYNC, picture->fence);
1198 next_buffer(dec);
1199 }
1200
1201 /**
1202 * flush any outstanding command buffers to the hardware
1203 */
ruvd_flush(struct pipe_video_codec * decoder)1204 static void ruvd_flush(struct pipe_video_codec *decoder)
1205 {
1206 }
1207
1208 /**
1209 * create and UVD decoder
1210 */
si_common_uvd_create_decoder(struct pipe_context * context,const struct pipe_video_codec * templ,ruvd_set_dtb set_dtb)1211 struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *context,
1212 const struct pipe_video_codec *templ,
1213 ruvd_set_dtb set_dtb)
1214 {
1215 struct si_context *sctx = (struct si_context *)context;
1216 struct radeon_winsys *ws = sctx->ws;
1217 unsigned dpb_size;
1218 unsigned width = templ->width, height = templ->height;
1219 unsigned bs_buf_size;
1220 struct ruvd_decoder *dec;
1221 int r, i;
1222
1223 switch (u_reduce_video_profile(templ->profile)) {
1224 case PIPE_VIDEO_FORMAT_MPEG12:
1225 if (templ->entrypoint > PIPE_VIDEO_ENTRYPOINT_BITSTREAM)
1226 return vl_create_mpeg12_decoder(context, templ);
1227
1228 FALLTHROUGH;
1229 case PIPE_VIDEO_FORMAT_MPEG4:
1230 width = align(width, VL_MACROBLOCK_WIDTH);
1231 height = align(height, VL_MACROBLOCK_HEIGHT);
1232 break;
1233 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
1234 width = align(width, VL_MACROBLOCK_WIDTH);
1235 height = align(height, VL_MACROBLOCK_HEIGHT);
1236 break;
1237
1238 default:
1239 break;
1240 }
1241
1242 dec = CALLOC_STRUCT(ruvd_decoder);
1243
1244 if (!dec)
1245 return NULL;
1246
1247 if (!sctx->screen->info.is_amdgpu)
1248 dec->use_legacy = true;
1249
1250 dec->base = *templ;
1251 dec->base.context = context;
1252 dec->base.width = width;
1253 dec->base.height = height;
1254
1255 dec->base.destroy = ruvd_destroy;
1256 dec->base.begin_frame = ruvd_begin_frame;
1257 dec->base.decode_macroblock = ruvd_decode_macroblock;
1258 dec->base.decode_bitstream = ruvd_decode_bitstream;
1259 dec->base.end_frame = ruvd_end_frame;
1260 dec->base.flush = ruvd_flush;
1261 dec->base.get_decoder_fence = ruvd_dec_get_decoder_fence;
1262 dec->base.destroy_fence = ruvd_dec_destroy_fence;
1263
1264 dec->stream_type = profile2stream_type(dec, sctx->family);
1265 dec->set_dtb = set_dtb;
1266 dec->stream_handle = si_vid_alloc_stream_handle();
1267 dec->screen = context->screen;
1268 dec->ws = ws;
1269
1270 if (!ws->cs_create(&dec->cs, sctx->ctx, AMD_IP_UVD, NULL, NULL)) {
1271 RVID_ERR("Can't get command submission context.\n");
1272 goto error;
1273 }
1274
1275 for (i = 0; i < 16; i++)
1276 dec->render_pic_list[i] = NULL;
1277 dec->fb_size = (sctx->family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA : FB_BUFFER_SIZE;
1278 bs_buf_size = width * height * (512 / (16 * 16));
1279 for (i = 0; i < NUM_BUFFERS; ++i) {
1280 unsigned msg_fb_it_size = FB_BUFFER_OFFSET + dec->fb_size;
1281 STATIC_ASSERT(sizeof(struct ruvd_msg) <= FB_BUFFER_OFFSET);
1282 if (have_it(dec))
1283 msg_fb_it_size += IT_SCALING_TABLE_SIZE;
1284 if (!si_vid_create_buffer(dec->screen, &dec->msg_fb_it_buffers[i], msg_fb_it_size,
1285 PIPE_USAGE_STAGING)) {
1286 RVID_ERR("Can't allocated message buffers.\n");
1287 goto error;
1288 }
1289
1290 if (!si_vid_create_buffer(dec->screen, &dec->bs_buffers[i], bs_buf_size,
1291 PIPE_USAGE_STAGING)) {
1292 RVID_ERR("Can't allocated bitstream buffers.\n");
1293 goto error;
1294 }
1295
1296 si_vid_clear_buffer(context, &dec->msg_fb_it_buffers[i]);
1297 si_vid_clear_buffer(context, &dec->bs_buffers[i]);
1298 }
1299
1300 dpb_size = calc_dpb_size(dec);
1301 if (dpb_size) {
1302 if (!si_vid_create_buffer(dec->screen, &dec->dpb, dpb_size, PIPE_USAGE_DEFAULT)) {
1303 RVID_ERR("Can't allocated dpb.\n");
1304 goto error;
1305 }
1306 si_vid_clear_buffer(context, &dec->dpb);
1307 }
1308
1309 if (dec->stream_type == RUVD_CODEC_H264_PERF && sctx->family >= CHIP_POLARIS10) {
1310 unsigned ctx_size = calc_ctx_size_h264_perf(dec);
1311 if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
1312 RVID_ERR("Can't allocated context buffer.\n");
1313 goto error;
1314 }
1315 si_vid_clear_buffer(context, &dec->ctx);
1316 }
1317
1318 if (sctx->family >= CHIP_POLARIS10) {
1319 if (!si_vid_create_buffer(dec->screen, &dec->sessionctx, UVD_SESSION_CONTEXT_SIZE,
1320 PIPE_USAGE_DEFAULT)) {
1321 RVID_ERR("Can't allocated session ctx.\n");
1322 goto error;
1323 }
1324 si_vid_clear_buffer(context, &dec->sessionctx);
1325 }
1326
1327 if (sctx->family >= CHIP_VEGA10) {
1328 dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0_SOC15;
1329 dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1_SOC15;
1330 dec->reg.cmd = RUVD_GPCOM_VCPU_CMD_SOC15;
1331 dec->reg.cntl = RUVD_ENGINE_CNTL_SOC15;
1332 } else {
1333 dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0;
1334 dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1;
1335 dec->reg.cmd = RUVD_GPCOM_VCPU_CMD;
1336 dec->reg.cntl = RUVD_ENGINE_CNTL;
1337 }
1338
1339 map_msg_fb_it_buf(dec);
1340 dec->msg->size = sizeof(*dec->msg);
1341 dec->msg->msg_type = RUVD_MSG_CREATE;
1342 dec->msg->stream_handle = dec->stream_handle;
1343 dec->msg->body.create.stream_type = dec->stream_type;
1344 dec->msg->body.create.width_in_samples = dec->base.width;
1345 dec->msg->body.create.height_in_samples = dec->base.height;
1346 dec->msg->body.create.dpb_size = dpb_size;
1347 send_msg_buf(dec);
1348 r = flush(dec, 0, NULL);
1349 if (r)
1350 goto error;
1351
1352 next_buffer(dec);
1353
1354 return &dec->base;
1355
1356 error:
1357 dec->ws->cs_destroy(&dec->cs);
1358
1359 for (i = 0; i < NUM_BUFFERS; ++i) {
1360 si_vid_destroy_buffer(&dec->msg_fb_it_buffers[i]);
1361 si_vid_destroy_buffer(&dec->bs_buffers[i]);
1362 }
1363
1364 si_vid_destroy_buffer(&dec->dpb);
1365 si_vid_destroy_buffer(&dec->ctx);
1366 si_vid_destroy_buffer(&dec->sessionctx);
1367
1368 FREE(dec);
1369
1370 return NULL;
1371 }
1372
1373 /* calculate top/bottom offset */
texture_offset(struct radeon_surf * surface,unsigned layer,enum ruvd_surface_type type)1374 static unsigned texture_offset(struct radeon_surf *surface, unsigned layer,
1375 enum ruvd_surface_type type)
1376 {
1377 switch (type) {
1378 default:
1379 case RUVD_SURFACE_TYPE_LEGACY:
1380 return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 +
1381 layer * (uint64_t)surface->u.legacy.level[0].slice_size_dw * 4;
1382 break;
1383 case RUVD_SURFACE_TYPE_GFX9:
1384 return surface->u.gfx9.surf_offset + layer * surface->u.gfx9.surf_slice_size;
1385 break;
1386 }
1387 }
1388
1389 /* hw encode the aspect of macro tiles */
macro_tile_aspect(unsigned macro_tile_aspect)1390 static unsigned macro_tile_aspect(unsigned macro_tile_aspect)
1391 {
1392 switch (macro_tile_aspect) {
1393 default:
1394 case 1:
1395 macro_tile_aspect = 0;
1396 break;
1397 case 2:
1398 macro_tile_aspect = 1;
1399 break;
1400 case 4:
1401 macro_tile_aspect = 2;
1402 break;
1403 case 8:
1404 macro_tile_aspect = 3;
1405 break;
1406 }
1407 return macro_tile_aspect;
1408 }
1409
1410 /* hw encode the bank width and height */
bank_wh(unsigned bankwh)1411 static unsigned bank_wh(unsigned bankwh)
1412 {
1413 switch (bankwh) {
1414 default:
1415 case 1:
1416 bankwh = 0;
1417 break;
1418 case 2:
1419 bankwh = 1;
1420 break;
1421 case 4:
1422 bankwh = 2;
1423 break;
1424 case 8:
1425 bankwh = 3;
1426 break;
1427 }
1428 return bankwh;
1429 }
1430
1431 /**
1432 * fill decoding target field from the luma and chroma surfaces
1433 */
si_uvd_set_dt_surfaces(struct ruvd_msg * msg,struct radeon_surf * luma,struct radeon_surf * chroma,enum ruvd_surface_type type)1434 void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
1435 struct radeon_surf *chroma, enum ruvd_surface_type type)
1436 {
1437 switch (type) {
1438 default:
1439 case RUVD_SURFACE_TYPE_LEGACY:
1440 msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x * luma->blk_w;
1441 switch (luma->u.legacy.level[0].mode) {
1442 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1443 msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
1444 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
1445 break;
1446 case RADEON_SURF_MODE_1D:
1447 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1448 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_1D_THIN;
1449 break;
1450 case RADEON_SURF_MODE_2D:
1451 msg->body.decode.dt_tiling_mode = RUVD_TILE_8X8;
1452 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_2D_THIN;
1453 break;
1454 default:
1455 assert(0);
1456 break;
1457 }
1458
1459 msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0, type);
1460 if (chroma)
1461 msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0, type);
1462 if (msg->body.decode.dt_field_mode) {
1463 msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1, type);
1464 if (chroma)
1465 msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1, type);
1466 } else {
1467 msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
1468 msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
1469 }
1470
1471 if (chroma) {
1472 assert(luma->u.legacy.bankw == chroma->u.legacy.bankw);
1473 assert(luma->u.legacy.bankh == chroma->u.legacy.bankh);
1474 assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
1475 }
1476
1477 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw));
1478 msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->u.legacy.bankh));
1479 msg->body.decode.dt_surf_tile_config |=
1480 RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
1481 break;
1482 case RUVD_SURFACE_TYPE_GFX9:
1483 msg->body.decode.dt_pitch = luma->u.gfx9.surf_pitch * luma->blk_w;
1484 /* SWIZZLE LINEAR MODE */
1485 msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
1486 msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
1487 msg->body.decode.dt_luma_top_offset = texture_offset(luma, 0, type);
1488 msg->body.decode.dt_chroma_top_offset = texture_offset(chroma, 0, type);
1489 if (msg->body.decode.dt_field_mode) {
1490 msg->body.decode.dt_luma_bottom_offset = texture_offset(luma, 1, type);
1491 msg->body.decode.dt_chroma_bottom_offset = texture_offset(chroma, 1, type);
1492 } else {
1493 msg->body.decode.dt_luma_bottom_offset = msg->body.decode.dt_luma_top_offset;
1494 msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
1495 }
1496 msg->body.decode.dt_surf_tile_config = 0;
1497 break;
1498 }
1499 }
1500