1 /**************************************************************************
2 *
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "radeon_uvd_enc.h"
10
11 #include "pipe/p_video_codec.h"
12 #include "radeon_video.h"
13 #include "radeonsi/si_pipe.h"
14 #include "util/u_memory.h"
15 #include "util/u_video.h"
16 #include "vl/vl_video_buffer.h"
17
18 #include <stdio.h>
19
20 #define UVD_HEVC_LEVEL_1 30
21 #define UVD_HEVC_LEVEL_2 60
22 #define UVD_HEVC_LEVEL_2_1 63
23 #define UVD_HEVC_LEVEL_3 90
24 #define UVD_HEVC_LEVEL_3_1 93
25 #define UVD_HEVC_LEVEL_4 120
26 #define UVD_HEVC_LEVEL_4_1 123
27 #define UVD_HEVC_LEVEL_5 150
28 #define UVD_HEVC_LEVEL_5_1 153
29 #define UVD_HEVC_LEVEL_5_2 156
30 #define UVD_HEVC_LEVEL_6 180
31 #define UVD_HEVC_LEVEL_6_1 183
32 #define UVD_HEVC_LEVEL_6_2 186
33
radeon_uvd_enc_get_vui_param(struct radeon_uvd_encoder * enc,struct pipe_h265_enc_picture_desc * pic)34 static void radeon_uvd_enc_get_vui_param(struct radeon_uvd_encoder *enc,
35 struct pipe_h265_enc_picture_desc *pic)
36 {
37 enc->enc_pic.vui_info.vui_parameters_present_flag =
38 pic->seq.vui_parameters_present_flag;
39 enc->enc_pic.vui_info.flags.aspect_ratio_info_present_flag =
40 pic->seq.vui_flags.aspect_ratio_info_present_flag;
41 enc->enc_pic.vui_info.flags.timing_info_present_flag =
42 pic->seq.vui_flags.timing_info_present_flag;
43 enc->enc_pic.vui_info.flags.video_signal_type_present_flag =
44 pic->seq.vui_flags.video_signal_type_present_flag;
45 enc->enc_pic.vui_info.flags.colour_description_present_flag =
46 pic->seq.vui_flags.colour_description_present_flag;
47 enc->enc_pic.vui_info.flags.chroma_loc_info_present_flag =
48 pic->seq.vui_flags.chroma_loc_info_present_flag;
49 enc->enc_pic.vui_info.aspect_ratio_idc = pic->seq.aspect_ratio_idc;
50 enc->enc_pic.vui_info.sar_width = pic->seq.sar_width;
51 enc->enc_pic.vui_info.sar_height = pic->seq.sar_height;
52 enc->enc_pic.vui_info.num_units_in_tick = pic->seq.num_units_in_tick;
53 enc->enc_pic.vui_info.time_scale = pic->seq.time_scale;
54 enc->enc_pic.vui_info.video_format = pic->seq.video_format;
55 enc->enc_pic.vui_info.video_full_range_flag = pic->seq.video_full_range_flag;
56 enc->enc_pic.vui_info.colour_primaries = pic->seq.colour_primaries;
57 enc->enc_pic.vui_info.transfer_characteristics = pic->seq.transfer_characteristics;
58 enc->enc_pic.vui_info.matrix_coefficients = pic->seq.matrix_coefficients;
59 enc->enc_pic.vui_info.chroma_sample_loc_type_top_field =
60 pic->seq.chroma_sample_loc_type_top_field;
61 enc->enc_pic.vui_info.chroma_sample_loc_type_bottom_field =
62 pic->seq.chroma_sample_loc_type_bottom_field;
63 }
64
radeon_uvd_enc_get_param(struct radeon_uvd_encoder * enc,struct pipe_h265_enc_picture_desc * pic)65 static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
66 struct pipe_h265_enc_picture_desc *pic)
67 {
68 enc->enc_pic.picture_type = pic->picture_type;
69 enc->enc_pic.frame_num = pic->frame_num;
70 enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
71 enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
72 enc->enc_pic.not_referenced = pic->not_referenced;
73 enc->enc_pic.is_iframe = (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) ||
74 (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_I);
75
76 if (pic->seq.conformance_window_flag) {
77 enc->enc_pic.crop_left = pic->seq.conf_win_left_offset;
78 enc->enc_pic.crop_right = pic->seq.conf_win_right_offset;
79 enc->enc_pic.crop_top = pic->seq.conf_win_top_offset;
80 enc->enc_pic.crop_bottom = pic->seq.conf_win_bottom_offset;
81 } else {
82 enc->enc_pic.crop_left = 0;
83 enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
84 enc->enc_pic.crop_top = 0;
85 enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
86 }
87
88 enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
89 enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
90 enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
91 enc->enc_pic.max_poc = MAX2(16, util_next_power_of_two(pic->seq.intra_period));
92 enc->enc_pic.log2_max_poc = 0;
93 for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
94 i = (i >> 1);
95 enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
96 enc->enc_pic.pic_width_in_luma_samples = pic->seq.pic_width_in_luma_samples;
97 enc->enc_pic.pic_height_in_luma_samples = pic->seq.pic_height_in_luma_samples;
98 enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
99 pic->seq.log2_diff_max_min_luma_coding_block_size;
100 enc->enc_pic.log2_min_transform_block_size_minus2 =
101 pic->seq.log2_min_transform_block_size_minus2;
102 enc->enc_pic.log2_diff_max_min_transform_block_size =
103 pic->seq.log2_diff_max_min_transform_block_size;
104 enc->enc_pic.max_transform_hierarchy_depth_inter = pic->seq.max_transform_hierarchy_depth_inter;
105 enc->enc_pic.max_transform_hierarchy_depth_intra = pic->seq.max_transform_hierarchy_depth_intra;
106 enc->enc_pic.log2_parallel_merge_level_minus2 = pic->pic.log2_parallel_merge_level_minus2;
107 enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
108 enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
109 enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
110 enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
111 enc->enc_pic.sample_adaptive_offset_enabled_flag = pic->seq.sample_adaptive_offset_enabled_flag;
112 enc->enc_pic.pcm_enabled_flag = 0; /*HW not support PCM */
113 enc->enc_pic.sps_temporal_mvp_enabled_flag = pic->seq.sps_temporal_mvp_enabled_flag;
114 radeon_uvd_enc_get_vui_param(enc, pic);
115 }
116
flush(struct radeon_uvd_encoder * enc)117 static void flush(struct radeon_uvd_encoder *enc)
118 {
119 enc->ws->cs_flush(&enc->cs, PIPE_FLUSH_ASYNC, NULL);
120 }
121
radeon_uvd_enc_flush(struct pipe_video_codec * encoder)122 static void radeon_uvd_enc_flush(struct pipe_video_codec *encoder)
123 {
124 struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
125 flush(enc);
126 }
127
radeon_uvd_enc_cs_flush(void * ctx,unsigned flags,struct pipe_fence_handle ** fence)128 static void radeon_uvd_enc_cs_flush(void *ctx, unsigned flags, struct pipe_fence_handle **fence)
129 {
130 // just ignored
131 }
132
get_cpb_num(struct radeon_uvd_encoder * enc)133 static unsigned get_cpb_num(struct radeon_uvd_encoder *enc)
134 {
135 unsigned w = align(enc->base.width, 16) / 16;
136 unsigned h = align(enc->base.height, 16) / 16;
137 unsigned dpb;
138
139 switch (enc->base.level) {
140 case UVD_HEVC_LEVEL_1:
141 dpb = 36864;
142 break;
143
144 case UVD_HEVC_LEVEL_2:
145 dpb = 122880;
146 break;
147
148 case UVD_HEVC_LEVEL_2_1:
149 dpb = 245760;
150 break;
151
152 case UVD_HEVC_LEVEL_3:
153 dpb = 552960;
154 break;
155
156 case UVD_HEVC_LEVEL_3_1:
157 dpb = 983040;
158 break;
159
160 case UVD_HEVC_LEVEL_4:
161 case UVD_HEVC_LEVEL_4_1:
162 dpb = 2228224;
163 break;
164
165 case UVD_HEVC_LEVEL_5:
166 case UVD_HEVC_LEVEL_5_1:
167 case UVD_HEVC_LEVEL_5_2:
168 dpb = 8912896;
169 break;
170
171 case UVD_HEVC_LEVEL_6:
172 case UVD_HEVC_LEVEL_6_1:
173 case UVD_HEVC_LEVEL_6_2:
174 default:
175 dpb = 35651584;
176 break;
177 }
178
179 return MIN2(dpb / (w * h), 16);
180 }
181
radeon_uvd_enc_begin_frame(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_picture_desc * picture)182 static void radeon_uvd_enc_begin_frame(struct pipe_video_codec *encoder,
183 struct pipe_video_buffer *source,
184 struct pipe_picture_desc *picture)
185 {
186 struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
187 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
188
189 radeon_uvd_enc_get_param(enc, (struct pipe_h265_enc_picture_desc *)picture);
190
191 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
192 enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
193
194 enc->need_feedback = false;
195
196 if (!enc->stream_handle) {
197 struct rvid_buffer fb;
198 enc->stream_handle = si_vid_alloc_stream_handle();
199 enc->si = CALLOC_STRUCT(rvid_buffer);
200 si_vid_create_buffer(enc->screen, enc->si, 128 * 1024, PIPE_USAGE_STAGING);
201 si_vid_create_buffer(enc->screen, &fb, 4096, PIPE_USAGE_STAGING);
202 enc->fb = &fb;
203 enc->begin(enc, picture);
204 flush(enc);
205 si_vid_destroy_buffer(&fb);
206 }
207 }
208
radeon_uvd_enc_encode_bitstream(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_resource * destination,void ** fb)209 static void radeon_uvd_enc_encode_bitstream(struct pipe_video_codec *encoder,
210 struct pipe_video_buffer *source,
211 struct pipe_resource *destination, void **fb)
212 {
213 struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
214 enc->get_buffer(destination, &enc->bs_handle, NULL);
215 enc->bs_size = destination->width0;
216
217 *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
218
219 if (!si_vid_create_buffer(enc->screen, enc->fb, 4096, PIPE_USAGE_STAGING)) {
220 RVID_ERR("Can't create feedback buffer.\n");
221 return;
222 }
223
224 enc->need_feedback = true;
225 enc->encode(enc);
226 }
227
radeon_uvd_enc_end_frame(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_picture_desc * picture)228 static void radeon_uvd_enc_end_frame(struct pipe_video_codec *encoder,
229 struct pipe_video_buffer *source,
230 struct pipe_picture_desc *picture)
231 {
232 struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
233 flush(enc);
234 }
235
radeon_uvd_enc_destroy(struct pipe_video_codec * encoder)236 static void radeon_uvd_enc_destroy(struct pipe_video_codec *encoder)
237 {
238 struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
239
240 if (enc->stream_handle) {
241 struct rvid_buffer fb;
242 enc->need_feedback = false;
243 si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
244 enc->fb = &fb;
245 enc->destroy(enc);
246 flush(enc);
247 if (enc->si) {
248 si_vid_destroy_buffer(enc->si);
249 FREE(enc->si);
250 }
251 si_vid_destroy_buffer(&fb);
252 }
253
254 si_vid_destroy_buffer(&enc->cpb);
255 enc->ws->cs_destroy(&enc->cs);
256 FREE(enc);
257 }
258
radeon_uvd_enc_get_feedback(struct pipe_video_codec * encoder,void * feedback,unsigned * size,struct pipe_enc_feedback_metadata * metadata)259 static void radeon_uvd_enc_get_feedback(struct pipe_video_codec *encoder, void *feedback,
260 unsigned *size, struct pipe_enc_feedback_metadata* metadata)
261 {
262 struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
263 struct rvid_buffer *fb = feedback;
264
265 if (NULL != size) {
266 radeon_uvd_enc_feedback_t *fb_data = (radeon_uvd_enc_feedback_t *)enc->ws->buffer_map(
267 enc->ws, fb->res->buf, &enc->cs, PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY);
268
269 if (!fb_data->status)
270 *size = fb_data->bitstream_size;
271 else
272 *size = 0;
273 enc->ws->buffer_unmap(enc->ws, fb->res->buf);
274 }
275
276 si_vid_destroy_buffer(fb);
277 FREE(fb);
278 }
279
radeon_uvd_enc_destroy_fence(struct pipe_video_codec * encoder,struct pipe_fence_handle * fence)280 static void radeon_uvd_enc_destroy_fence(struct pipe_video_codec *encoder,
281 struct pipe_fence_handle *fence)
282 {
283 struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
284
285 enc->ws->fence_reference(enc->ws, &fence, NULL);
286 }
287
radeon_uvd_create_encoder(struct pipe_context * context,const struct pipe_video_codec * templ,struct radeon_winsys * ws,radeon_uvd_enc_get_buffer get_buffer)288 struct pipe_video_codec *radeon_uvd_create_encoder(struct pipe_context *context,
289 const struct pipe_video_codec *templ,
290 struct radeon_winsys *ws,
291 radeon_uvd_enc_get_buffer get_buffer)
292 {
293 struct si_screen *sscreen = (struct si_screen *)context->screen;
294 struct si_context *sctx = (struct si_context *)context;
295 struct radeon_uvd_encoder *enc;
296 struct pipe_video_buffer *tmp_buf, templat = {};
297 struct radeon_surf *tmp_surf;
298 unsigned cpb_size;
299
300 if (!si_radeon_uvd_enc_supported(sscreen)) {
301 RVID_ERR("Unsupported UVD ENC fw version loaded!\n");
302 return NULL;
303 }
304
305 enc = CALLOC_STRUCT(radeon_uvd_encoder);
306
307 if (!enc)
308 return NULL;
309
310 enc->base = *templ;
311 enc->base.context = context;
312 enc->base.destroy = radeon_uvd_enc_destroy;
313 enc->base.begin_frame = radeon_uvd_enc_begin_frame;
314 enc->base.encode_bitstream = radeon_uvd_enc_encode_bitstream;
315 enc->base.end_frame = radeon_uvd_enc_end_frame;
316 enc->base.flush = radeon_uvd_enc_flush;
317 enc->base.get_feedback = radeon_uvd_enc_get_feedback;
318 enc->base.destroy_fence = radeon_uvd_enc_destroy_fence;
319 enc->get_buffer = get_buffer;
320 enc->bits_in_shifter = 0;
321 enc->screen = context->screen;
322 enc->ws = ws;
323
324 if (!ws->cs_create(&enc->cs, sctx->ctx, AMD_IP_UVD_ENC, radeon_uvd_enc_cs_flush, enc)) {
325 RVID_ERR("Can't get command submission context.\n");
326 goto error;
327 }
328
329 templat.buffer_format = PIPE_FORMAT_NV12;
330 templat.width = enc->base.width;
331 templat.height = enc->base.height;
332 templat.interlaced = false;
333
334 if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
335 RVID_ERR("Can't create video buffer.\n");
336 goto error;
337 }
338
339 enc->cpb_num = get_cpb_num(enc);
340
341 if (!enc->cpb_num)
342 goto error;
343
344 get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
345
346 cpb_size = (sscreen->info.gfx_level < GFX9)
347 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
348 align(tmp_surf->u.legacy.level[0].nblk_y, 32)
349 : align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
350 align(tmp_surf->u.gfx9.surf_height, 32);
351
352 cpb_size = cpb_size * 3 / 2;
353 cpb_size = cpb_size * enc->cpb_num;
354 tmp_buf->destroy(tmp_buf);
355
356 if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
357 RVID_ERR("Can't create CPB buffer.\n");
358 goto error;
359 }
360
361 radeon_uvd_enc_1_1_init(enc);
362
363 return &enc->base;
364
365 error:
366 enc->ws->cs_destroy(&enc->cs);
367
368 si_vid_destroy_buffer(&enc->cpb);
369
370 FREE(enc);
371 return NULL;
372 }
373
si_radeon_uvd_enc_supported(struct si_screen * sscreen)374 bool si_radeon_uvd_enc_supported(struct si_screen *sscreen)
375 {
376 return sscreen->info.ip[AMD_IP_UVD_ENC].num_queues;
377 }
378