1 /**************************************************************************
2 *
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "pipe/p_video_codec.h"
10 #include "radeon_uvd_enc.h"
11 #include "radeon_video.h"
12 #include "radeonsi/si_pipe.h"
13 #include "util/u_memory.h"
14 #include "util/u_video.h"
15 #include "vl/vl_video_buffer.h"
16
17 #include <stdio.h>
18
19 #define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value))
20 #define RADEON_ENC_BEGIN(cmd) \
21 { \
22 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \
23 RADEON_ENC_CS(cmd)
24 #define RADEON_ENC_READ(buf, domain, off) \
25 radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
26 #define RADEON_ENC_WRITE(buf, domain, off) \
27 radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
28 #define RADEON_ENC_READWRITE(buf, domain, off) \
29 radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
30 #define RADEON_ENC_END() \
31 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \
32 enc->total_task_size += *begin; \
33 }
34
35 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
36
radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder * enc,struct pb_buffer_lean * buf,unsigned usage,enum radeon_bo_domain domain,signed offset)37 static void radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc, struct pb_buffer_lean *buf,
38 unsigned usage, enum radeon_bo_domain domain,
39 signed offset)
40 {
41 enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
42 uint64_t addr;
43 addr = enc->ws->buffer_get_virtual_address(buf);
44 addr = addr + offset;
45 RADEON_ENC_CS(addr >> 32);
46 RADEON_ENC_CS(addr);
47 }
48
radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder * enc,bool set)49 static void radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc, bool set)
50 {
51 if (set != enc->emulation_prevention) {
52 enc->emulation_prevention = set;
53 enc->num_zeros = 0;
54 }
55 }
56
radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder * enc,unsigned char byte)57 static void radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc, unsigned char byte)
58 {
59 if (enc->byte_index == 0)
60 enc->cs.current.buf[enc->cs.current.cdw] = 0;
61 enc->cs.current.buf[enc->cs.current.cdw] |=
62 ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
63 enc->byte_index++;
64
65 if (enc->byte_index >= 4) {
66 enc->byte_index = 0;
67 enc->cs.current.cdw++;
68 }
69 }
70
radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder * enc,unsigned char byte)71 static void radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc, unsigned char byte)
72 {
73 if (enc->emulation_prevention) {
74 if ((enc->num_zeros >= 2) &&
75 ((byte == 0x00) || (byte == 0x01) || (byte == 0x02) || (byte == 0x03))) {
76 radeon_uvd_enc_output_one_byte(enc, 0x03);
77 enc->bits_output += 8;
78 enc->num_zeros = 0;
79 }
80 enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
81 }
82 }
83
radeon_uvd_enc_code_fixed_bits(struct radeon_uvd_encoder * enc,unsigned int value,unsigned int num_bits)84 static void radeon_uvd_enc_code_fixed_bits(struct radeon_uvd_encoder *enc, unsigned int value,
85 unsigned int num_bits)
86 {
87 unsigned int bits_to_pack = 0;
88
89 while (num_bits > 0) {
90 unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
91 bits_to_pack =
92 num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
93
94 if (bits_to_pack < num_bits)
95 value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
96
97 enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
98 num_bits -= bits_to_pack;
99 enc->bits_in_shifter += bits_to_pack;
100
101 while (enc->bits_in_shifter >= 8) {
102 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
103 enc->shifter <<= 8;
104 radeon_uvd_enc_emulation_prevention(enc, output_byte);
105 radeon_uvd_enc_output_one_byte(enc, output_byte);
106 enc->bits_in_shifter -= 8;
107 enc->bits_output += 8;
108 }
109 }
110 }
111
radeon_uvd_enc_reset(struct radeon_uvd_encoder * enc)112 static void radeon_uvd_enc_reset(struct radeon_uvd_encoder *enc)
113 {
114 enc->emulation_prevention = false;
115 enc->shifter = 0;
116 enc->bits_in_shifter = 0;
117 enc->bits_output = 0;
118 enc->num_zeros = 0;
119 enc->byte_index = 0;
120 }
121
radeon_uvd_enc_byte_align(struct radeon_uvd_encoder * enc)122 static void radeon_uvd_enc_byte_align(struct radeon_uvd_encoder *enc)
123 {
124 unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
125
126 if (num_padding_zeros > 0)
127 radeon_uvd_enc_code_fixed_bits(enc, 0, num_padding_zeros);
128 }
129
radeon_uvd_enc_flush_headers(struct radeon_uvd_encoder * enc)130 static void radeon_uvd_enc_flush_headers(struct radeon_uvd_encoder *enc)
131 {
132 if (enc->bits_in_shifter != 0) {
133 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
134 radeon_uvd_enc_emulation_prevention(enc, output_byte);
135 radeon_uvd_enc_output_one_byte(enc, output_byte);
136 enc->bits_output += enc->bits_in_shifter;
137 enc->shifter = 0;
138 enc->bits_in_shifter = 0;
139 enc->num_zeros = 0;
140 }
141
142 if (enc->byte_index > 0) {
143 enc->cs.current.cdw++;
144 enc->byte_index = 0;
145 }
146 }
147
radeon_uvd_enc_code_ue(struct radeon_uvd_encoder * enc,unsigned int value)148 static void radeon_uvd_enc_code_ue(struct radeon_uvd_encoder *enc, unsigned int value)
149 {
150 int x = -1;
151 unsigned int ue_code = value + 1;
152 value += 1;
153
154 while (value) {
155 value = (value >> 1);
156 x += 1;
157 }
158
159 unsigned int ue_length = (x << 1) + 1;
160 radeon_uvd_enc_code_fixed_bits(enc, ue_code, ue_length);
161 }
162
radeon_uvd_enc_code_se(struct radeon_uvd_encoder * enc,int value)163 static void radeon_uvd_enc_code_se(struct radeon_uvd_encoder *enc, int value)
164 {
165 unsigned int v = 0;
166
167 if (value != 0)
168 v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
169
170 radeon_uvd_enc_code_ue(enc, v);
171 }
172
radeon_uvd_enc_session_info(struct radeon_uvd_encoder * enc)173 static void radeon_uvd_enc_session_info(struct radeon_uvd_encoder *enc)
174 {
175 unsigned int interface_version =
176 ((RENC_UVD_FW_INTERFACE_MAJOR_VERSION << RENC_UVD_IF_MAJOR_VERSION_SHIFT) |
177 (RENC_UVD_FW_INTERFACE_MINOR_VERSION << RENC_UVD_IF_MINOR_VERSION_SHIFT));
178 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INFO);
179 RADEON_ENC_CS(0x00000000); // reserved
180 RADEON_ENC_CS(interface_version);
181 RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
182 RADEON_ENC_END();
183 }
184
radeon_uvd_enc_task_info(struct radeon_uvd_encoder * enc,bool need_feedback)185 static void radeon_uvd_enc_task_info(struct radeon_uvd_encoder *enc, bool need_feedback)
186 {
187 enc->enc_pic.task_info.task_id++;
188
189 if (need_feedback)
190 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
191 else
192 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
193
194 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_TASK_INFO);
195 enc->p_task_size = &enc->cs.current.buf[enc->cs.current.cdw++];
196 RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
197 RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
198 RADEON_ENC_END();
199 }
200
radeon_uvd_enc_session_init_hevc(struct radeon_uvd_encoder * enc)201 static void radeon_uvd_enc_session_init_hevc(struct radeon_uvd_encoder *enc)
202 {
203 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
204 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
205 enc->enc_pic.session_init.padding_width =
206 enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
207 enc->enc_pic.session_init.padding_height =
208 enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
209 enc->enc_pic.session_init.pre_encode_mode = RENC_UVD_PREENCODE_MODE_NONE;
210 enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
211
212 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INIT);
213 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
214 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
215 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
216 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
217 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
218 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
219 RADEON_ENC_END();
220 }
221
radeon_uvd_enc_layer_control(struct radeon_uvd_encoder * enc)222 static void radeon_uvd_enc_layer_control(struct radeon_uvd_encoder *enc)
223 {
224 enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
225 enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
226
227 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_CONTROL);
228 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
229 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
230 RADEON_ENC_END();
231 }
232
radeon_uvd_enc_layer_select(struct radeon_uvd_encoder * enc)233 static void radeon_uvd_enc_layer_select(struct radeon_uvd_encoder *enc)
234 {
235 enc->enc_pic.layer_sel.temporal_layer_index = 0;
236
237 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_SELECT);
238 RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
239 RADEON_ENC_END();
240 }
241
radeon_uvd_enc_slice_control_hevc(struct radeon_uvd_encoder * enc)242 static void radeon_uvd_enc_slice_control_hevc(struct radeon_uvd_encoder *enc)
243 {
244 enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS;
245 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
246 align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
247 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
248 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
249
250 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SLICE_CONTROL);
251 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
252 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
253 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
254 RADEON_ENC_END();
255 }
256
radeon_uvd_enc_spec_misc_hevc(struct radeon_uvd_encoder * enc,struct pipe_picture_desc * picture)257 static void radeon_uvd_enc_spec_misc_hevc(struct radeon_uvd_encoder *enc,
258 struct pipe_picture_desc *picture)
259 {
260 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
261 enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 =
262 pic->seq.log2_min_luma_coding_block_size_minus3;
263 enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
264 enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled =
265 pic->seq.strong_intra_smoothing_enabled_flag;
266 enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = pic->pic.constrained_intra_pred_flag;
267 enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
268 enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
269 enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
270
271 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SPEC_MISC);
272 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
273 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
274 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
275 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
276 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
277 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
278 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
279 RADEON_ENC_END();
280 }
281
radeon_uvd_enc_rc_session_init(struct radeon_uvd_encoder * enc,struct pipe_picture_desc * picture)282 static void radeon_uvd_enc_rc_session_init(struct radeon_uvd_encoder *enc,
283 struct pipe_picture_desc *picture)
284 {
285 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
286 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
287 switch (pic->rc.rate_ctrl_method) {
288 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_DISABLE:
289 enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_NONE;
290 break;
291 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
292 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT:
293 enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_CBR;
294 break;
295 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
296 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE:
297 enc->enc_pic.rc_session_init.rate_control_method =
298 RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
299 break;
300 default:
301 enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_NONE;
302 }
303
304 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT);
305 RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
306 RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
307 RADEON_ENC_END();
308 }
309
radeon_uvd_enc_rc_layer_init(struct radeon_uvd_encoder * enc,struct pipe_picture_desc * picture)310 static void radeon_uvd_enc_rc_layer_init(struct radeon_uvd_encoder *enc,
311 struct pipe_picture_desc *picture)
312 {
313 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
314 enc->enc_pic.rc_layer_init.target_bit_rate = pic->rc.target_bitrate;
315 enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rc.peak_bitrate;
316 enc->enc_pic.rc_layer_init.frame_rate_num = pic->rc.frame_rate_num;
317 enc->enc_pic.rc_layer_init.frame_rate_den = pic->rc.frame_rate_den;
318 enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rc.vbv_buffer_size;
319 enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rc.target_bits_picture;
320 enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rc.peak_bits_picture_integer;
321 enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rc.peak_bits_picture_fraction;
322
323 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT);
324 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
325 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
326 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
327 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
328 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
329 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
330 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
331 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
332 RADEON_ENC_END();
333 }
334
radeon_uvd_enc_deblocking_filter_hevc(struct radeon_uvd_encoder * enc,struct pipe_picture_desc * picture)335 static void radeon_uvd_enc_deblocking_filter_hevc(struct radeon_uvd_encoder *enc,
336 struct pipe_picture_desc *picture)
337 {
338 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
339 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
340 pic->slice.slice_loop_filter_across_slices_enabled_flag;
341 enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
342 pic->slice.slice_deblocking_filter_disabled_flag;
343 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
344 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
345 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
346 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
347
348 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_DEBLOCKING_FILTER);
349 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
350 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
351 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
352 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
353 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
354 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
355 RADEON_ENC_END();
356 }
357
radeon_uvd_enc_quality_params(struct radeon_uvd_encoder * enc)358 static void radeon_uvd_enc_quality_params(struct radeon_uvd_encoder *enc)
359 {
360 enc->enc_pic.quality_params.vbaq_mode = 0;
361 enc->enc_pic.quality_params.scene_change_sensitivity = 0;
362 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
363
364 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_QUALITY_PARAMS);
365 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
366 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
367 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
368 RADEON_ENC_END();
369 }
370
radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder * enc)371 static void radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
372 {
373 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
374 RADEON_ENC_CS(RENC_UVD_NALU_TYPE_SPS);
375 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
376 int i;
377
378 radeon_uvd_enc_reset(enc);
379 radeon_uvd_enc_set_emulation_prevention(enc, false);
380 radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
381 radeon_uvd_enc_code_fixed_bits(enc, 0x4201, 16);
382 radeon_uvd_enc_byte_align(enc);
383 radeon_uvd_enc_set_emulation_prevention(enc, true);
384 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 4);
385 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
386 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
387 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
388 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
389 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
390 radeon_uvd_enc_code_fixed_bits(enc, 0x60000000, 32);
391 radeon_uvd_enc_code_fixed_bits(enc, 0xb0000000, 32);
392 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 16);
393 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
394
395 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
396 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
397
398 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
399 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
400 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
401 }
402
403 radeon_uvd_enc_code_ue(enc, 0x0);
404 radeon_uvd_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
405 radeon_uvd_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
406 radeon_uvd_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
407
408 int conformance_window_flag = (enc->enc_pic.crop_top > 0) || (enc->enc_pic.crop_bottom > 0) ||
409 (enc->enc_pic.crop_left > 0) || (enc->enc_pic.crop_right > 0)
410 ? 0x1
411 : 0x0;
412 radeon_uvd_enc_code_fixed_bits(enc, conformance_window_flag, 1);
413
414 if (conformance_window_flag == 1) {
415 radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_left);
416 radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_right);
417 radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_top);
418 radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_bottom);
419 }
420
421 radeon_uvd_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
422 radeon_uvd_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
423 radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
424 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
425 radeon_uvd_enc_code_ue(enc, 1);
426 radeon_uvd_enc_code_ue(enc, 0x0);
427 radeon_uvd_enc_code_ue(enc, 0x0);
428 radeon_uvd_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
429 /* Only support CTBSize 64 */
430 radeon_uvd_enc_code_ue(
431 enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
432 radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
433 radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
434 radeon_uvd_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
435 radeon_uvd_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
436
437 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
438 radeon_uvd_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
439 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
440 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
441
442 radeon_uvd_enc_code_ue(enc, 1);
443 radeon_uvd_enc_code_ue(enc, 1);
444 radeon_uvd_enc_code_ue(enc, 0);
445 radeon_uvd_enc_code_ue(enc, 0);
446 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
447
448 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
449
450 radeon_uvd_enc_code_fixed_bits(enc, 0, 1);
451 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled,
452 1);
453
454 radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.vui_parameters_present_flag), 1);
455 if (enc->enc_pic.vui_info.vui_parameters_present_flag) {
456 /* aspect ratio present flag */
457 radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.flags.aspect_ratio_info_present_flag), 1);
458 if (enc->enc_pic.vui_info.flags.aspect_ratio_info_present_flag) {
459 radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.aspect_ratio_idc), 8);
460 if (enc->enc_pic.vui_info.aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
461 radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.sar_width), 16);
462 radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.sar_height), 16);
463 }
464 }
465 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* overscan info present flag */
466 /* video signal type present flag */
467 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.flags.video_signal_type_present_flag, 1);
468 if (enc->enc_pic.vui_info.flags.video_signal_type_present_flag) {
469 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.video_format, 3);
470 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.video_full_range_flag, 1);
471 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.flags.colour_description_present_flag, 1);
472 if (enc->enc_pic.vui_info.flags.colour_description_present_flag) {
473 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.colour_primaries, 8);
474 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.transfer_characteristics, 8);
475 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.matrix_coefficients, 8);
476 }
477 }
478 /* chroma loc info present flag */
479 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.flags.chroma_loc_info_present_flag, 1);
480 if (enc->enc_pic.vui_info.flags.chroma_loc_info_present_flag) {
481 radeon_uvd_enc_code_ue(enc, enc->enc_pic.vui_info.chroma_sample_loc_type_top_field);
482 radeon_uvd_enc_code_ue(enc, enc->enc_pic.vui_info.chroma_sample_loc_type_bottom_field);
483 }
484 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* neutral chroma indication flag */
485 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* field seq flag */
486 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* frame field info present flag */
487 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* default display windows flag */
488 /* vui timing info present flag */
489 radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.flags.timing_info_present_flag), 1);
490 if (enc->enc_pic.vui_info.flags.timing_info_present_flag) {
491 radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.num_units_in_tick), 32);
492 radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.time_scale), 32);
493 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
494 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
495 }
496 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* bitstream restriction flag */
497 }
498
499 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
500
501 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
502
503 radeon_uvd_enc_byte_align(enc);
504 radeon_uvd_enc_flush_headers(enc);
505 *size_in_bytes = (enc->bits_output + 7) / 8;
506 RADEON_ENC_END();
507 }
508
radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder * enc)509 static void radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
510 {
511 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
512 RADEON_ENC_CS(RENC_UVD_NALU_TYPE_PPS);
513 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
514 radeon_uvd_enc_reset(enc);
515 radeon_uvd_enc_set_emulation_prevention(enc, false);
516 radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
517 radeon_uvd_enc_code_fixed_bits(enc, 0x4401, 16);
518 radeon_uvd_enc_byte_align(enc);
519 radeon_uvd_enc_set_emulation_prevention(enc, true);
520 radeon_uvd_enc_code_ue(enc, 0x0);
521 radeon_uvd_enc_code_ue(enc, 0x0);
522 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
523 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* output_flag_resent_flag */
524 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 3); /* num_extra_slice_header_bits */
525 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
526 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
527 radeon_uvd_enc_code_ue(enc, 0x0);
528 radeon_uvd_enc_code_ue(enc, 0x0);
529 radeon_uvd_enc_code_se(enc, 0x0);
530 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
531 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
532 if (enc->enc_pic.rc_session_init.rate_control_method == RENC_UVD_RATE_CONTROL_METHOD_NONE)
533 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
534 else {
535 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
536 radeon_uvd_enc_code_ue(enc, 0x0);
537 }
538 radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
539 radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
540 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
541 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
542 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
543 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
544 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
545 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled,
546 1);
547 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
548 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
549 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
550
551 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
552 radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
553 radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
554 }
555
556 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
557 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
558 radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
559 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
560
561 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
562
563 radeon_uvd_enc_byte_align(enc);
564 radeon_uvd_enc_flush_headers(enc);
565 *size_in_bytes = (enc->bits_output + 7) / 8;
566 RADEON_ENC_END();
567 }
568
radeon_uvd_enc_nalu_vps_hevc(struct radeon_uvd_encoder * enc)569 static void radeon_uvd_enc_nalu_vps_hevc(struct radeon_uvd_encoder *enc)
570 {
571 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
572 RADEON_ENC_CS(RENC_UVD_NALU_TYPE_VPS);
573 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
574 int i;
575
576 radeon_uvd_enc_reset(enc);
577 radeon_uvd_enc_set_emulation_prevention(enc, false);
578 radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
579 radeon_uvd_enc_code_fixed_bits(enc, 0x4001, 16);
580 radeon_uvd_enc_byte_align(enc);
581 radeon_uvd_enc_set_emulation_prevention(enc, true);
582
583 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 4);
584 radeon_uvd_enc_code_fixed_bits(enc, 0x3, 2);
585 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
586 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
587 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
588 radeon_uvd_enc_code_fixed_bits(enc, 0xffff, 16);
589 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
590 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
591 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
592 radeon_uvd_enc_code_fixed_bits(enc, 0x60000000, 32);
593 radeon_uvd_enc_code_fixed_bits(enc, 0xb0000000, 32);
594 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 16);
595 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
596
597 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
598 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
599
600 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
601 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
602 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
603 }
604
605 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
606 radeon_uvd_enc_code_ue(enc, 0x1);
607 radeon_uvd_enc_code_ue(enc, 0x0);
608 radeon_uvd_enc_code_ue(enc, 0x0);
609
610 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
611 radeon_uvd_enc_code_ue(enc, 0x0);
612 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
613 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
614
615 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
616
617 radeon_uvd_enc_byte_align(enc);
618 radeon_uvd_enc_flush_headers(enc);
619 *size_in_bytes = (enc->bits_output + 7) / 8;
620 RADEON_ENC_END();
621 }
622
radeon_uvd_enc_nalu_aud_hevc(struct radeon_uvd_encoder * enc)623 static void radeon_uvd_enc_nalu_aud_hevc(struct radeon_uvd_encoder *enc)
624 {
625 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
626 RADEON_ENC_CS(RENC_UVD_NALU_TYPE_AUD);
627 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
628 radeon_uvd_enc_reset(enc);
629 radeon_uvd_enc_set_emulation_prevention(enc, false);
630 radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
631 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
632 radeon_uvd_enc_code_fixed_bits(enc, 35, 6);
633 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
634 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 3);
635 radeon_uvd_enc_byte_align(enc);
636 radeon_uvd_enc_set_emulation_prevention(enc, true);
637 switch (enc->enc_pic.picture_type) {
638 case PIPE_H2645_ENC_PICTURE_TYPE_I:
639 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
640 radeon_uvd_enc_code_fixed_bits(enc, 0x00, 3);
641 break;
642 case PIPE_H2645_ENC_PICTURE_TYPE_P:
643 radeon_uvd_enc_code_fixed_bits(enc, 0x01, 3);
644 break;
645 case PIPE_H2645_ENC_PICTURE_TYPE_B:
646 radeon_uvd_enc_code_fixed_bits(enc, 0x02, 3);
647 break;
648 default:
649 assert(0 && "Unsupported picture type!");
650 }
651
652 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
653
654 radeon_uvd_enc_byte_align(enc);
655 radeon_uvd_enc_flush_headers(enc);
656 *size_in_bytes = (enc->bits_output + 7) / 8;
657 RADEON_ENC_END();
658 }
659
radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder * enc)660 static void radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
661 {
662 uint32_t instruction[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
663 uint32_t num_bits[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
664 unsigned int inst_index = 0;
665 unsigned int bit_index = 0;
666 unsigned int bits_copied = 0;
667 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SLICE_HEADER);
668 radeon_uvd_enc_reset(enc);
669 radeon_uvd_enc_set_emulation_prevention(enc, false);
670
671 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
672 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
673 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
674 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 3);
675
676 radeon_uvd_enc_flush_headers(enc);
677 bit_index++;
678 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
679 num_bits[inst_index] = enc->bits_output - bits_copied;
680 bits_copied = enc->bits_output;
681 inst_index++;
682
683 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_FIRST_SLICE;
684 inst_index++;
685
686 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
687 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
688
689 radeon_uvd_enc_code_ue(enc, 0x0);
690
691 radeon_uvd_enc_flush_headers(enc);
692 bit_index++;
693 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
694 num_bits[inst_index] = enc->bits_output - bits_copied;
695 bits_copied = enc->bits_output;
696 inst_index++;
697
698 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_SLICE_SEGMENT;
699 inst_index++;
700
701 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
702 inst_index++;
703
704 switch (enc->enc_pic.picture_type) {
705 case PIPE_H2645_ENC_PICTURE_TYPE_I:
706 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
707 radeon_uvd_enc_code_ue(enc, 0x2);
708 break;
709 case PIPE_H2645_ENC_PICTURE_TYPE_P:
710 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
711 radeon_uvd_enc_code_ue(enc, 0x1);
712 break;
713 case PIPE_H2645_ENC_PICTURE_TYPE_B:
714 radeon_uvd_enc_code_ue(enc, 0x0);
715 break;
716 default:
717 radeon_uvd_enc_code_ue(enc, 0x1);
718 }
719
720 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
721 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
722 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P)
723 radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
724 else {
725 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
726 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
727 radeon_uvd_enc_code_ue(enc, 0x0);
728 radeon_uvd_enc_code_ue(enc, 0x0);
729 }
730 }
731
732 if (enc->enc_pic.sample_adaptive_offset_enabled_flag)
733 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* slice_sao_luma_flag */
734
735 if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
736 (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
737 radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
738 radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
739 radeon_uvd_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
740 }
741
742 radeon_uvd_enc_flush_headers(enc);
743 bit_index++;
744 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
745 num_bits[inst_index] = enc->bits_output - bits_copied;
746 bits_copied = enc->bits_output;
747 inst_index++;
748
749 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_SLICE_QP_DELTA;
750 inst_index++;
751
752 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
753 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
754 radeon_uvd_enc_code_fixed_bits(
755 enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
756
757 radeon_uvd_enc_flush_headers(enc);
758 bit_index++;
759 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
760 num_bits[inst_index] = enc->bits_output - bits_copied;
761 bits_copied = enc->bits_output;
762 inst_index++;
763 }
764
765 instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_END;
766
767 for (int i = bit_index; i < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
768 RADEON_ENC_CS(0x00000000);
769
770 for (int j = 0; j < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
771 RADEON_ENC_CS(instruction[j]);
772 RADEON_ENC_CS(num_bits[j]);
773 }
774
775 RADEON_ENC_END();
776 }
777
radeon_uvd_enc_ctx(struct radeon_uvd_encoder * enc)778 static void radeon_uvd_enc_ctx(struct radeon_uvd_encoder *enc)
779 {
780 struct si_screen *sscreen = (struct si_screen *)enc->screen;
781
782 enc->enc_pic.ctx_buf.swizzle_mode = 0;
783 if (sscreen->info.gfx_level < GFX9) {
784 enc->enc_pic.ctx_buf.rec_luma_pitch = (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
785 enc->enc_pic.ctx_buf.rec_chroma_pitch =
786 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
787 } else {
788 enc->enc_pic.ctx_buf.rec_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
789 enc->enc_pic.ctx_buf.rec_chroma_pitch = enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
790 }
791 enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
792
793 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER);
794 RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
795 RADEON_ENC_CS(0x00000000); // reserved
796 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
797 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
798 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
799 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
800 /* reconstructed_picture_1_luma_offset */
801 RADEON_ENC_CS(0x00000000);
802 /* reconstructed_picture_1_chroma_offset */
803 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch * align(enc->base.height, 16));
804 /* reconstructed_picture_2_luma_offset */
805 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch * align(enc->base.height, 16) * 3 / 2);
806 /* reconstructed_picture_2_chroma_offset */
807 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch * align(enc->base.height, 16) * 5 / 2);
808
809 for (int i = 0; i < 136; i++)
810 RADEON_ENC_CS(0x00000000);
811
812 RADEON_ENC_END();
813 }
814
radeon_uvd_enc_bitstream(struct radeon_uvd_encoder * enc)815 static void radeon_uvd_enc_bitstream(struct radeon_uvd_encoder *enc)
816 {
817 enc->enc_pic.bit_buf.mode = RENC_UVD_SWIZZLE_MODE_LINEAR;
818 enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
819 enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
820
821 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER);
822 RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
823 RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
824 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
825 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
826 RADEON_ENC_END();
827 }
828
radeon_uvd_enc_feedback(struct radeon_uvd_encoder * enc)829 static void radeon_uvd_enc_feedback(struct radeon_uvd_encoder *enc)
830 {
831 enc->enc_pic.fb_buf.mode = RENC_UVD_FEEDBACK_BUFFER_MODE_LINEAR;
832 enc->enc_pic.fb_buf.feedback_buffer_size = 16;
833 enc->enc_pic.fb_buf.feedback_data_size = 40;
834
835 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_FEEDBACK_BUFFER);
836 RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
837 RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
838 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
839 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
840 RADEON_ENC_END();
841 }
842
radeon_uvd_enc_intra_refresh(struct radeon_uvd_encoder * enc)843 static void radeon_uvd_enc_intra_refresh(struct radeon_uvd_encoder *enc)
844 {
845 enc->enc_pic.intra_ref.intra_refresh_mode = RENC_UVD_INTRA_REFRESH_MODE_NONE;
846 enc->enc_pic.intra_ref.offset = 0;
847 enc->enc_pic.intra_ref.region_size = 0;
848
849 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INTRA_REFRESH);
850 RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
851 RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
852 RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
853 RADEON_ENC_END();
854 }
855
radeon_uvd_enc_rc_per_pic(struct radeon_uvd_encoder * enc,struct pipe_picture_desc * picture)856 static void radeon_uvd_enc_rc_per_pic(struct radeon_uvd_encoder *enc,
857 struct pipe_picture_desc *picture)
858 {
859 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
860 enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
861 enc->enc_pic.rc_per_pic.min_qp_app = 0;
862 enc->enc_pic.rc_per_pic.max_qp_app = 51;
863 enc->enc_pic.rc_per_pic.max_au_size = 0;
864 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc.fill_data_enable;
865 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
866 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc.enforce_hrd;
867
868 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE);
869 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
870 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
871 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
872 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
873 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
874 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
875 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
876 RADEON_ENC_END();
877 }
878
radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder * enc)879 static void radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
880 {
881 struct si_screen *sscreen = (struct si_screen *)enc->screen;
882 switch (enc->enc_pic.picture_type) {
883 case PIPE_H2645_ENC_PICTURE_TYPE_I:
884 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
885 enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_I;
886 break;
887 case PIPE_H2645_ENC_PICTURE_TYPE_P:
888 enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_P;
889 break;
890 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
891 enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_P_SKIP;
892 break;
893 case PIPE_H2645_ENC_PICTURE_TYPE_B:
894 enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_B;
895 break;
896 default:
897 enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_I;
898 }
899
900 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
901 if (sscreen->info.gfx_level < GFX9) {
902 enc->enc_pic.enc_params.input_pic_luma_pitch =
903 (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
904 enc->enc_pic.enc_params.input_pic_chroma_pitch =
905 (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
906 } else {
907 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
908 enc->enc_pic.enc_params.input_pic_chroma_pitch =
909 enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
910 }
911 enc->enc_pic.enc_params.input_pic_swizzle_mode = RENC_UVD_SWIZZLE_MODE_LINEAR;
912
913 if (enc->enc_pic.enc_params.pic_type == RENC_UVD_PICTURE_TYPE_I)
914 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
915 else
916 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
917
918 enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
919
920 RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_ENCODE_PARAMS);
921 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
922 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
923
924 if (sscreen->info.gfx_level < GFX9) {
925 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256);
926 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256);
927 } else {
928 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
929 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
930 }
931 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
932 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
933 RADEON_ENC_CS(0x00000000); // reserved
934 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
935 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
936 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
937 RADEON_ENC_END();
938 }
939
radeon_uvd_enc_op_init(struct radeon_uvd_encoder * enc)940 static void radeon_uvd_enc_op_init(struct radeon_uvd_encoder *enc)
941 {
942 RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INITIALIZE);
943 RADEON_ENC_END();
944 }
945
radeon_uvd_enc_op_close(struct radeon_uvd_encoder * enc)946 static void radeon_uvd_enc_op_close(struct radeon_uvd_encoder *enc)
947 {
948 RADEON_ENC_BEGIN(RENC_UVD_IB_OP_CLOSE_SESSION);
949 RADEON_ENC_END();
950 }
951
radeon_uvd_enc_op_enc(struct radeon_uvd_encoder * enc)952 static void radeon_uvd_enc_op_enc(struct radeon_uvd_encoder *enc)
953 {
954 RADEON_ENC_BEGIN(RENC_UVD_IB_OP_ENCODE);
955 RADEON_ENC_END();
956 }
957
radeon_uvd_enc_op_init_rc(struct radeon_uvd_encoder * enc)958 static void radeon_uvd_enc_op_init_rc(struct radeon_uvd_encoder *enc)
959 {
960 RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INIT_RC);
961 RADEON_ENC_END();
962 }
963
radeon_uvd_enc_op_init_rc_vbv(struct radeon_uvd_encoder * enc)964 static void radeon_uvd_enc_op_init_rc_vbv(struct radeon_uvd_encoder *enc)
965 {
966 RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
967 RADEON_ENC_END();
968 }
969
radeon_uvd_enc_op_speed(struct radeon_uvd_encoder * enc)970 static void radeon_uvd_enc_op_speed(struct radeon_uvd_encoder *enc)
971 {
972 RADEON_ENC_BEGIN(RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE);
973 RADEON_ENC_END();
974 }
975
begin(struct radeon_uvd_encoder * enc,struct pipe_picture_desc * pic)976 static void begin(struct radeon_uvd_encoder *enc, struct pipe_picture_desc *pic)
977 {
978 radeon_uvd_enc_session_info(enc);
979 enc->total_task_size = 0;
980 radeon_uvd_enc_task_info(enc, enc->need_feedback);
981 radeon_uvd_enc_op_init(enc);
982
983 radeon_uvd_enc_session_init_hevc(enc);
984 radeon_uvd_enc_slice_control_hevc(enc);
985 radeon_uvd_enc_spec_misc_hevc(enc, pic);
986 radeon_uvd_enc_deblocking_filter_hevc(enc, pic);
987
988 radeon_uvd_enc_layer_control(enc);
989 radeon_uvd_enc_rc_session_init(enc, pic);
990 radeon_uvd_enc_quality_params(enc);
991 radeon_uvd_enc_layer_select(enc);
992 radeon_uvd_enc_rc_layer_init(enc, pic);
993 radeon_uvd_enc_layer_select(enc);
994 radeon_uvd_enc_rc_per_pic(enc, pic);
995 radeon_uvd_enc_op_init_rc(enc);
996 radeon_uvd_enc_op_init_rc_vbv(enc);
997 *enc->p_task_size = (enc->total_task_size);
998 }
999
encode(struct radeon_uvd_encoder * enc)1000 static void encode(struct radeon_uvd_encoder *enc)
1001 {
1002 radeon_uvd_enc_session_info(enc);
1003 enc->total_task_size = 0;
1004 radeon_uvd_enc_task_info(enc, enc->need_feedback);
1005
1006 radeon_uvd_enc_nalu_aud_hevc(enc);
1007
1008 if (enc->enc_pic.is_iframe) {
1009 radeon_uvd_enc_nalu_vps_hevc(enc);
1010 radeon_uvd_enc_nalu_pps_hevc(enc);
1011 radeon_uvd_enc_nalu_sps_hevc(enc);
1012 }
1013 radeon_uvd_enc_slice_header_hevc(enc);
1014 radeon_uvd_enc_encode_params_hevc(enc);
1015
1016 radeon_uvd_enc_ctx(enc);
1017 radeon_uvd_enc_bitstream(enc);
1018 radeon_uvd_enc_feedback(enc);
1019 radeon_uvd_enc_intra_refresh(enc);
1020
1021 radeon_uvd_enc_op_speed(enc);
1022 radeon_uvd_enc_op_enc(enc);
1023 *enc->p_task_size = (enc->total_task_size);
1024 }
1025
destroy(struct radeon_uvd_encoder * enc)1026 static void destroy(struct radeon_uvd_encoder *enc)
1027 {
1028 radeon_uvd_enc_session_info(enc);
1029 enc->total_task_size = 0;
1030 radeon_uvd_enc_task_info(enc, enc->need_feedback);
1031 radeon_uvd_enc_op_close(enc);
1032 *enc->p_task_size = (enc->total_task_size);
1033 }
1034
radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder * enc)1035 void radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc)
1036 {
1037 enc->begin = begin;
1038 enc->encode = encode;
1039 enc->destroy = destroy;
1040 }
1041