1 /************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 **************************************************************************/ 8 9 #ifndef _RADEON_VCN_DEC_H 10 #define _RADEON_VCN_DEC_H 11 12 #include "radeon_vcn.h" 13 #include "util/list.h" 14 15 #include "ac_vcn_dec.h" 16 17 #define NUM_BUFFERS 4 18 19 struct rvcn_dec_dynamic_dpb_t2 { 20 struct list_head list; 21 uint8_t index; 22 struct rvid_buffer dpb; 23 }; 24 25 struct jpeg_registers { 26 #define RDECODE_JPEG_REG_VER_V1 0 27 #define RDECODE_JPEG_REG_VER_V2 1 28 #define RDECODE_JPEG_REG_VER_V3 2 29 unsigned version; 30 unsigned jpeg_dec_soft_rst; 31 unsigned jrbc_ib_cond_rd_timer; 32 unsigned jrbc_ib_ref_data; 33 unsigned lmi_jpeg_read_64bit_bar_high; 34 unsigned lmi_jpeg_read_64bit_bar_low; 35 unsigned jpeg_rb_base; 36 unsigned jpeg_rb_size; 37 unsigned jpeg_rb_wptr; 38 unsigned jpeg_pitch; 39 unsigned jpeg_uv_pitch; 40 unsigned dec_addr_mode; 41 unsigned dec_y_gfx10_tiling_surface; 42 unsigned dec_uv_gfx10_tiling_surface; 43 unsigned lmi_jpeg_write_64bit_bar_high; 44 unsigned lmi_jpeg_write_64bit_bar_low; 45 unsigned jpeg_tier_cntl2; 46 unsigned jpeg_outbuf_rptr; 47 unsigned jpeg_outbuf_cntl; 48 unsigned jpeg_int_en; 49 unsigned jpeg_cntl; 50 unsigned jpeg_rb_rptr; 51 unsigned jpeg_outbuf_wptr; 52 unsigned jpeg_luma_base0_0; 53 unsigned jpeg_chroma_base0_0; 54 unsigned jpeg_chromav_base0_0; 55 unsigned jpeg_index; 56 unsigned jpeg_data; 57 }; 58 59 struct radeon_decoder { 60 struct pipe_video_codec base; 61 62 unsigned stream_handle; 63 unsigned stream_type; 64 unsigned frame_number; 65 unsigned db_alignment; 66 unsigned dpb_size; 67 unsigned last_width; 68 unsigned last_height; 69 unsigned max_width; 70 unsigned max_height; 71 unsigned addr_gfx_mode; 72 73 struct pipe_screen *screen; 74 struct radeon_winsys *ws; 75 struct radeon_cmdbuf cs; 76 77 void *msg; 78 uint32_t *fb; 79 uint8_t *it; 80 uint8_t *probs; 81 void *bs_ptr; 82 rvcn_decode_buffer_t *decode_buffer; 83 bool vcn_dec_sw_ring; 84 struct rvcn_sq_var sq; 85 86 struct rvid_buffer *msg_fb_it_probs_buffers; 87 unsigned num_dec_bufs; 88 struct rvid_buffer *bs_buffers; 89 struct rvid_buffer dpb; 90 struct rvid_buffer ctx; 91 struct rvid_buffer sessionctx; 92 93 unsigned bs_size; 94 unsigned cur_buffer; 95 void *render_pic_list[32]; 96 unsigned h264_valid_ref_num[17]; 97 unsigned h264_valid_poc_num[34]; 98 unsigned av1_version; 99 bool show_frame; 100 unsigned ref_idx; 101 bool tmz_ctx; 102 struct { 103 unsigned data0; 104 unsigned data1; 105 unsigned cmd; 106 unsigned cntl; 107 } reg; 108 struct jpeg_params jpg; 109 struct jpeg_registers jpg_reg; 110 enum { 111 DPB_MAX_RES = 0, 112 DPB_DYNAMIC_TIER_1, 113 DPB_DYNAMIC_TIER_2 114 } dpb_type; 115 116 struct { 117 enum { 118 CODEC_8_BITS = 0, 119 CODEC_10_BITS 120 } bts; 121 uint8_t index; 122 unsigned ref_size; 123 uint8_t ref_list[16]; 124 } ref_codec; 125 126 struct list_head dpb_ref_list; 127 struct list_head dpb_unref_list; 128 129 void (*send_cmd)(struct radeon_decoder *dec, struct pipe_video_buffer *target, 130 struct pipe_picture_desc *picture); 131 /* Additional contexts for mJPEG */ 132 struct radeon_cmdbuf *jcs; 133 struct radeon_winsys_ctx **jctx; 134 unsigned cb_idx; 135 unsigned njctx; 136 struct pipe_fence_handle *prev_fence; 137 struct pipe_fence_handle *destroy_fence; 138 }; 139 140 void send_cmd_dec(struct radeon_decoder *dec, struct pipe_video_buffer *target, 141 struct pipe_picture_desc *picture); 142 143 void send_cmd_jpeg(struct radeon_decoder *dec, struct pipe_video_buffer *target, 144 struct pipe_picture_desc *picture); 145 146 struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context, 147 const struct pipe_video_codec *templat); 148 149 #endif 150