1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "pipe/p_video_codec.h"
10 #include "radeon_vcn_enc.h"
11 #include "radeon_video.h"
12 #include "radeon_temporal.h"
13 #include "si_pipe.h"
14 #include "util/u_video.h"
15
16 #include <stdio.h>
17
18 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
19 #define RENCODE_FW_INTERFACE_MINOR_VERSION 9
20
21 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
22 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002
23 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
24 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
25 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
26 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
27 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
28 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
29 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
30 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000a
31 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000b
32 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x0000000c
33 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0000000d
34 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x0000000e
35 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000010
36 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x00000020
37 #define RENCODE_IB_PARAM_QP_MAP 0x00000021
38 #define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x00000024
39
40 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
41 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
42 #define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER 0x00100003
43
44 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
45 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
46 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
47 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
48
radeon_enc_session_info(struct radeon_encoder * enc)49 static void radeon_enc_session_info(struct radeon_encoder *enc)
50 {
51 RADEON_ENC_BEGIN(enc->cmd.session_info);
52 RADEON_ENC_CS(enc->enc_pic.session_info.interface_version);
53 RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
54 RADEON_ENC_CS(RENCODE_ENGINE_TYPE_ENCODE);
55 RADEON_ENC_END();
56 }
57
radeon_enc_task_info(struct radeon_encoder * enc,bool need_feedback)58 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
59 {
60 enc->enc_pic.task_info.task_id++;
61
62 if (need_feedback)
63 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
64 else
65 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
66
67 RADEON_ENC_BEGIN(enc->cmd.task_info);
68 enc->p_task_size = &enc->cs.current.buf[enc->cs.current.cdw++];
69 RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
70 RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
71 RADEON_ENC_END();
72 }
73
radeon_enc_session_init(struct radeon_encoder * enc)74 static void radeon_enc_session_init(struct radeon_encoder *enc)
75 {
76 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
77 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
78 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
79 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
80 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
81 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
82 }
83 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
84 enc->enc_pic.session_init.padding_width =
85 enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
86 enc->enc_pic.session_init.padding_height =
87 enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
88 enc->enc_pic.session_init.display_remote = 0;
89 enc->enc_pic.session_init.pre_encode_mode = enc->enc_pic.quality_modes.pre_encode_mode;
90 enc->enc_pic.session_init.pre_encode_chroma_enabled = !!(enc->enc_pic.quality_modes.pre_encode_mode);
91
92 RADEON_ENC_BEGIN(enc->cmd.session_init);
93 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
94 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
95 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
96 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
97 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
98 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
99 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
100 RADEON_ENC_CS(enc->enc_pic.session_init.display_remote);
101 RADEON_ENC_END();
102 }
103
radeon_enc_layer_control(struct radeon_encoder * enc)104 static void radeon_enc_layer_control(struct radeon_encoder *enc)
105 {
106 enc->enc_pic.layer_ctrl.max_num_temporal_layers = enc->enc_pic.num_temporal_layers;
107 enc->enc_pic.layer_ctrl.num_temporal_layers = enc->enc_pic.num_temporal_layers;
108
109 RADEON_ENC_BEGIN(enc->cmd.layer_control);
110 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
111 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
112 RADEON_ENC_END();
113 }
114
radeon_enc_layer_select(struct radeon_encoder * enc)115 static void radeon_enc_layer_select(struct radeon_encoder *enc)
116 {
117 enc->enc_pic.layer_sel.temporal_layer_index = enc->enc_pic.temporal_id;
118
119 RADEON_ENC_BEGIN(enc->cmd.layer_select);
120 RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
121 RADEON_ENC_END();
122 }
123
radeon_enc_slice_control(struct radeon_encoder * enc)124 static void radeon_enc_slice_control(struct radeon_encoder *enc)
125 {
126 enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
127
128 RADEON_ENC_BEGIN(enc->cmd.slice_control_h264);
129 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
130 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
131 RADEON_ENC_END();
132 }
133
radeon_enc_slice_control_hevc(struct radeon_encoder * enc)134 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
135 {
136 enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
137
138 RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc);
139 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
140 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
141 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
142 RADEON_ENC_END();
143 }
144
radeon_enc_spec_misc(struct radeon_encoder * enc)145 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
146 {
147 enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
148 enc->enc_pic.spec_misc.half_pel_enabled = 1;
149 enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
150 enc->enc_pic.spec_misc.level_idc = enc->base.level;
151
152 RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
153 RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
154 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
155 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
156 RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
157 RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
158 RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
159 RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
160 RADEON_ENC_END();
161 }
162
radeon_enc_spec_misc_hevc(struct radeon_encoder * enc)163 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc)
164 {
165 RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc);
166 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
167 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
168 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
169 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
170 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
171 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
172 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
173 RADEON_ENC_END();
174 }
175
radeon_enc_rc_session_init(struct radeon_encoder * enc)176 static void radeon_enc_rc_session_init(struct radeon_encoder *enc)
177 {
178 RADEON_ENC_BEGIN(enc->cmd.rc_session_init);
179 RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
180 RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
181 RADEON_ENC_END();
182 }
183
radeon_enc_rc_layer_init(struct radeon_encoder * enc)184 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc)
185 {
186 unsigned int i = enc->enc_pic.temporal_id;
187 RADEON_ENC_BEGIN(enc->cmd.rc_layer_init);
188 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].target_bit_rate);
189 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bit_rate);
190 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_num);
191 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_den);
192 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].vbv_buffer_size);
193 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].avg_target_bits_per_picture);
194 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_integer);
195 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_fractional);
196 RADEON_ENC_END();
197 }
198
radeon_enc_deblocking_filter_h264(struct radeon_encoder * enc)199 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
200 {
201 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_h264);
202 RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
203 RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
204 RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
205 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
206 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
207 RADEON_ENC_END();
208 }
209
radeon_enc_deblocking_filter_hevc(struct radeon_encoder * enc)210 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc)
211 {
212 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
213 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
214 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
215 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
216 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
217 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
218 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
219 RADEON_ENC_END();
220 }
221
radeon_enc_quality_params(struct radeon_encoder * enc)222 static void radeon_enc_quality_params(struct radeon_encoder *enc)
223 {
224 enc->enc_pic.quality_params.vbaq_mode = enc->enc_pic.quality_modes.vbaq_mode;
225 enc->enc_pic.quality_params.scene_change_sensitivity = 0;
226 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
227 enc->enc_pic.quality_params.two_pass_search_center_map_mode =
228 (enc->enc_pic.quality_modes.pre_encode_mode) ? 1 : 0;
229
230 RADEON_ENC_BEGIN(enc->cmd.quality_params);
231 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
232 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
233 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
234 RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
235 RADEON_ENC_END();
236 }
237
radeon_enc_nalu_sps(struct radeon_encoder * enc)238 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
239 {
240 struct radeon_enc_pic *pic = &enc->enc_pic;
241 RADEON_ENC_BEGIN(enc->cmd.nalu);
242 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
243 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
244 radeon_enc_reset(enc);
245 radeon_enc_set_emulation_prevention(enc, false);
246 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
247 radeon_enc_code_fixed_bits(enc, 0x67, 8);
248 radeon_enc_byte_align(enc);
249 radeon_enc_set_emulation_prevention(enc, true);
250 radeon_enc_code_fixed_bits(enc, pic->spec_misc.profile_idc, 8);
251 radeon_enc_code_fixed_bits(enc, 0x44, 8); // hardcode to constrained baseline
252 radeon_enc_code_fixed_bits(enc, pic->spec_misc.level_idc, 8);
253 radeon_enc_code_ue(enc, 0x0);
254
255 if (pic->spec_misc.profile_idc == 100 || pic->spec_misc.profile_idc == 110 ||
256 pic->spec_misc.profile_idc == 122 || pic->spec_misc.profile_idc == 244 ||
257 pic->spec_misc.profile_idc == 44 || pic->spec_misc.profile_idc == 83 ||
258 pic->spec_misc.profile_idc == 86 || pic->spec_misc.profile_idc == 118 ||
259 pic->spec_misc.profile_idc == 128 || pic->spec_misc.profile_idc == 138) {
260 radeon_enc_code_ue(enc, 0x1);
261 radeon_enc_code_ue(enc, 0x0);
262 radeon_enc_code_ue(enc, 0x0);
263 radeon_enc_code_fixed_bits(enc, 0x0, 2);
264 }
265
266 radeon_enc_code_ue(enc, 1);
267 radeon_enc_code_ue(enc, pic->pic_order_cnt_type);
268
269 if (pic->pic_order_cnt_type == 0)
270 radeon_enc_code_ue(enc, 1);
271
272 radeon_enc_code_ue(enc, enc->base.max_references);
273 radeon_enc_code_fixed_bits(enc, pic->layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0,
274 1);
275 radeon_enc_code_ue(enc, (pic->session_init.aligned_picture_width / 16 - 1));
276 radeon_enc_code_ue(enc, (pic->session_init.aligned_picture_height / 16 - 1));
277 bool progressive_only = true;
278 radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
279
280 if (!progressive_only)
281 radeon_enc_code_fixed_bits(enc, 0x0, 1);
282
283 radeon_enc_code_fixed_bits(enc, 0x1, 1);
284
285 if ((pic->crop_left != 0) || (pic->crop_right != 0) ||
286 (pic->crop_top != 0) || (pic->crop_bottom != 0)) {
287 radeon_enc_code_fixed_bits(enc, 0x1, 1);
288 radeon_enc_code_ue(enc, pic->crop_left);
289 radeon_enc_code_ue(enc, pic->crop_right);
290 radeon_enc_code_ue(enc, pic->crop_top);
291 radeon_enc_code_ue(enc, pic->crop_bottom);
292 } else
293 radeon_enc_code_fixed_bits(enc, 0x0, 1);
294
295 /* VUI present flag */
296 radeon_enc_code_fixed_bits(enc, pic->vui_info.vui_parameters_present_flag, 1);
297 if (pic->vui_info.vui_parameters_present_flag) {
298 /* aspect ratio present flag */
299 radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.aspect_ratio_info_present_flag), 1);
300 if (pic->vui_info.flags.aspect_ratio_info_present_flag) {
301 radeon_enc_code_fixed_bits(enc, (pic->vui_info.aspect_ratio_idc), 8);
302 if (pic->vui_info.aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
303 radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_width), 16);
304 radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_height), 16);
305 }
306 }
307 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* overscan info present flag */
308 /* video signal type present flag */
309 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.video_signal_type_present_flag, 1);
310 if (pic->vui_info.flags.video_signal_type_present_flag) {
311 radeon_enc_code_fixed_bits(enc, pic->vui_info.video_format, 3);
312 radeon_enc_code_fixed_bits(enc, pic->vui_info.video_full_range_flag, 1);
313 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.colour_description_present_flag, 1);
314 if (pic->vui_info.flags.colour_description_present_flag) {
315 radeon_enc_code_fixed_bits(enc, pic->vui_info.colour_primaries, 8);
316 radeon_enc_code_fixed_bits(enc, pic->vui_info.transfer_characteristics, 8);
317 radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
318 }
319 }
320 /* chroma loc info present flag */
321 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
322 if (pic->vui_info.flags.chroma_loc_info_present_flag) {
323 radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
324 radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
325 }
326 /* timing info present flag */
327 radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.timing_info_present_flag), 1);
328 if (pic->vui_info.flags.timing_info_present_flag) {
329 radeon_enc_code_fixed_bits(enc, (pic->vui_info.num_units_in_tick), 32);
330 radeon_enc_code_fixed_bits(enc, (pic->vui_info.time_scale), 32);
331 radeon_enc_code_fixed_bits(enc, 0x0, 1);
332 }
333 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* nal hrd parameters present flag */
334 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* vcl hrd parameters present flag */
335 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pic_struct_present flag */
336 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* bitstream_restriction_flag */
337 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* motion_vectors_over_pic_boundaries_flag */
338 radeon_enc_code_ue(enc, 0x0);
339 radeon_enc_code_ue(enc, 0x0);
340 radeon_enc_code_ue(enc, 16);
341 radeon_enc_code_ue(enc, 16);
342 radeon_enc_code_ue(enc, 0x0);
343 radeon_enc_code_ue(enc, enc->base.max_references); /* max_dec_frame_buffering */
344 }
345 radeon_enc_code_fixed_bits(enc, 0x1, 1);
346
347 radeon_enc_byte_align(enc);
348 radeon_enc_flush_headers(enc);
349 *size_in_bytes = (enc->bits_output + 7) / 8;
350 RADEON_ENC_END();
351 }
352
radeon_enc_nalu_sps_hevc(struct radeon_encoder * enc)353 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
354 {
355 struct radeon_enc_pic *pic = &enc->enc_pic;
356 RADEON_ENC_BEGIN(enc->cmd.nalu);
357 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
358 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
359 int i;
360
361 radeon_enc_reset(enc);
362 radeon_enc_set_emulation_prevention(enc, false);
363 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
364 radeon_enc_code_fixed_bits(enc, 0x4201, 16);
365 radeon_enc_byte_align(enc);
366 radeon_enc_set_emulation_prevention(enc, true);
367 radeon_enc_code_fixed_bits(enc, 0x0, 4);
368 radeon_enc_code_fixed_bits(enc, pic->layer_ctrl.max_num_temporal_layers - 1, 3);
369 radeon_enc_code_fixed_bits(enc, 0x1, 1);
370 radeon_enc_code_fixed_bits(enc, 0x0, 2);
371 radeon_enc_code_fixed_bits(enc, pic->general_tier_flag, 1);
372 radeon_enc_code_fixed_bits(enc, pic->general_profile_idc, 5);
373 radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
374 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
375 radeon_enc_code_fixed_bits(enc, 0x0, 16);
376 radeon_enc_code_fixed_bits(enc, pic->general_level_idc, 8);
377
378 for (i = 0; i < (pic->layer_ctrl.max_num_temporal_layers - 1); i++)
379 radeon_enc_code_fixed_bits(enc, 0x0, 2);
380
381 if ((pic->layer_ctrl.max_num_temporal_layers - 1) > 0) {
382 for (i = (pic->layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
383 radeon_enc_code_fixed_bits(enc, 0x0, 2);
384 }
385
386 radeon_enc_code_ue(enc, 0x0);
387 radeon_enc_code_ue(enc, pic->chroma_format_idc);
388 radeon_enc_code_ue(enc, pic->session_init.aligned_picture_width);
389 radeon_enc_code_ue(enc, pic->session_init.aligned_picture_height);
390
391 if ((pic->crop_left != 0) || (pic->crop_right != 0) ||
392 (pic->crop_top != 0) || (pic->crop_bottom != 0)) {
393 radeon_enc_code_fixed_bits(enc, 0x1, 1);
394 radeon_enc_code_ue(enc, pic->crop_left);
395 radeon_enc_code_ue(enc, pic->crop_right);
396 radeon_enc_code_ue(enc, pic->crop_top);
397 radeon_enc_code_ue(enc, pic->crop_bottom);
398 } else if (pic->session_init.padding_width != 0 ||
399 pic->session_init.padding_height != 0) {
400 radeon_enc_code_fixed_bits(enc, 0x1, 1);
401 radeon_enc_code_ue(enc, 0);
402 radeon_enc_code_ue(enc, pic->session_init.padding_width / 2);
403 radeon_enc_code_ue(enc, 0);
404 radeon_enc_code_ue(enc, pic->session_init.padding_height / 2);
405 } else
406 radeon_enc_code_fixed_bits(enc, 0x0, 1);
407
408 radeon_enc_code_ue(enc, pic->bit_depth_luma_minus8);
409 radeon_enc_code_ue(enc, pic->bit_depth_chroma_minus8);
410 radeon_enc_code_ue(enc, pic->log2_max_poc - 4);
411 radeon_enc_code_fixed_bits(enc, 0x0, 1);
412 radeon_enc_code_ue(enc, 1);
413 radeon_enc_code_ue(enc, 0x0);
414 radeon_enc_code_ue(enc, 0x0);
415 radeon_enc_code_ue(enc, pic->hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
416 // Only support CTBSize 64
417 radeon_enc_code_ue(enc,
418 6 - (pic->hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
419 radeon_enc_code_ue(enc, pic->log2_min_transform_block_size_minus2);
420 radeon_enc_code_ue(enc, pic->log2_diff_max_min_transform_block_size);
421 radeon_enc_code_ue(enc, pic->max_transform_hierarchy_depth_inter);
422 radeon_enc_code_ue(enc, pic->max_transform_hierarchy_depth_intra);
423
424 radeon_enc_code_fixed_bits(enc, 0x0, 1);
425 radeon_enc_code_fixed_bits(enc, !pic->hevc_spec_misc.amp_disabled, 1);
426 radeon_enc_code_fixed_bits(enc, pic->sample_adaptive_offset_enabled_flag, 1);
427 radeon_enc_code_fixed_bits(enc, pic->pcm_enabled_flag, 1);
428
429 radeon_enc_code_ue(enc, 1);
430 radeon_enc_code_ue(enc, 1);
431 radeon_enc_code_ue(enc, 0);
432 radeon_enc_code_ue(enc, 0);
433 radeon_enc_code_fixed_bits(enc, 0x1, 1);
434
435 radeon_enc_code_fixed_bits(enc, 0x0, 1);
436
437 radeon_enc_code_fixed_bits(enc, 0, 1);
438 radeon_enc_code_fixed_bits(enc, pic->hevc_spec_misc.strong_intra_smoothing_enabled, 1);
439
440 /* VUI parameter present flag */
441 radeon_enc_code_fixed_bits(enc, (pic->vui_info.vui_parameters_present_flag), 1);
442 if (pic->vui_info.vui_parameters_present_flag) {
443 /* aspect ratio present flag */
444 radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.aspect_ratio_info_present_flag), 1);
445 if (pic->vui_info.flags.aspect_ratio_info_present_flag) {
446 radeon_enc_code_fixed_bits(enc, (pic->vui_info.aspect_ratio_idc), 8);
447 if (pic->vui_info.aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
448 radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_width), 16);
449 radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_height), 16);
450 }
451 }
452 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* overscan info present flag */
453 /* video signal type present flag */
454 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.video_signal_type_present_flag, 1);
455 if (pic->vui_info.flags.video_signal_type_present_flag) {
456 radeon_enc_code_fixed_bits(enc, pic->vui_info.video_format, 3);
457 radeon_enc_code_fixed_bits(enc, pic->vui_info.video_full_range_flag, 1);
458 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.colour_description_present_flag, 1);
459 if (pic->vui_info.flags.colour_description_present_flag) {
460 radeon_enc_code_fixed_bits(enc, pic->vui_info.colour_primaries, 8);
461 radeon_enc_code_fixed_bits(enc, pic->vui_info.transfer_characteristics, 8);
462 radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
463 }
464 }
465 /* chroma loc info present flag */
466 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
467 if (pic->vui_info.flags.chroma_loc_info_present_flag) {
468 radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
469 radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
470 }
471 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* neutral chroma indication flag */
472 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* field seq flag */
473 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* frame field info present flag */
474 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* default display windows flag */
475 /* vui timing info present flag */
476 radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.timing_info_present_flag), 1);
477 if (pic->vui_info.flags.timing_info_present_flag) {
478 radeon_enc_code_fixed_bits(enc, (pic->vui_info.num_units_in_tick), 32);
479 radeon_enc_code_fixed_bits(enc, (pic->vui_info.time_scale), 32);
480 radeon_enc_code_fixed_bits(enc, 0x0, 1);
481 radeon_enc_code_fixed_bits(enc, 0x0, 1);
482 }
483 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* bitstream restriction flag */
484 }
485
486 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* SPS extension present */
487 radeon_enc_code_fixed_bits(enc, 0x1, 1);
488
489 radeon_enc_byte_align(enc);
490 radeon_enc_flush_headers(enc);
491 *size_in_bytes = (enc->bits_output + 7) / 8;
492 RADEON_ENC_END();
493 }
494
radeon_enc_nalu_prefix(struct radeon_encoder * enc)495 static void radeon_enc_nalu_prefix(struct radeon_encoder *enc)
496 {
497 uint nalRefIdc = enc->enc_pic.is_idr ? 3 : 0;
498
499 rvcn_temporal_layer_pattern_table_t table_info;
500 table_info = rvcn_temporal_layer_pattern_tables[enc->enc_pic.layer_ctrl.num_temporal_layers];
501
502 if (enc->enc_pic.pic_order_cnt == 0)
503 enc->enc_pic.temporal_layer_pattern_index = 0;
504 else if(enc->enc_pic.temporal_layer_pattern_index == (table_info.pattern_size - 1))
505 enc->enc_pic.temporal_layer_pattern_index = 1;
506 else
507 enc->enc_pic.temporal_layer_pattern_index++;
508
509 rvcn_temporal_layer_pattern_entry_t pattern =
510 table_info.pattern_table[enc->enc_pic.temporal_layer_pattern_index];
511
512 RADEON_ENC_BEGIN(enc->cmd.nalu);
513 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX);
514 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
515 radeon_enc_reset(enc);
516 radeon_enc_set_emulation_prevention(enc, false);
517 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
518 radeon_enc_code_fixed_bits(enc, 0x0, 1);
519 radeon_enc_code_fixed_bits(enc, nalRefIdc, 2);
520 radeon_enc_code_fixed_bits(enc, 14, 5);
521 radeon_enc_byte_align(enc);
522 radeon_enc_set_emulation_prevention(enc, true);
523 radeon_enc_code_fixed_bits(enc, 0x1, 1);
524 radeon_enc_code_fixed_bits(enc, enc->enc_pic.is_idr ? 0x1 : 0x0, 1);
525 radeon_enc_code_fixed_bits(enc, 0x0, 6);
526 radeon_enc_code_fixed_bits(enc, 0x1, 1);
527 radeon_enc_code_fixed_bits(enc, 0x0, 3);
528 radeon_enc_code_fixed_bits(enc, 0x0, 4);
529 radeon_enc_code_fixed_bits(enc, pattern.temporal_id, 3);
530 radeon_enc_code_fixed_bits(enc, 0x0, 1);
531 radeon_enc_code_fixed_bits(enc, 0x0, 1);
532 radeon_enc_code_fixed_bits(enc, 0x0, 1);
533 radeon_enc_code_fixed_bits(enc, 0x3, 2);
534
535 if(nalRefIdc != 0)
536 {
537 radeon_enc_code_fixed_bits(enc, 0x0, 1);
538 radeon_enc_code_fixed_bits(enc, 0x0, 1);
539 radeon_enc_code_fixed_bits(enc, 0x1, 1);
540 radeon_enc_byte_align(enc);
541 }
542
543 radeon_enc_flush_headers(enc);
544 *size_in_bytes = (enc->bits_output + 7) / 8;
545 RADEON_ENC_END();
546 }
547
radeon_enc_nalu_sei(struct radeon_encoder * enc)548 static void radeon_enc_nalu_sei(struct radeon_encoder *enc)
549 {
550 unsigned number_of_layers;
551
552 rvcn_temporal_layer_pattern_table_t table_info;
553 table_info = rvcn_temporal_layer_pattern_tables[enc->enc_pic.layer_ctrl.num_temporal_layers - 1];
554 number_of_layers = table_info.pattern_size;
555
556 RADEON_ENC_BEGIN(enc->cmd.nalu);
557 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SEI);
558 unsigned *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
559 radeon_enc_reset(enc);
560 radeon_enc_set_emulation_prevention(enc, false);
561
562 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
563 radeon_enc_code_fixed_bits(enc, 0x6, 8);
564 radeon_enc_byte_align(enc);
565
566 radeon_enc_set_emulation_prevention(enc, true);
567
568 /* save the current position for later */
569 unsigned position = enc->cs.current.cdw;
570 unsigned shifter = enc->shifter;
571 unsigned bits_in_shifter = enc->bits_in_shifter;
572 unsigned num_zeros = enc->num_zeros;
573 unsigned byte_index = enc->byte_index;
574 unsigned bits_output = enc->bits_output;
575 bool emulation_prevention = enc->emulation_prevention;
576
577 /* temporarily fill out the payload type and size */
578 radeon_enc_code_fixed_bits(enc, 24, 8);
579 radeon_enc_code_fixed_bits(enc, 0, 8);
580
581 unsigned svc_start_offset = enc->bits_size;
582
583 radeon_enc_code_fixed_bits(enc, 0x0, 1);
584 radeon_enc_code_fixed_bits(enc, 0x0, 1);
585 radeon_enc_code_fixed_bits(enc, 0x0, 1);
586 radeon_enc_code_ue(enc, number_of_layers - 1);
587
588 for(int i = 0; i < number_of_layers; i++ )
589 {
590 rvcn_temporal_layer_pattern_entry_t pattern = table_info.pattern_table[i];
591 radeon_enc_code_ue(enc, i);
592 radeon_enc_code_fixed_bits(enc, 0x0, 6);
593 radeon_enc_code_fixed_bits(enc, 0x0, 1);
594 radeon_enc_code_fixed_bits(enc, 0x0, 3);
595 radeon_enc_code_fixed_bits(enc, 0x0, 4);
596 radeon_enc_code_fixed_bits(enc, pattern.temporal_id, 3);
597 radeon_enc_code_fixed_bits(enc, 0x0, 1);
598 radeon_enc_code_fixed_bits(enc, 0x0, 1);
599 radeon_enc_code_fixed_bits(enc, 0x0, 1);
600 radeon_enc_code_fixed_bits(enc, 0x0, 1);
601 radeon_enc_code_fixed_bits(enc, 0x0, 1);
602 radeon_enc_code_fixed_bits(enc, 0x0, 1);
603 radeon_enc_code_fixed_bits(enc, 0x0, 1);
604 radeon_enc_code_fixed_bits(enc, 0x0, 1);
605 radeon_enc_code_fixed_bits(enc, 0x0, 1);
606 radeon_enc_code_fixed_bits(enc, 0x0, 1);
607 radeon_enc_code_fixed_bits(enc, 0x0, 1);
608 radeon_enc_code_fixed_bits(enc, 0x0, 1);
609 radeon_enc_code_fixed_bits(enc, 0x0, 1);
610 radeon_enc_code_ue(enc, 0);
611 radeon_enc_code_ue(enc, 0);
612 }
613 unsigned svc_size = ((enc->bits_size - svc_start_offset) + 7) / 8;
614 unsigned aligned = (32 - enc->bits_in_shifter) % 8;
615 if (aligned > 0)
616 radeon_enc_code_fixed_bits(enc, 0x1, 1);
617 radeon_enc_byte_align(enc);
618
619 radeon_enc_code_fixed_bits(enc, 0x1, 1);
620 radeon_enc_byte_align(enc);
621
622 /* store our current state, and go to the beginning to write the size */
623 unsigned position2 = enc->cs.current.cdw;
624 unsigned shifter2 = enc->shifter;
625 unsigned bits_in_shifter2 = enc->bits_in_shifter;
626 unsigned num_zeros2 = enc->num_zeros;
627 unsigned byte_index2 = enc->byte_index;
628 unsigned bits_output2 = enc->bits_output;
629 bool emulation_prevention2 = enc->emulation_prevention;
630
631 enc->cs.current.cdw = position;
632 enc->shifter = shifter;
633 enc->bits_in_shifter = bits_in_shifter;
634 enc->num_zeros = num_zeros;
635 enc->byte_index = byte_index;
636 enc->bits_output = bits_output;
637 enc->emulation_prevention = emulation_prevention;
638
639 radeon_enc_output_one_byte(enc, 24);
640 radeon_enc_output_one_byte(enc, svc_size);
641
642 /* restore our state */
643 enc->cs.current.cdw = position2;
644 enc->shifter = shifter2;
645 enc->bits_in_shifter = bits_in_shifter2;
646 enc->num_zeros = num_zeros2;
647 enc->byte_index = byte_index2;
648 enc->bits_output = bits_output2;
649 enc->emulation_prevention = emulation_prevention2;
650
651 radeon_enc_flush_headers(enc);
652
653 *size_in_bytes = (enc->bits_output + 7) / 8;
654 RADEON_ENC_END();
655 }
656
radeon_enc_nalu_pps(struct radeon_encoder * enc)657 static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
658 {
659 RADEON_ENC_BEGIN(enc->cmd.nalu);
660 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
661 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
662 radeon_enc_reset(enc);
663 radeon_enc_set_emulation_prevention(enc, false);
664 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
665 radeon_enc_code_fixed_bits(enc, 0x68, 8);
666 radeon_enc_byte_align(enc);
667 radeon_enc_set_emulation_prevention(enc, true);
668 radeon_enc_code_ue(enc, 0x0);
669 radeon_enc_code_ue(enc, 0x0);
670 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
671 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* bottom_field_pic_order_in_frame_present_flag */
672 radeon_enc_code_ue(enc, 0x0); /* num_slice_groups_minus_1 */
673 radeon_enc_code_ue(enc, 0x0); /* num_ref_idx_l0_default_active_minus1 */
674 radeon_enc_code_ue(enc, 0x0); /* num_ref_idx_l1_default_active_minus1 */
675 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* weighted_pred_flag */
676 radeon_enc_code_fixed_bits(enc, 0x0, 2); /* weighted_bipred_idc */
677 radeon_enc_code_se(enc, 0x0); /* pic_init_qp_minus26 */
678 radeon_enc_code_se(enc, 0x0); /* pic_init_qs_minus26 */
679 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.cb_qp_offset); /* chroma_qp_index_offset */
680 /* deblocking_filter_control_present_flag */
681 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag), 1);
682 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* constrained_intra_pred_flag */
683 /* redundant_pic_cnt_present_flag */
684 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag), 1);
685 if (enc->enc_pic.spec_misc.redundant_pic_cnt_present_flag) {
686 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* transform_8x8_mode_flag */
687 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pic_scaling_matrix_present_flag */
688 /* second_chroma_qp_index_offset */
689 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.cr_qp_offset);
690 }
691
692 radeon_enc_code_fixed_bits(enc, 0x1, 1);
693
694 radeon_enc_byte_align(enc);
695 radeon_enc_flush_headers(enc);
696 *size_in_bytes = (enc->bits_output + 7) / 8;
697 RADEON_ENC_END();
698 }
699
radeon_enc_nalu_pps_hevc(struct radeon_encoder * enc)700 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
701 {
702 RADEON_ENC_BEGIN(enc->cmd.nalu);
703 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
704 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
705 radeon_enc_reset(enc);
706 radeon_enc_set_emulation_prevention(enc, false);
707 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
708 radeon_enc_code_fixed_bits(enc, 0x4401, 16);
709 radeon_enc_byte_align(enc);
710 radeon_enc_set_emulation_prevention(enc, true);
711 radeon_enc_code_ue(enc, 0x0);
712 radeon_enc_code_ue(enc, 0x0);
713 radeon_enc_code_fixed_bits(enc, 0x1, 1);
714 radeon_enc_code_fixed_bits(enc, 0x0, 4);
715 radeon_enc_code_fixed_bits(enc, 0x0, 1);
716 radeon_enc_code_fixed_bits(enc, 0x1, 1);
717 radeon_enc_code_ue(enc, 0x0);
718 radeon_enc_code_ue(enc, 0x0);
719 radeon_enc_code_se(enc, 0x0);
720 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
721 radeon_enc_code_fixed_bits(enc, 0x0, 1);
722 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE &&
723 enc->enc_pic.enc_qp_map.qp_map_type == RENCODE_QP_MAP_TYPE_NONE)
724 radeon_enc_code_fixed_bits(enc, 0x0, 1);
725 else {
726 radeon_enc_code_fixed_bits(enc, 0x1, 1);
727 radeon_enc_code_ue(enc, 0x0);
728 }
729 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
730 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
731 radeon_enc_code_fixed_bits(enc, 0x0, 1);
732 radeon_enc_code_fixed_bits(enc, 0x0, 2);
733 radeon_enc_code_fixed_bits(enc, 0x0, 1);
734 radeon_enc_code_fixed_bits(enc, 0x0, 1);
735 radeon_enc_code_fixed_bits(enc, 0x0, 1);
736 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
737 radeon_enc_code_fixed_bits(enc, 0x1, 1);
738 radeon_enc_code_fixed_bits(enc, 0x0, 1);
739 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
740
741 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
742 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
743 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
744 }
745
746 radeon_enc_code_fixed_bits(enc, 0x0, 1);
747 radeon_enc_code_fixed_bits(enc, 0x0, 1);
748 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
749 radeon_enc_code_fixed_bits(enc, 0x0, 2);
750
751 radeon_enc_code_fixed_bits(enc, 0x1, 1);
752
753 radeon_enc_byte_align(enc);
754 radeon_enc_flush_headers(enc);
755 *size_in_bytes = (enc->bits_output + 7) / 8;
756 RADEON_ENC_END();
757 }
758
radeon_enc_nalu_vps(struct radeon_encoder * enc)759 static void radeon_enc_nalu_vps(struct radeon_encoder *enc)
760 {
761 RADEON_ENC_BEGIN(enc->cmd.nalu);
762 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS);
763 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
764 int i;
765
766 radeon_enc_reset(enc);
767 radeon_enc_set_emulation_prevention(enc, false);
768 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
769 radeon_enc_code_fixed_bits(enc, 0x4001, 16);
770 radeon_enc_byte_align(enc);
771 radeon_enc_set_emulation_prevention(enc, true);
772
773 radeon_enc_code_fixed_bits(enc, 0x0, 4);
774 radeon_enc_code_fixed_bits(enc, 0x3, 2);
775 radeon_enc_code_fixed_bits(enc, 0x0, 6);
776 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
777 radeon_enc_code_fixed_bits(enc, 0x1, 1);
778 radeon_enc_code_fixed_bits(enc, 0xffff, 16);
779 radeon_enc_code_fixed_bits(enc, 0x0, 2);
780 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
781 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
782 radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
783 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
784 radeon_enc_code_fixed_bits(enc, 0x0, 16);
785 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
786
787 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
788 radeon_enc_code_fixed_bits(enc, 0x0, 2);
789
790 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
791 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
792 radeon_enc_code_fixed_bits(enc, 0x0, 2);
793 }
794
795 radeon_enc_code_fixed_bits(enc, 0x0, 1);
796 radeon_enc_code_ue(enc, 0x1);
797 radeon_enc_code_ue(enc, 0x0);
798 radeon_enc_code_ue(enc, 0x0);
799
800 radeon_enc_code_fixed_bits(enc, 0x0, 6);
801 radeon_enc_code_ue(enc, 0x0);
802 radeon_enc_code_fixed_bits(enc, 0x0, 1);
803 radeon_enc_code_fixed_bits(enc, 0x0, 1);
804
805 radeon_enc_code_fixed_bits(enc, 0x1, 1);
806
807 radeon_enc_byte_align(enc);
808 radeon_enc_flush_headers(enc);
809 *size_in_bytes = (enc->bits_output + 7) / 8;
810 RADEON_ENC_END();
811 }
812
radeon_enc_nalu_aud(struct radeon_encoder * enc)813 static void radeon_enc_nalu_aud(struct radeon_encoder *enc)
814 {
815 RADEON_ENC_BEGIN(enc->cmd.nalu);
816 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD);
817 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
818 radeon_enc_reset(enc);
819 radeon_enc_set_emulation_prevention(enc, false);
820 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
821
822 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC)
823 radeon_enc_code_fixed_bits(enc, 0x9, 8);
824 else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
825 radeon_enc_code_fixed_bits(enc, 0x0, 1);
826 radeon_enc_code_fixed_bits(enc, 35, 6);
827 radeon_enc_code_fixed_bits(enc, 0x0, 6);
828 radeon_enc_code_fixed_bits(enc, 0x1, 3);
829 }
830 radeon_enc_byte_align(enc);
831 radeon_enc_set_emulation_prevention(enc, true);
832 switch (enc->enc_pic.picture_type) {
833 case PIPE_H2645_ENC_PICTURE_TYPE_I:
834 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
835 radeon_enc_code_fixed_bits(enc, 0x00, 3);
836 break;
837 case PIPE_H2645_ENC_PICTURE_TYPE_P:
838 radeon_enc_code_fixed_bits(enc, 0x01, 3);
839 break;
840 case PIPE_H2645_ENC_PICTURE_TYPE_B:
841 radeon_enc_code_fixed_bits(enc, 0x02, 3);
842 break;
843 default:
844 radeon_enc_code_fixed_bits(enc, 0x02, 3);
845 }
846
847 radeon_enc_code_fixed_bits(enc, 0x1, 1);
848
849 radeon_enc_byte_align(enc);
850 radeon_enc_flush_headers(enc);
851 *size_in_bytes = (enc->bits_output + 7) / 8;
852 RADEON_ENC_END();
853 }
854
radeon_enc_slice_header(struct radeon_encoder * enc)855 static void radeon_enc_slice_header(struct radeon_encoder *enc)
856 {
857 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
858 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
859 unsigned int inst_index = 0;
860 unsigned int cdw_start = 0;
861 unsigned int cdw_filled = 0;
862 unsigned int bits_copied = 0;
863 RADEON_ENC_BEGIN(enc->cmd.slice_header);
864 radeon_enc_reset(enc);
865 radeon_enc_set_emulation_prevention(enc, false);
866
867 cdw_start = enc->cs.current.cdw;
868 if (enc->enc_pic.is_idr)
869 radeon_enc_code_fixed_bits(enc, 0x65, 8);
870 else if (enc->enc_pic.not_referenced)
871 radeon_enc_code_fixed_bits(enc, 0x01, 8);
872 else
873 radeon_enc_code_fixed_bits(enc, 0x41, 8);
874
875 radeon_enc_flush_headers(enc);
876 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
877 num_bits[inst_index] = enc->bits_output - bits_copied;
878 bits_copied = enc->bits_output;
879 inst_index++;
880
881 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
882 inst_index++;
883
884 switch (enc->enc_pic.picture_type) {
885 case PIPE_H2645_ENC_PICTURE_TYPE_I:
886 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
887 radeon_enc_code_fixed_bits(enc, 0x08, 7);
888 break;
889 case PIPE_H2645_ENC_PICTURE_TYPE_P:
890 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
891 radeon_enc_code_fixed_bits(enc, 0x06, 5);
892 break;
893 case PIPE_H2645_ENC_PICTURE_TYPE_B:
894 radeon_enc_code_fixed_bits(enc, 0x07, 5);
895 break;
896 default:
897 radeon_enc_code_fixed_bits(enc, 0x08, 7);
898 }
899
900 radeon_enc_code_ue(enc, 0x0);
901 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
902
903 if (enc->enc_pic.h264_enc_params.input_picture_structure !=
904 RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
905 radeon_enc_code_fixed_bits(enc, 0x1, 1);
906 radeon_enc_code_fixed_bits(enc,
907 enc->enc_pic.h264_enc_params.input_picture_structure ==
908 RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
909 ? 1
910 : 0,
911 1);
912 }
913
914 if (enc->enc_pic.is_idr)
915 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
916
917 enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
918
919 if (enc->enc_pic.pic_order_cnt_type == 0)
920 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
921
922 /* ref_pic_list_modification() */
923 if (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR &&
924 enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_I) {
925 radeon_enc_code_fixed_bits(enc, 0x0, 1);
926
927 /* long-term reference */
928 if (enc->enc_pic.ref_idx_l0_is_ltr) {
929 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* ref_pic_list_modification_flag_l0 */
930 radeon_enc_code_ue(enc, 0x2); /* modification_of_pic_nums_idc */
931 radeon_enc_code_ue(enc, enc->enc_pic.ref_idx_l0); /* long_term_pic_num */
932 radeon_enc_code_ue(enc, 0x3);
933 }
934
935 /* short-term reference */
936 /* list_mod_diff_pic_minus1 != 0 */
937 else if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
938 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* ref_pic_list_modification_flag_l0 */
939 radeon_enc_code_ue(enc, 0x0); /* modification_of_pic_nums_idc */
940 /* abs_diff_pic_num_minus1 */
941 radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
942 radeon_enc_code_ue(enc, 0x3);
943 } else
944 radeon_enc_code_fixed_bits(enc, 0x0, 1);
945 }
946
947 if (enc->enc_pic.is_idr) {
948 radeon_enc_code_fixed_bits(enc, 0x0, 1);
949 if (enc->enc_pic.is_ltr)
950 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* long_term_reference_flag */
951 else
952 radeon_enc_code_fixed_bits(enc, 0x0, 1);
953 } else if (!enc->enc_pic.not_referenced) {
954 if (enc->enc_pic.is_ltr) {
955 radeon_enc_code_fixed_bits(enc, 0x1, 1);
956 radeon_enc_code_ue(enc, 0x4); /* memory_management_control_operation */
957 radeon_enc_code_ue(enc, enc->max_ltr_idx + 1); /* max_long_term_frame_idx_plus1 */
958 radeon_enc_code_ue(enc, 0x6); /*memory_management_control_operation */
959 radeon_enc_code_ue(enc, enc->enc_pic.ltr_idx); /* long_term_frame_idx */
960 radeon_enc_code_ue(enc, 0x0); /*memory_management_control_operation end*/
961 } else
962 radeon_enc_code_fixed_bits(enc, 0x0, 1);
963 }
964
965 if ((enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) &&
966 (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_I) &&
967 (enc->enc_pic.spec_misc.cabac_enable))
968 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
969
970 radeon_enc_flush_headers(enc);
971 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
972 num_bits[inst_index] = enc->bits_output - bits_copied;
973 bits_copied = enc->bits_output;
974 inst_index++;
975
976 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
977 inst_index++;
978
979 if (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag) {
980 radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
981 if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
982 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
983 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
984 }
985 }
986
987 radeon_enc_flush_headers(enc);
988 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
989 num_bits[inst_index] = enc->bits_output - bits_copied;
990 bits_copied = enc->bits_output;
991 inst_index++;
992
993 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
994
995 cdw_filled = enc->cs.current.cdw - cdw_start;
996 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
997 RADEON_ENC_CS(0x00000000);
998
999 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
1000 RADEON_ENC_CS(instruction[j]);
1001 RADEON_ENC_CS(num_bits[j]);
1002 }
1003
1004 RADEON_ENC_END();
1005 }
1006
radeon_enc_slice_header_hevc(struct radeon_encoder * enc)1007 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
1008 {
1009 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
1010 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
1011 unsigned int inst_index = 0;
1012 unsigned int cdw_start = 0;
1013 unsigned int cdw_filled = 0;
1014 unsigned int bits_copied = 0;
1015 RADEON_ENC_BEGIN(enc->cmd.slice_header);
1016 radeon_enc_reset(enc);
1017 radeon_enc_set_emulation_prevention(enc, false);
1018
1019 cdw_start = enc->cs.current.cdw;
1020 radeon_enc_code_fixed_bits(enc, 0x0, 1);
1021 radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
1022 radeon_enc_code_fixed_bits(enc, 0x0, 6);
1023 radeon_enc_code_fixed_bits(enc, 0x1, 3);
1024
1025 radeon_enc_flush_headers(enc);
1026 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1027 num_bits[inst_index] = enc->bits_output - bits_copied;
1028 bits_copied = enc->bits_output;
1029 inst_index++;
1030
1031 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
1032 inst_index++;
1033
1034 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
1035 radeon_enc_code_fixed_bits(enc, 0x0, 1);
1036
1037 radeon_enc_code_ue(enc, 0x0);
1038
1039 radeon_enc_flush_headers(enc);
1040 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1041 num_bits[inst_index] = enc->bits_output - bits_copied;
1042 bits_copied = enc->bits_output;
1043 inst_index++;
1044
1045 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
1046 inst_index++;
1047
1048 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
1049 inst_index++;
1050
1051 switch (enc->enc_pic.picture_type) {
1052 case PIPE_H2645_ENC_PICTURE_TYPE_I:
1053 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
1054 radeon_enc_code_ue(enc, 0x2);
1055 break;
1056 case PIPE_H2645_ENC_PICTURE_TYPE_P:
1057 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
1058 radeon_enc_code_ue(enc, 0x1);
1059 break;
1060 case PIPE_H2645_ENC_PICTURE_TYPE_B:
1061 radeon_enc_code_ue(enc, 0x0);
1062 break;
1063 default:
1064 radeon_enc_code_ue(enc, 0x1);
1065 }
1066
1067 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
1068 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
1069 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P)
1070 radeon_enc_code_fixed_bits(enc, 0x1, 1);
1071 else {
1072 radeon_enc_code_fixed_bits(enc, 0x0, 1);
1073 radeon_enc_code_fixed_bits(enc, 0x0, 1);
1074 radeon_enc_code_ue(enc, 0x0);
1075 radeon_enc_code_ue(enc, 0x0);
1076 }
1077 }
1078
1079 if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
1080 (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
1081 radeon_enc_code_fixed_bits(enc, 0x0, 1);
1082 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
1083 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
1084 }
1085
1086 radeon_enc_flush_headers(enc);
1087 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1088 num_bits[inst_index] = enc->bits_output - bits_copied;
1089 bits_copied = enc->bits_output;
1090 inst_index++;
1091
1092 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
1093 inst_index++;
1094
1095 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
1096 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
1097 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled,
1098 1);
1099
1100 radeon_enc_flush_headers(enc);
1101 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
1102 num_bits[inst_index] = enc->bits_output - bits_copied;
1103 bits_copied = enc->bits_output;
1104 inst_index++;
1105 }
1106
1107 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
1108
1109 cdw_filled = enc->cs.current.cdw - cdw_start;
1110 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
1111 RADEON_ENC_CS(0x00000000);
1112
1113 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
1114 RADEON_ENC_CS(instruction[j]);
1115 RADEON_ENC_CS(num_bits[j]);
1116 }
1117
1118 RADEON_ENC_END();
1119 }
1120
radeon_enc_ctx(struct radeon_encoder * enc)1121 static void radeon_enc_ctx(struct radeon_encoder *enc)
1122 {
1123 enc->enc_pic.ctx_buf.swizzle_mode = 0;
1124 enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0;
1125
1126 RADEON_ENC_BEGIN(enc->cmd.ctx);
1127 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
1128 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
1129 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
1130 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
1131 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
1132
1133 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1134 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
1135 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
1136 }
1137
1138 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_luma_pitch);
1139 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_chroma_pitch);
1140
1141 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
1142 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].luma_offset);
1143 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].chroma_offset);
1144 }
1145
1146 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.yuv.luma_offset);
1147 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.yuv.chroma_offset);
1148
1149 RADEON_ENC_CS(enc->enc_pic.ctx_buf.two_pass_search_center_map_offset);
1150 RADEON_ENC_END();
1151 }
1152
radeon_enc_bitstream(struct radeon_encoder * enc)1153 static void radeon_enc_bitstream(struct radeon_encoder *enc)
1154 {
1155 enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
1156 enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
1157 enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
1158
1159 RADEON_ENC_BEGIN(enc->cmd.bitstream);
1160 RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
1161 RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
1162 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
1163 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
1164 RADEON_ENC_END();
1165 }
1166
radeon_enc_feedback(struct radeon_encoder * enc)1167 static void radeon_enc_feedback(struct radeon_encoder *enc)
1168 {
1169 enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
1170 enc->enc_pic.fb_buf.feedback_buffer_size = 16;
1171 enc->enc_pic.fb_buf.feedback_data_size = 40;
1172
1173 RADEON_ENC_BEGIN(enc->cmd.feedback);
1174 RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
1175 RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
1176 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
1177 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
1178 RADEON_ENC_END();
1179 }
1180
radeon_enc_intra_refresh(struct radeon_encoder * enc)1181 static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
1182 {
1183 RADEON_ENC_BEGIN(enc->cmd.intra_refresh);
1184 RADEON_ENC_CS(enc->enc_pic.intra_refresh.intra_refresh_mode);
1185 RADEON_ENC_CS(enc->enc_pic.intra_refresh.offset);
1186 RADEON_ENC_CS(enc->enc_pic.intra_refresh.region_size);
1187 RADEON_ENC_END();
1188 }
1189
radeon_enc_rc_per_pic(struct radeon_encoder * enc)1190 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc)
1191 {
1192 RADEON_ENC_BEGIN(enc->cmd.rc_per_pic);
1193 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
1194 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
1195 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
1196 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
1197 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
1198 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
1199 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
1200 RADEON_ENC_END();
1201 }
1202
radeon_enc_encode_params(struct radeon_encoder * enc)1203 static void radeon_enc_encode_params(struct radeon_encoder *enc)
1204 {
1205 switch (enc->enc_pic.picture_type) {
1206 case PIPE_H2645_ENC_PICTURE_TYPE_I:
1207 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
1208 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1209 break;
1210 case PIPE_H2645_ENC_PICTURE_TYPE_P:
1211 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1212 break;
1213 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
1214 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1215 break;
1216 case PIPE_H2645_ENC_PICTURE_TYPE_B:
1217 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1218 break;
1219 default:
1220 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1221 }
1222
1223 if (enc->luma->meta_offset) {
1224 RVID_ERR("DCC surfaces not supported.\n");
1225 assert(false);
1226 }
1227
1228 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1229 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1230 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma ?
1231 enc->chroma->u.gfx9.surf_pitch : enc->luma->u.gfx9.surf_pitch;
1232 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
1233
1234 RADEON_ENC_BEGIN(enc->cmd.enc_params);
1235 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1236 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1237 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1238 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma ?
1239 enc->chroma->u.gfx9.surf_offset : enc->luma->u.gfx9.surf_pitch);
1240 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1241 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1242 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1243 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1244 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1245 RADEON_ENC_END();
1246 }
1247
radeon_enc_encode_params_h264(struct radeon_encoder * enc)1248 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
1249 {
1250 enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1251 enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
1252 enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1253 enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
1254
1255 RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
1256 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
1257 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
1258 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
1259 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
1260 RADEON_ENC_END();
1261 }
1262
radeon_enc_encode_statistics(struct radeon_encoder * enc)1263 static void radeon_enc_encode_statistics(struct radeon_encoder *enc)
1264 {
1265 if (!enc->stats) return;
1266
1267 enc->enc_pic.enc_statistics.encode_stats_type = RENCODE_STATISTICS_TYPE_0;
1268
1269 RADEON_ENC_BEGIN(enc->cmd.enc_statistics);
1270 RADEON_ENC_CS(enc->enc_pic.enc_statistics.encode_stats_type);
1271 RADEON_ENC_WRITE(enc->stats, RADEON_DOMAIN_GTT, 0);
1272 RADEON_ENC_END();
1273 }
1274
radeon_enc_qp_map(struct radeon_encoder * enc)1275 static void radeon_enc_qp_map(struct radeon_encoder *enc)
1276 {
1277 if (enc->enc_pic.enc_qp_map.qp_map_type == RENCODE_QP_MAP_TYPE_NONE)
1278 return;
1279 enc->enc_pic.enc_qp_map.qp_map_pitch = 0;
1280
1281 RADEON_ENC_BEGIN(enc->cmd.enc_qp_map);
1282 RADEON_ENC_CS(enc->enc_pic.enc_qp_map.qp_map_type);
1283 RADEON_ENC_READWRITE(enc->roi->res->buf, enc->roi->res->domains, 0);
1284 RADEON_ENC_CS(enc->enc_pic.enc_qp_map.qp_map_pitch);
1285 RADEON_ENC_END();
1286 }
1287
radeon_enc_op_init(struct radeon_encoder * enc)1288 static void radeon_enc_op_init(struct radeon_encoder *enc)
1289 {
1290 RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
1291 RADEON_ENC_END();
1292 }
1293
radeon_enc_op_close(struct radeon_encoder * enc)1294 static void radeon_enc_op_close(struct radeon_encoder *enc)
1295 {
1296 RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
1297 RADEON_ENC_END();
1298 }
1299
radeon_enc_op_enc(struct radeon_encoder * enc)1300 static void radeon_enc_op_enc(struct radeon_encoder *enc)
1301 {
1302 RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
1303 RADEON_ENC_END();
1304 }
1305
radeon_enc_op_init_rc(struct radeon_encoder * enc)1306 static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
1307 {
1308 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
1309 RADEON_ENC_END();
1310 }
1311
radeon_enc_op_init_rc_vbv(struct radeon_encoder * enc)1312 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
1313 {
1314 RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1315 RADEON_ENC_END();
1316 }
1317
radeon_enc_op_preset(struct radeon_encoder * enc)1318 static void radeon_enc_op_preset(struct radeon_encoder *enc)
1319 {
1320 uint32_t preset_mode;
1321
1322 if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_QUALITY)
1323 preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE;
1324 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_BALANCE)
1325 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
1326 else
1327 preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE;
1328
1329 RADEON_ENC_BEGIN(preset_mode);
1330 RADEON_ENC_END();
1331 }
1332
begin(struct radeon_encoder * enc)1333 static void begin(struct radeon_encoder *enc)
1334 {
1335 unsigned i;
1336
1337 enc->session_info(enc);
1338 enc->total_task_size = 0;
1339 enc->task_info(enc, enc->need_feedback);
1340 enc->op_init(enc);
1341
1342 enc->session_init(enc);
1343 enc->slice_control(enc);
1344 enc->spec_misc(enc);
1345 enc->deblocking_filter(enc);
1346
1347 enc->layer_control(enc);
1348 enc->rc_session_init(enc);
1349 enc->quality_params(enc);
1350
1351 i = 0;
1352 do {
1353 enc->enc_pic.temporal_id = i;
1354 enc->layer_select(enc);
1355 enc->rc_layer_init(enc);
1356 enc->layer_select(enc);
1357 enc->rc_per_pic(enc);
1358 } while (++i < enc->enc_pic.num_temporal_layers);
1359
1360 enc->op_init_rc(enc);
1361 enc->op_init_rc_vbv(enc);
1362 *enc->p_task_size = (enc->total_task_size);
1363 }
1364
radeon_enc_headers_h264(struct radeon_encoder * enc)1365 static void radeon_enc_headers_h264(struct radeon_encoder *enc)
1366 {
1367 enc->nalu_aud(enc);
1368 if (enc->enc_pic.layer_ctrl.num_temporal_layers > 1)
1369 enc->nalu_prefix(enc);
1370 if (enc->enc_pic.is_idr || enc->enc_pic.need_sequence_header) {
1371 if (enc->enc_pic.layer_ctrl.num_temporal_layers > 1)
1372 enc->nalu_sei(enc);
1373 enc->nalu_sps(enc);
1374 enc->nalu_pps(enc);
1375 }
1376 enc->slice_header(enc);
1377 enc->encode_params(enc);
1378 enc->encode_params_codec_spec(enc);
1379 }
1380
radeon_enc_headers_hevc(struct radeon_encoder * enc)1381 static void radeon_enc_headers_hevc(struct radeon_encoder *enc)
1382 {
1383 enc->nalu_aud(enc);
1384 if (enc->enc_pic.is_idr || enc->enc_pic.need_sequence_header) {
1385 enc->nalu_vps(enc);
1386 enc->nalu_pps(enc);
1387 enc->nalu_sps(enc);
1388 }
1389 enc->slice_header(enc);
1390 enc->encode_params(enc);
1391 }
1392
encode(struct radeon_encoder * enc)1393 static void encode(struct radeon_encoder *enc)
1394 {
1395 unsigned i;
1396
1397 enc->before_encode(enc);
1398 enc->session_info(enc);
1399 enc->total_task_size = 0;
1400 enc->task_info(enc, enc->need_feedback);
1401
1402 if (enc->need_rate_control) {
1403 i = 0;
1404 do {
1405 enc->enc_pic.temporal_id = i;
1406 enc->layer_select(enc);
1407 enc->rc_layer_init(enc);
1408 } while (++i < enc->enc_pic.num_temporal_layers);
1409 }
1410
1411 enc->encode_headers(enc);
1412 enc->ctx(enc);
1413 enc->bitstream(enc);
1414 enc->feedback(enc);
1415 enc->intra_refresh(enc);
1416 enc->qp_map(enc);
1417
1418 enc->op_preset(enc);
1419 enc->op_enc(enc);
1420 *enc->p_task_size = (enc->total_task_size);
1421 }
1422
destroy(struct radeon_encoder * enc)1423 static void destroy(struct radeon_encoder *enc)
1424 {
1425 enc->session_info(enc);
1426 enc->total_task_size = 0;
1427 enc->task_info(enc, enc->need_feedback);
1428 enc->op_close(enc);
1429 *enc->p_task_size = (enc->total_task_size);
1430 }
1431
find_ref_idx(struct radeon_encoder * enc,int pic_num,bool is_ltr)1432 static int find_ref_idx(struct radeon_encoder *enc, int pic_num, bool is_ltr)
1433 {
1434 for (int i = 0; i < enc->base.max_references + 1; i++) {
1435 if (enc->dpb_info[i].pic_num == pic_num &&
1436 enc->dpb_info[i].in_use &&
1437 enc->dpb_info[i].is_ltr == is_ltr)
1438 return i;
1439 }
1440
1441 return -1;
1442 }
1443
get_picture_storage(struct radeon_encoder * enc)1444 static int get_picture_storage(struct radeon_encoder *enc)
1445 {
1446 if (enc->enc_pic.is_ltr) {
1447 if (enc->enc_pic.is_idr) {
1448 enc->enc_pic.ltr_idx = 0;
1449 enc->max_ltr_idx = 0;
1450 }
1451 /*
1452 find ltr with the same ltr_idx to replace
1453 if this is a new ltr_idx, increase max_ltr_idx and use the normal logic to find slot
1454 */
1455 if (enc->enc_pic.ltr_idx <= enc->max_ltr_idx) {
1456 for (int i = 0; i < enc->base.max_references + 1; i++) {
1457 if (enc->dpb_info[i].in_use &&
1458 enc->dpb_info[i].is_ltr &&
1459 enc->enc_pic.ltr_idx == enc->dpb_info[i].pic_num) {
1460 enc->dpb_info[i].in_use = false;
1461 return i;
1462 }
1463 }
1464 } else
1465 enc->max_ltr_idx = enc->enc_pic.ltr_idx;
1466 }
1467
1468 for (int i = 0; i < enc->base.max_references + 1; i++) {
1469 if (!enc->dpb_info[i].in_use) {
1470 memset(&(enc->dpb_info[i]), 0, sizeof(rvcn_enc_picture_info_t));
1471 return i;
1472 }
1473 }
1474
1475 /* look for the oldest short term ref pic */
1476 unsigned int oldest_frame_num = 0xFFFFFFFF;
1477 int oldest_idx = -1;
1478 for (int i = 0; i < enc->base.max_references + 1; i++)
1479 if (!enc->dpb_info[i].is_ltr && enc->dpb_info[i].pic_num < oldest_frame_num) {
1480 oldest_frame_num = enc->dpb_info[i].pic_num;
1481 oldest_idx = i;
1482 }
1483
1484 if (oldest_idx >= 0)
1485 enc->dpb_info[oldest_idx].in_use = false;
1486
1487 return oldest_idx;
1488 }
1489
manage_dpb_before_encode(struct radeon_encoder * enc)1490 static void manage_dpb_before_encode(struct radeon_encoder *enc)
1491 {
1492 int current_pic_idx = 0;
1493
1494 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) {
1495 /* clear reference frames */
1496 for (int i = 0; i < enc->base.max_references + 1; i++)
1497 memset(&(enc->dpb_info[i]), 0, sizeof(rvcn_enc_picture_info_t));
1498 }
1499
1500 current_pic_idx = get_picture_storage(enc);
1501 assert(current_pic_idx >= 0);
1502
1503 int ref0_idx = find_ref_idx(enc, enc->enc_pic.ref_idx_l0, enc->enc_pic.ref_idx_l0_is_ltr);
1504 /* B-frames only supported on VCN >= 3.0 */
1505 int ref1_idx = find_ref_idx(enc, enc->enc_pic.ref_idx_l1, enc->enc_pic.ref_idx_l1_is_ltr);
1506
1507 assert(enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_P ||
1508 ref0_idx != -1);
1509 assert(enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_B ||
1510 (ref0_idx != -1 && ref1_idx != -1));
1511
1512 /* In case we didn't find the reference in dpb, we have to pick
1513 * some valid index to prevent GPU hang. */
1514 if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P ||
1515 enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) &&
1516 ref0_idx == -1) {
1517 RVID_ERR("Failed to find ref0 (%u).\n", enc->enc_pic.ref_idx_l0);
1518 ref0_idx = (current_pic_idx + 1) % (enc->base.max_references + 1);
1519 }
1520
1521 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B && ref1_idx == -1) {
1522 RVID_ERR("Failed to find ref1 (%u).\n", enc->enc_pic.ref_idx_l1);
1523 ref1_idx = (current_pic_idx + 2) % (enc->base.max_references + 1);
1524 }
1525
1526 if (!enc->enc_pic.not_referenced)
1527 enc->dpb_info[current_pic_idx].in_use = true;
1528
1529 if (enc->enc_pic.is_ltr) {
1530 enc->dpb_info[current_pic_idx].pic_num = enc->enc_pic.ltr_idx;
1531 enc->dpb_info[current_pic_idx].is_ltr = true;
1532 } else {
1533 enc->dpb_info[current_pic_idx].pic_num = enc->enc_pic.frame_num;
1534 enc->dpb_info[current_pic_idx].is_ltr = false;
1535 }
1536
1537 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) {
1538 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1539 enc->enc_pic.h264_enc_params.l1_reference_picture0_index = 0xFFFFFFFF;
1540 } else {
1541 enc->enc_pic.enc_params.reference_picture_index = ref0_idx;
1542 enc->enc_pic.h264_enc_params.l1_reference_picture0_index = ref1_idx;
1543 }
1544 enc->enc_pic.enc_params.reconstructed_picture_index = current_pic_idx;
1545 enc->enc_pic.h264_enc_params.is_reference = !enc->enc_pic.not_referenced;
1546 }
1547
radeon_enc_1_2_init(struct radeon_encoder * enc)1548 void radeon_enc_1_2_init(struct radeon_encoder *enc)
1549 {
1550 enc->before_encode = manage_dpb_before_encode;
1551 enc->begin = begin;
1552 enc->encode = encode;
1553 enc->destroy = destroy;
1554 enc->session_info = radeon_enc_session_info;
1555 enc->task_info = radeon_enc_task_info;
1556 enc->layer_control = radeon_enc_layer_control;
1557 enc->layer_select = radeon_enc_layer_select;
1558 enc->rc_session_init = radeon_enc_rc_session_init;
1559 enc->rc_layer_init = radeon_enc_rc_layer_init;
1560 enc->quality_params = radeon_enc_quality_params;
1561 enc->ctx = radeon_enc_ctx;
1562 enc->bitstream = radeon_enc_bitstream;
1563 enc->feedback = radeon_enc_feedback;
1564 enc->intra_refresh = radeon_enc_intra_refresh;
1565 enc->rc_per_pic = radeon_enc_rc_per_pic;
1566 enc->encode_params = radeon_enc_encode_params;
1567 enc->op_init = radeon_enc_op_init;
1568 enc->op_close = radeon_enc_op_close;
1569 enc->op_enc = radeon_enc_op_enc;
1570 enc->op_init_rc = radeon_enc_op_init_rc;
1571 enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv;
1572 enc->op_preset = radeon_enc_op_preset;
1573 enc->session_init = radeon_enc_session_init;
1574 enc->encode_statistics = radeon_enc_encode_statistics;
1575 enc->nalu_aud = radeon_enc_nalu_aud;
1576 enc->qp_map = radeon_enc_qp_map;
1577
1578 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1579 enc->slice_control = radeon_enc_slice_control;
1580 enc->spec_misc = radeon_enc_spec_misc;
1581 enc->deblocking_filter = radeon_enc_deblocking_filter_h264;
1582 enc->nalu_sps = radeon_enc_nalu_sps;
1583 enc->nalu_pps = radeon_enc_nalu_pps;
1584 enc->slice_header = radeon_enc_slice_header;
1585 enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
1586 enc->encode_headers = radeon_enc_headers_h264;
1587 enc->nalu_prefix = radeon_enc_nalu_prefix;
1588 enc->nalu_sei = radeon_enc_nalu_sei;
1589 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1590 enc->slice_control = radeon_enc_slice_control_hevc;
1591 enc->spec_misc = radeon_enc_spec_misc_hevc;
1592 enc->deblocking_filter = radeon_enc_deblocking_filter_hevc;
1593 enc->nalu_sps = radeon_enc_nalu_sps_hevc;
1594 enc->nalu_pps = radeon_enc_nalu_pps_hevc;
1595 enc->nalu_vps = radeon_enc_nalu_vps;
1596 enc->slice_header = radeon_enc_slice_header_hevc;
1597 enc->encode_headers = radeon_enc_headers_hevc;
1598 }
1599
1600 enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
1601 enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
1602 enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
1603 enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
1604 enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
1605 enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
1606 enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
1607 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
1608 enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
1609 enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
1610 enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
1611 enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
1612 enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
1613 enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
1614 enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
1615 enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
1616 enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
1617 enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
1618 enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
1619 enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
1620 enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
1621 enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
1622 enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
1623 enc->cmd.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
1624 enc->cmd.enc_qp_map = RENCODE_IB_PARAM_QP_MAP;
1625
1626 enc->enc_pic.session_info.interface_version =
1627 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
1628 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
1629 }
1630