1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include "pipe/p_video_codec.h"
10 #include "radeon_vcn_enc.h"
11 #include "radeon_video.h"
12 #include "si_pipe.h"
13 #include "util/u_video.h"
14
15 #include <stdio.h>
16
17 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
18 #define RENCODE_FW_INTERFACE_MINOR_VERSION 1
19
20 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
21 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002
22 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
23 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004
24 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005
25 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
26 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007
27 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008
28 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009
29 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x0000000a
30 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000b
31 #define RENCODE_IB_PARAM_INPUT_FORMAT 0x0000000c
32 #define RENCODE_IB_PARAM_OUTPUT_FORMAT 0x0000000d
33 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000f
34 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x00000010
35 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x00000011
36 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x00000012
37 #define RENCODE_IB_PARAM_QP_MAP 0x00000014
38 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000015
39 #define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x00000019
40
41 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
42 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
43 #define RENCODE_HEVC_IB_PARAM_LOOP_FILTER 0x00100003
44
45 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
46 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
47 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
48 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
49
radeon_enc_op_preset(struct radeon_encoder * enc)50 static void radeon_enc_op_preset(struct radeon_encoder *enc)
51 {
52 uint32_t preset_mode;
53
54 if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_SPEED &&
55 (enc->enc_pic.sample_adaptive_offset_enabled_flag &&
56 (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC)))
57 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
58 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_QUALITY)
59 preset_mode = RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE;
60 else if (enc->enc_pic.quality_modes.preset_mode == RENCODE_PRESET_MODE_BALANCE)
61 preset_mode = RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE;
62 else
63 preset_mode = RENCODE_IB_OP_SET_SPEED_ENCODING_MODE;
64
65 RADEON_ENC_BEGIN(preset_mode);
66 RADEON_ENC_END();
67 }
68
radeon_enc_quality_params(struct radeon_encoder * enc)69 static void radeon_enc_quality_params(struct radeon_encoder *enc)
70 {
71 enc->enc_pic.quality_params.vbaq_mode = enc->enc_pic.quality_modes.vbaq_mode;
72 enc->enc_pic.quality_params.scene_change_sensitivity = 0;
73 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
74 enc->enc_pic.quality_params.two_pass_search_center_map_mode =
75 (enc->enc_pic.quality_modes.pre_encode_mode) ? 1 : 0;
76 enc->enc_pic.quality_params.vbaq_strength = 0;
77
78 RADEON_ENC_BEGIN(enc->cmd.quality_params);
79 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
80 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
81 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
82 RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
83 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_strength);
84 RADEON_ENC_END();
85 }
86
radeon_enc_slice_header_hevc(struct radeon_encoder * enc)87 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
88 {
89 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
90 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
91 unsigned int inst_index = 0;
92 unsigned int cdw_start = 0;
93 unsigned int cdw_filled = 0;
94 unsigned int bits_copied = 0;
95 RADEON_ENC_BEGIN(enc->cmd.slice_header);
96 radeon_enc_reset(enc);
97 radeon_enc_set_emulation_prevention(enc, false);
98
99 cdw_start = enc->cs.current.cdw;
100 radeon_enc_code_fixed_bits(enc, 0x0, 1);
101 radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
102 radeon_enc_code_fixed_bits(enc, 0x0, 6);
103 radeon_enc_code_fixed_bits(enc, 0x1, 3);
104
105 radeon_enc_flush_headers(enc);
106 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
107 num_bits[inst_index] = enc->bits_output - bits_copied;
108 bits_copied = enc->bits_output;
109 inst_index++;
110
111 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
112 inst_index++;
113
114 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
115 radeon_enc_code_fixed_bits(enc, 0x0, 1);
116
117 radeon_enc_code_ue(enc, 0x0);
118
119 radeon_enc_flush_headers(enc);
120 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
121 num_bits[inst_index] = enc->bits_output - bits_copied;
122 bits_copied = enc->bits_output;
123 inst_index++;
124
125 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
126 inst_index++;
127
128 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
129 inst_index++;
130
131 switch (enc->enc_pic.picture_type) {
132 case PIPE_H2645_ENC_PICTURE_TYPE_I:
133 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
134 radeon_enc_code_ue(enc, 0x2);
135 break;
136 case PIPE_H2645_ENC_PICTURE_TYPE_P:
137 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
138 radeon_enc_code_ue(enc, 0x1);
139 break;
140 case PIPE_H2645_ENC_PICTURE_TYPE_B:
141 radeon_enc_code_ue(enc, 0x0);
142 break;
143 default:
144 radeon_enc_code_ue(enc, 0x1);
145 }
146
147 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
148 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
149 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P)
150 radeon_enc_code_fixed_bits(enc, 0x1, 1);
151 else {
152 radeon_enc_code_fixed_bits(enc, 0x0, 1);
153 radeon_enc_code_fixed_bits(enc, 0x0, 1);
154 radeon_enc_code_ue(enc, 0x0);
155 radeon_enc_code_ue(enc, 0x0);
156 }
157 }
158
159 if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
160 radeon_enc_flush_headers(enc);
161 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
162 num_bits[inst_index] = enc->bits_output - bits_copied;
163 bits_copied = enc->bits_output;
164 inst_index++;
165
166 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE;
167 inst_index++;
168 }
169
170 if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
171 (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
172 radeon_enc_code_fixed_bits(enc, 0x0, 1);
173 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
174 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
175 }
176
177 radeon_enc_flush_headers(enc);
178 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
179 num_bits[inst_index] = enc->bits_output - bits_copied;
180 bits_copied = enc->bits_output;
181 inst_index++;
182
183 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
184 inst_index++;
185
186 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
187 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled ||
188 enc->enc_pic.sample_adaptive_offset_enabled_flag)) {
189 if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
190 radeon_enc_flush_headers(enc);
191 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
192 num_bits[inst_index] = enc->bits_output - bits_copied;
193 bits_copied = enc->bits_output;
194 inst_index++;
195
196 instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE;
197 inst_index++;
198 }
199 else
200 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
201 }
202
203 radeon_enc_flush_headers(enc);
204 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
205 num_bits[inst_index] = enc->bits_output - bits_copied;
206 bits_copied = enc->bits_output;
207 inst_index++;
208 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
209
210 cdw_filled = enc->cs.current.cdw - cdw_start;
211 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
212 RADEON_ENC_CS(0x00000000);
213
214 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
215 RADEON_ENC_CS(instruction[j]);
216 RADEON_ENC_CS(num_bits[j]);
217 }
218
219 RADEON_ENC_END();
220 }
221
radeon_enc_loop_filter_hevc(struct radeon_encoder * enc)222 static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc)
223 {
224 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
225 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
226 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
227 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
228 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
229 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
230 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
231 RADEON_ENC_CS(!enc->enc_pic.sample_adaptive_offset_enabled_flag);
232 RADEON_ENC_END();
233 }
234
radeon_enc_nalu_sps_hevc(struct radeon_encoder * enc)235 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
236 {
237 struct radeon_enc_pic *pic = &enc->enc_pic;
238 RADEON_ENC_BEGIN(enc->cmd.nalu);
239 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
240 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
241 int i;
242
243 radeon_enc_reset(enc);
244 radeon_enc_set_emulation_prevention(enc, false);
245 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
246 radeon_enc_code_fixed_bits(enc, 0x4201, 16);
247 radeon_enc_byte_align(enc);
248 radeon_enc_set_emulation_prevention(enc, true);
249 radeon_enc_code_fixed_bits(enc, 0x0, 4);
250 radeon_enc_code_fixed_bits(enc, pic->layer_ctrl.max_num_temporal_layers - 1, 3);
251 radeon_enc_code_fixed_bits(enc, 0x1, 1);
252 radeon_enc_code_fixed_bits(enc, 0x0, 2);
253 radeon_enc_code_fixed_bits(enc, pic->general_tier_flag, 1);
254 radeon_enc_code_fixed_bits(enc, pic->general_profile_idc, 5);
255
256 if (pic->general_profile_idc == 2)
257 radeon_enc_code_fixed_bits(enc, 0x20000000, 32);
258 else
259 radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
260
261 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
262 radeon_enc_code_fixed_bits(enc, 0x0, 16);
263 radeon_enc_code_fixed_bits(enc, pic->general_level_idc, 8);
264
265 for (i = 0; i < (pic->layer_ctrl.max_num_temporal_layers - 1); i++)
266 radeon_enc_code_fixed_bits(enc, 0x0, 2);
267
268 if ((pic->layer_ctrl.max_num_temporal_layers - 1) > 0) {
269 for (i = (pic->layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
270 radeon_enc_code_fixed_bits(enc, 0x0, 2);
271 }
272
273 radeon_enc_code_ue(enc, 0x0);
274 radeon_enc_code_ue(enc, pic->chroma_format_idc);
275 radeon_enc_code_ue(enc, pic->session_init.aligned_picture_width);
276 radeon_enc_code_ue(enc, pic->session_init.aligned_picture_height);
277
278 if ((pic->crop_left != 0) || (pic->crop_right != 0) ||
279 (pic->crop_top != 0) || (pic->crop_bottom != 0)) {
280 radeon_enc_code_fixed_bits(enc, 0x1, 1);
281 radeon_enc_code_ue(enc, pic->crop_left);
282 radeon_enc_code_ue(enc, pic->crop_right);
283 radeon_enc_code_ue(enc, pic->crop_top);
284 radeon_enc_code_ue(enc, pic->crop_bottom);
285 } else if (pic->session_init.padding_width != 0 ||
286 pic->session_init.padding_height != 0) {
287 radeon_enc_code_fixed_bits(enc, 0x1, 1);
288 radeon_enc_code_ue(enc, 0);
289 radeon_enc_code_ue(enc, pic->session_init.padding_width / 2);
290 radeon_enc_code_ue(enc, 0);
291 radeon_enc_code_ue(enc, pic->session_init.padding_height / 2);
292 } else
293 radeon_enc_code_fixed_bits(enc, 0x0, 1);
294
295 radeon_enc_code_ue(enc, pic->bit_depth_luma_minus8);
296 radeon_enc_code_ue(enc, pic->bit_depth_chroma_minus8);
297 radeon_enc_code_ue(enc, pic->log2_max_poc - 4);
298 radeon_enc_code_fixed_bits(enc, 0x0, 1);
299 radeon_enc_code_ue(enc, 1);
300 radeon_enc_code_ue(enc, 0x0);
301 radeon_enc_code_ue(enc, 0x0);
302 radeon_enc_code_ue(enc, pic->hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
303 // Only support CTBSize 64
304 radeon_enc_code_ue(enc,
305 6 - (pic->hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
306 radeon_enc_code_ue(enc, pic->log2_min_transform_block_size_minus2);
307 radeon_enc_code_ue(enc, pic->log2_diff_max_min_transform_block_size);
308 radeon_enc_code_ue(enc, pic->max_transform_hierarchy_depth_inter);
309 radeon_enc_code_ue(enc, pic->max_transform_hierarchy_depth_intra);
310
311 radeon_enc_code_fixed_bits(enc, 0x0, 1);
312 radeon_enc_code_fixed_bits(enc, !pic->hevc_spec_misc.amp_disabled, 1);
313 radeon_enc_code_fixed_bits(enc, pic->sample_adaptive_offset_enabled_flag, 1);
314 radeon_enc_code_fixed_bits(enc, pic->pcm_enabled_flag, 1);
315
316 radeon_enc_code_ue(enc, 1);
317 radeon_enc_code_ue(enc, 1);
318 radeon_enc_code_ue(enc, 0);
319 radeon_enc_code_ue(enc, 0);
320 radeon_enc_code_fixed_bits(enc, 0x1, 1);
321
322 radeon_enc_code_fixed_bits(enc, 0x0, 1);
323
324 radeon_enc_code_fixed_bits(enc, 0, 1);
325 radeon_enc_code_fixed_bits(enc, pic->hevc_spec_misc.strong_intra_smoothing_enabled, 1);
326
327 /* VUI parameters present flag */
328 radeon_enc_code_fixed_bits(enc, (pic->vui_info.vui_parameters_present_flag), 1);
329 if (pic->vui_info.vui_parameters_present_flag) {
330 /* aspect ratio present flag */
331 radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.aspect_ratio_info_present_flag), 1);
332 if (pic->vui_info.flags.aspect_ratio_info_present_flag) {
333 radeon_enc_code_fixed_bits(enc, (pic->vui_info.aspect_ratio_idc), 8);
334 if (pic->vui_info.aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
335 radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_width), 16);
336 radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_height), 16);
337 }
338 }
339 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* overscan info present flag */
340 /* video signal type present flag */
341 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.video_signal_type_present_flag, 1);
342 if (pic->vui_info.flags.video_signal_type_present_flag) {
343 radeon_enc_code_fixed_bits(enc, pic->vui_info.video_format, 3);
344 radeon_enc_code_fixed_bits(enc, pic->vui_info.video_full_range_flag, 1);
345 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.colour_description_present_flag, 1);
346 if (pic->vui_info.flags.colour_description_present_flag) {
347 radeon_enc_code_fixed_bits(enc, pic->vui_info.colour_primaries, 8);
348 radeon_enc_code_fixed_bits(enc, pic->vui_info.transfer_characteristics, 8);
349 radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
350 }
351 }
352 /* chroma loc info present flag */
353 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
354 if (pic->vui_info.flags.chroma_loc_info_present_flag) {
355 radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
356 radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
357 }
358 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* neutral chroma indication flag */
359 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* field seq flag */
360 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* frame field info present flag */
361 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* default display windows flag */
362 /* vui timing info present flag */
363 radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.timing_info_present_flag), 1);
364 if (pic->vui_info.flags.timing_info_present_flag) {
365 radeon_enc_code_fixed_bits(enc, (pic->vui_info.num_units_in_tick), 32);
366 radeon_enc_code_fixed_bits(enc, (pic->vui_info.time_scale), 32);
367 radeon_enc_code_fixed_bits(enc, 0x0, 1);
368 radeon_enc_code_fixed_bits(enc, 0x0, 1);
369 }
370 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* bitstream restriction flag */
371 }
372 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* sps extension present flag */
373 radeon_enc_code_fixed_bits(enc, 0x1, 1);
374
375 radeon_enc_byte_align(enc);
376 radeon_enc_flush_headers(enc);
377 *size_in_bytes = (enc->bits_output + 7) / 8;
378 RADEON_ENC_END();
379 }
380
radeon_enc_nalu_pps_hevc(struct radeon_encoder * enc)381 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
382 {
383 RADEON_ENC_BEGIN(enc->cmd.nalu);
384 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
385 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
386 radeon_enc_reset(enc);
387 radeon_enc_set_emulation_prevention(enc, false);
388 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
389 radeon_enc_code_fixed_bits(enc, 0x4401, 16);
390 radeon_enc_byte_align(enc);
391 radeon_enc_set_emulation_prevention(enc, true);
392 radeon_enc_code_ue(enc, 0x0);
393 radeon_enc_code_ue(enc, 0x0);
394 radeon_enc_code_fixed_bits(enc, 0x1, 1);
395 radeon_enc_code_fixed_bits(enc, 0x0, 4);
396 radeon_enc_code_fixed_bits(enc, 0x0, 1);
397 radeon_enc_code_fixed_bits(enc, 0x1, 1);
398 radeon_enc_code_ue(enc, 0x0);
399 radeon_enc_code_ue(enc, 0x0);
400 radeon_enc_code_se(enc, 0x0);
401 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
402 radeon_enc_code_fixed_bits(enc, 0x0, 1);
403 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE &&
404 enc->enc_pic.enc_qp_map.qp_map_type == RENCODE_QP_MAP_TYPE_NONE)
405 radeon_enc_code_fixed_bits(enc, 0x0, 1);
406 else {
407 radeon_enc_code_fixed_bits(enc, 0x1, 1);
408 radeon_enc_code_ue(enc, 0x0);
409 }
410 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
411 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
412 radeon_enc_code_fixed_bits(enc, 0x0, 1);
413 radeon_enc_code_fixed_bits(enc, 0x0, 2);
414 radeon_enc_code_fixed_bits(enc, 0x0, 1);
415 radeon_enc_code_fixed_bits(enc, 0x0, 1);
416 radeon_enc_code_fixed_bits(enc, 0x0, 1);
417 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
418 radeon_enc_code_fixed_bits(enc, 0x1, 1);
419 radeon_enc_code_fixed_bits(enc, 0x0, 1);
420 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
421
422 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
423 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
424 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
425 }
426
427 radeon_enc_code_fixed_bits(enc, 0x0, 1);
428 radeon_enc_code_fixed_bits(enc, 0x0, 1);
429 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
430 radeon_enc_code_fixed_bits(enc, 0x0, 2);
431
432 radeon_enc_code_fixed_bits(enc, 0x1, 1);
433
434 radeon_enc_byte_align(enc);
435 radeon_enc_flush_headers(enc);
436 *size_in_bytes = (enc->bits_output + 7) / 8;
437 RADEON_ENC_END();
438 }
439
radeon_enc_input_format(struct radeon_encoder * enc)440 static void radeon_enc_input_format(struct radeon_encoder *enc)
441 {
442 RADEON_ENC_BEGIN(enc->cmd.input_format);
443 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_color_volume);
444 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_color_space);
445 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_color_range);
446 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_chroma_subsampling);
447 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_chroma_location);
448 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_color_bit_depth);
449 RADEON_ENC_CS(enc->enc_pic.enc_input_format.input_color_packing_format);
450 RADEON_ENC_END();
451 }
452
radeon_enc_output_format(struct radeon_encoder * enc)453 static void radeon_enc_output_format(struct radeon_encoder *enc)
454 {
455 RADEON_ENC_BEGIN(enc->cmd.output_format);
456 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_color_volume);
457 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_color_range);
458 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_chroma_location);
459 RADEON_ENC_CS(enc->enc_pic.enc_output_format.output_color_bit_depth);
460 RADEON_ENC_END();
461 }
462
radeon_enc_ref_swizzle_mode(struct radeon_encoder * enc)463 static uint32_t radeon_enc_ref_swizzle_mode(struct radeon_encoder *enc)
464 {
465 /* return RENCODE_REC_SWIZZLE_MODE_LINEAR; for debugging purpose */
466 if (enc->enc_pic.bit_depth_luma_minus8 != 0)
467 return RENCODE_REC_SWIZZLE_MODE_8x8_1D_THIN_12_24BPP;
468 else
469 return RENCODE_REC_SWIZZLE_MODE_256B_S;
470 }
471
radeon_enc_ctx(struct radeon_encoder * enc)472 static void radeon_enc_ctx(struct radeon_encoder *enc)
473 {
474 enc->enc_pic.ctx_buf.swizzle_mode = radeon_enc_ref_swizzle_mode(enc);
475 enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0;
476
477 RADEON_ENC_BEGIN(enc->cmd.ctx);
478 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
479 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
480 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
481 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
482 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
483
484 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
485 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
486 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
487 }
488
489 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_luma_pitch);
490 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_chroma_pitch);
491
492 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
493 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].luma_offset);
494 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].chroma_offset);
495 }
496
497 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.yuv.luma_offset);
498 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.yuv.chroma_offset);
499 RADEON_ENC_CS(enc->enc_pic.ctx_buf.two_pass_search_center_map_offset);
500 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.red_offset);
501 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.green_offset);
502 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.blue_offset);
503
504 RADEON_ENC_END();
505 }
encode(struct radeon_encoder * enc)506 static void encode(struct radeon_encoder *enc)
507 {
508 unsigned i;
509
510 enc->before_encode(enc);
511 enc->session_info(enc);
512 enc->total_task_size = 0;
513 enc->task_info(enc, enc->need_feedback);
514
515 if (enc->need_rate_control) {
516 i = 0;
517 do {
518 enc->enc_pic.temporal_id = i;
519 enc->layer_select(enc);
520 enc->rc_layer_init(enc);
521 } while (++i < enc->enc_pic.num_temporal_layers);
522 }
523
524 enc->encode_headers(enc);
525 enc->ctx(enc);
526 enc->bitstream(enc);
527 enc->feedback(enc);
528 enc->encode_statistics(enc);
529 enc->intra_refresh(enc);
530 enc->qp_map(enc);
531 enc->input_format(enc);
532 enc->output_format(enc);
533
534 enc->op_preset(enc);
535 enc->op_enc(enc);
536 *enc->p_task_size = (enc->total_task_size);
537 }
538
radeon_enc_2_0_init(struct radeon_encoder * enc)539 void radeon_enc_2_0_init(struct radeon_encoder *enc)
540 {
541 radeon_enc_1_2_init(enc);
542 enc->encode = encode;
543 enc->input_format = radeon_enc_input_format;
544 enc->output_format = radeon_enc_output_format;
545 enc->ctx = radeon_enc_ctx;
546 enc->op_preset = radeon_enc_op_preset;
547 enc->quality_params = radeon_enc_quality_params;
548
549 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
550 enc->deblocking_filter = radeon_enc_loop_filter_hevc;
551 enc->nalu_sps = radeon_enc_nalu_sps_hevc;
552 enc->nalu_pps = radeon_enc_nalu_pps_hevc;
553 enc->slice_header = radeon_enc_slice_header_hevc;
554 }
555
556 enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
557 enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
558 enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
559 enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
560 enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
561 enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
562 enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
563 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
564 enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
565 enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
566 enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
567 enc->cmd.input_format = RENCODE_IB_PARAM_INPUT_FORMAT;
568 enc->cmd.output_format = RENCODE_IB_PARAM_OUTPUT_FORMAT;
569 enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
570 enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
571 enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
572 enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
573 enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
574 enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
575 enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
576 enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_LOOP_FILTER;
577 enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
578 enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
579 enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
580 enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
581 enc->cmd.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
582 enc->cmd.enc_qp_map = RENCODE_IB_PARAM_QP_MAP;
583
584 enc->enc_pic.session_info.interface_version =
585 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
586 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
587 }
588