1 /**************************************************************************
2 *
3 * Copyright 2020 Advanced Micro Devices, Inc.
4 *
5 * SPDX-License-Identifier: MIT
6 *
7 **************************************************************************/
8
9 #include <stdio.h>
10
11 #include "pipe/p_video_codec.h"
12
13 #include "util/u_video.h"
14
15 #include "si_pipe.h"
16 #include "radeon_video.h"
17 #include "radeon_vcn_enc.h"
18
19 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
20 #define RENCODE_FW_INTERFACE_MINOR_VERSION 20
21
radeon_enc_session_info(struct radeon_encoder * enc)22 static void radeon_enc_session_info(struct radeon_encoder *enc)
23 {
24 RADEON_ENC_BEGIN(enc->cmd.session_info);
25 RADEON_ENC_CS(enc->enc_pic.session_info.interface_version);
26 RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
27 RADEON_ENC_CS(0); /* padding 0, not used for vcn3 */
28 RADEON_ENC_END();
29 }
30
radeon_enc_spec_misc(struct radeon_encoder * enc)31 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
32 {
33 enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
34 enc->enc_pic.spec_misc.half_pel_enabled = 1;
35 enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
36 enc->enc_pic.spec_misc.level_idc = enc->base.level;
37 enc->enc_pic.spec_misc.weighted_bipred_idc = 0;
38
39 RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
40 RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
41 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
42 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
43 RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
44 RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
45 RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
46 RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
47 RADEON_ENC_CS(enc->enc_pic.spec_misc.b_picture_enabled);
48 RADEON_ENC_CS(enc->enc_pic.spec_misc.weighted_bipred_idc);
49 RADEON_ENC_END();
50 }
51
radeon_enc_spec_misc_hevc(struct radeon_encoder * enc)52 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc)
53 {
54 enc->enc_pic.hevc_spec_misc.transform_skip_discarded = 0;
55 enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag = 0;
56
57 RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc);
58 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
59 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
60 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
61 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
62 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
63 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
64 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
65 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.transform_skip_discarded);
66 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cu_qp_delta_enabled_flag);
67 RADEON_ENC_END();
68 }
69
radeon_enc_encode_params_h264(struct radeon_encoder * enc)70 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
71 {
72 enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
73 enc->enc_pic.h264_enc_params.input_pic_order_cnt = 0;
74 enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
75 enc->enc_pic.h264_enc_params.l0_reference_picture1_index = 0xFFFFFFFF;
76
77 RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
78 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
79 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_pic_order_cnt);
80 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
81 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_type);
82 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.is_long_term);
83 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.picture_structure);
84 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_order_cnt);
85 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l0_reference_picture1_index);
86 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_type);
87 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.is_long_term);
88 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.picture_structure);
89 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_order_cnt);
90 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l1_reference_picture0_index);
91 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_type);
92 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.is_long_term);
93 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.picture_structure);
94 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_order_cnt);
95 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.is_reference);
96 RADEON_ENC_END();
97 }
98
radeon_enc_quality_params(struct radeon_encoder * enc)99 static void radeon_enc_quality_params(struct radeon_encoder *enc)
100 {
101 enc->enc_pic.quality_params.vbaq_mode = enc->enc_pic.quality_modes.vbaq_mode;
102 enc->enc_pic.quality_params.scene_change_sensitivity = 0;
103 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
104 enc->enc_pic.quality_params.two_pass_search_center_map_mode =
105 (enc->enc_pic.quality_modes.pre_encode_mode &&
106 !enc->enc_pic.spec_misc.b_picture_enabled) ? 1 : 0;
107 enc->enc_pic.quality_params.vbaq_strength = 0;
108
109 RADEON_ENC_BEGIN(enc->cmd.quality_params);
110 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
111 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
112 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
113 RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
114 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_strength);
115 RADEON_ENC_END();
116 }
117
radeon_enc_nalu_sps(struct radeon_encoder * enc)118 static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
119 {
120 struct radeon_enc_pic *pic = &enc->enc_pic;
121 RADEON_ENC_BEGIN(enc->cmd.nalu);
122 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
123 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
124 radeon_enc_reset(enc);
125 radeon_enc_set_emulation_prevention(enc, false);
126 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
127 radeon_enc_code_fixed_bits(enc, 0x67, 8);
128 radeon_enc_byte_align(enc);
129 radeon_enc_set_emulation_prevention(enc, true);
130 radeon_enc_code_fixed_bits(enc, pic->spec_misc.profile_idc, 8);
131 radeon_enc_code_fixed_bits(enc, 0x0, 8); /* constraint_set_flags */
132 radeon_enc_code_fixed_bits(enc, pic->spec_misc.level_idc, 8);
133 radeon_enc_code_ue(enc, 0x0);
134
135 if (pic->spec_misc.profile_idc == 100 || pic->spec_misc.profile_idc == 110 ||
136 pic->spec_misc.profile_idc == 122 || pic->spec_misc.profile_idc == 244 ||
137 pic->spec_misc.profile_idc == 44 || pic->spec_misc.profile_idc == 83 ||
138 pic->spec_misc.profile_idc == 86 || pic->spec_misc.profile_idc == 118 ||
139 pic->spec_misc.profile_idc == 128 || pic->spec_misc.profile_idc == 138) {
140 radeon_enc_code_ue(enc, 0x1);
141 radeon_enc_code_ue(enc, 0x0);
142 radeon_enc_code_ue(enc, 0x0);
143 radeon_enc_code_fixed_bits(enc, 0x0, 2);
144 }
145
146 radeon_enc_code_ue(enc, 1);
147 radeon_enc_code_ue(enc, pic->pic_order_cnt_type);
148
149 if (pic->pic_order_cnt_type == 0)
150 radeon_enc_code_ue(enc, 1);
151
152 radeon_enc_code_ue(enc, enc->base.max_references);
153 radeon_enc_code_fixed_bits(enc, pic->layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0,
154 1);
155 radeon_enc_code_ue(enc, (pic->session_init.aligned_picture_width / 16 - 1));
156 radeon_enc_code_ue(enc, (pic->session_init.aligned_picture_height / 16 - 1));
157 bool progressive_only = true;
158 radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
159
160 if (!progressive_only)
161 radeon_enc_code_fixed_bits(enc, 0x0, 1);
162
163 radeon_enc_code_fixed_bits(enc, 0x1, 1);
164
165 if ((pic->crop_left != 0) || (pic->crop_right != 0) ||
166 (pic->crop_top != 0) || (pic->crop_bottom != 0)) {
167 radeon_enc_code_fixed_bits(enc, 0x1, 1);
168 radeon_enc_code_ue(enc, pic->crop_left);
169 radeon_enc_code_ue(enc, pic->crop_right);
170 radeon_enc_code_ue(enc, pic->crop_top);
171 radeon_enc_code_ue(enc, pic->crop_bottom);
172 } else
173 radeon_enc_code_fixed_bits(enc, 0x0, 1);
174
175 /* VUI present flag */
176 radeon_enc_code_fixed_bits(enc, pic->vui_info.vui_parameters_present_flag, 1);
177 if (pic->vui_info.vui_parameters_present_flag) {
178 /* aspect ratio present flag */
179 radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.aspect_ratio_info_present_flag), 1);
180 if (pic->vui_info.flags.aspect_ratio_info_present_flag) {
181 radeon_enc_code_fixed_bits(enc, (pic->vui_info.aspect_ratio_idc), 8);
182 if (pic->vui_info.aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
183 radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_width), 16);
184 radeon_enc_code_fixed_bits(enc, (pic->vui_info.sar_height), 16);
185 }
186 }
187 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* overscan info present flag */
188 /* video signal type present flag */
189 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.video_signal_type_present_flag, 1);
190 if (pic->vui_info.flags.video_signal_type_present_flag) {
191 radeon_enc_code_fixed_bits(enc, pic->vui_info.video_format, 3);
192 radeon_enc_code_fixed_bits(enc, pic->vui_info.video_full_range_flag, 1);
193 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.colour_description_present_flag, 1);
194 if (pic->vui_info.flags.colour_description_present_flag) {
195 radeon_enc_code_fixed_bits(enc, pic->vui_info.colour_primaries, 8);
196 radeon_enc_code_fixed_bits(enc, pic->vui_info.transfer_characteristics, 8);
197 radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
198 }
199 }
200 /* chroma loc info present flag */
201 radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
202 if (pic->vui_info.flags.chroma_loc_info_present_flag) {
203 radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
204 radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
205 }
206 /* timing info present flag */
207 radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.timing_info_present_flag), 1);
208 if (pic->vui_info.flags.timing_info_present_flag) {
209 radeon_enc_code_fixed_bits(enc, (pic->vui_info.num_units_in_tick), 32);
210 radeon_enc_code_fixed_bits(enc, (pic->vui_info.time_scale), 32);
211 radeon_enc_code_fixed_bits(enc, 0x0, 1);
212 }
213 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* nal hrd parameters present flag */
214 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* vcl hrd parameters present flag */
215 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* pic_struct_present flag */
216 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* bitstream_restriction_flag */
217 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* motion_vectors_over_pic_boundaries_flag */
218 radeon_enc_code_ue(enc, 0x0);
219 radeon_enc_code_ue(enc, 0x0);
220 radeon_enc_code_ue(enc, 16);
221 radeon_enc_code_ue(enc, 16);
222 radeon_enc_code_ue(enc, pic->vui_info.max_num_reorder_frames);
223 radeon_enc_code_ue(enc, enc->base.max_references); /* max_dec_frame_buffering */
224 }
225 radeon_enc_code_fixed_bits(enc, 0x1, 1);
226
227 radeon_enc_byte_align(enc);
228 radeon_enc_flush_headers(enc);
229 *size_in_bytes = (enc->bits_output + 7) / 8;
230 RADEON_ENC_END();
231 }
232
radeon_enc_slice_header(struct radeon_encoder * enc)233 static void radeon_enc_slice_header(struct radeon_encoder *enc)
234 {
235 uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
236 uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
237 unsigned int inst_index = 0;
238 unsigned int cdw_start = 0;
239 unsigned int cdw_filled = 0;
240 unsigned int bits_copied = 0;
241 RADEON_ENC_BEGIN(enc->cmd.slice_header);
242 radeon_enc_reset(enc);
243 radeon_enc_set_emulation_prevention(enc, false);
244
245 cdw_start = enc->cs.current.cdw;
246 if (enc->enc_pic.is_idr)
247 radeon_enc_code_fixed_bits(enc, 0x65, 8);
248 else if (enc->enc_pic.not_referenced)
249 radeon_enc_code_fixed_bits(enc, 0x01, 8);
250 else
251 radeon_enc_code_fixed_bits(enc, 0x41, 8);
252
253 radeon_enc_flush_headers(enc);
254 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
255 num_bits[inst_index] = enc->bits_output - bits_copied;
256 bits_copied = enc->bits_output;
257 inst_index++;
258
259 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
260 inst_index++;
261
262 switch (enc->enc_pic.picture_type) {
263 case PIPE_H2645_ENC_PICTURE_TYPE_I:
264 case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
265 radeon_enc_code_fixed_bits(enc, 0x08, 7);
266 break;
267 case PIPE_H2645_ENC_PICTURE_TYPE_P:
268 case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
269 radeon_enc_code_fixed_bits(enc, 0x06, 5);
270 break;
271 case PIPE_H2645_ENC_PICTURE_TYPE_B:
272 radeon_enc_code_fixed_bits(enc, 0x07, 5);
273 break;
274 default:
275 radeon_enc_code_fixed_bits(enc, 0x08, 7);
276 }
277
278 radeon_enc_code_ue(enc, 0x0);
279 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
280
281 if (enc->enc_pic.h264_enc_params.input_picture_structure !=
282 RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
283 radeon_enc_code_fixed_bits(enc, 0x1, 1);
284 radeon_enc_code_fixed_bits(enc,
285 enc->enc_pic.h264_enc_params.input_picture_structure ==
286 RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
287 ? 1
288 : 0,
289 1);
290 }
291
292 if (enc->enc_pic.is_idr)
293 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
294
295 enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
296
297 if (enc->enc_pic.pic_order_cnt_type == 0)
298 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
299
300 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)
301 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* direct_spatial_mv_pred_flag */
302
303 /* ref_pic_list_modification() */
304 if (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR &&
305 enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_I) {
306 radeon_enc_code_fixed_bits(enc, 0x0, 1);
307
308 /* long-term reference */
309 if (enc->enc_pic.ref_idx_l0_is_ltr) {
310 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* ref_pic_list_modification_flag_l0 */
311 radeon_enc_code_ue(enc, 0x2); /* modification_of_pic_nums_idc */
312 radeon_enc_code_ue(enc, enc->enc_pic.ref_idx_l0); /* long_term_pic_num */
313 radeon_enc_code_ue(enc, 0x3);
314 }
315
316 /* short-term reference */
317 else if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B) {
318 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* ref_pic_list_modification_flag_l0 */
319 radeon_enc_code_fixed_bits(enc, 0x0, 1); /* ref_pic_list_modification_flag_l1 */
320 }
321 /* list_mod_diff_pic_minus1 != 0 */
322 else if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
323 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* ref_pic_list_modification_flag_l0 */
324 radeon_enc_code_ue(enc, 0x0); /* modification_of_pic_nums_idc */
325 /* abs_diff_pic_num_minus1 */
326 radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
327 radeon_enc_code_ue(enc, 0x3);
328 } else
329 radeon_enc_code_fixed_bits(enc, 0x0, 1);
330 }
331
332 if (enc->enc_pic.is_idr) {
333 radeon_enc_code_fixed_bits(enc, 0x0, 1);
334 if (enc->enc_pic.is_ltr)
335 radeon_enc_code_fixed_bits(enc, 0x1, 1); /* long_term_reference_flag */
336 else
337 radeon_enc_code_fixed_bits(enc, 0x0, 1);
338 } else if (!enc->enc_pic.not_referenced) {
339 if (enc->enc_pic.is_ltr) {
340 radeon_enc_code_fixed_bits(enc, 0x1, 1);
341 radeon_enc_code_ue(enc, 0x4); /* memory_management_control_operation */
342 radeon_enc_code_ue(enc, enc->max_ltr_idx + 1); /* max_long_term_frame_idx_plus1 */
343 radeon_enc_code_ue(enc, 0x6); /*memory_management_control_operation */
344 radeon_enc_code_ue(enc, enc->enc_pic.ltr_idx); /* long_term_frame_idx */
345 radeon_enc_code_ue(enc, 0x0); /*memory_management_control_operation end*/
346 } else
347 radeon_enc_code_fixed_bits(enc, 0x0, 1);
348 }
349
350 if ((enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) &&
351 (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_I) &&
352 (enc->enc_pic.spec_misc.cabac_enable))
353 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
354
355 radeon_enc_flush_headers(enc);
356 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
357 num_bits[inst_index] = enc->bits_output - bits_copied;
358 bits_copied = enc->bits_output;
359 inst_index++;
360
361 instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
362 inst_index++;
363
364 if (enc->enc_pic.spec_misc.deblocking_filter_control_present_flag) {
365 radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
366 if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
367 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
368 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
369 }
370 }
371
372 radeon_enc_flush_headers(enc);
373 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
374 num_bits[inst_index] = enc->bits_output - bits_copied;
375 bits_copied = enc->bits_output;
376 inst_index++;
377
378 instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
379
380 cdw_filled = enc->cs.current.cdw - cdw_start;
381 for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
382 RADEON_ENC_CS(0x00000000);
383
384 for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
385 RADEON_ENC_CS(instruction[j]);
386 RADEON_ENC_CS(num_bits[j]);
387 }
388
389 RADEON_ENC_END();
390 }
391
radeon_enc_nalu_pps_hevc(struct radeon_encoder * enc)392 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
393 {
394 uint32_t *size_in_bytes;
395
396 RADEON_ENC_BEGIN(enc->cmd.nalu);
397 RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
398 size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
399
400 radeon_enc_reset(enc);
401 radeon_enc_set_emulation_prevention(enc, false);
402 radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
403 radeon_enc_code_fixed_bits(enc, 0x4401, 16);
404 radeon_enc_byte_align(enc);
405 radeon_enc_set_emulation_prevention(enc, true);
406 radeon_enc_code_ue(enc, 0x0);
407 radeon_enc_code_ue(enc, 0x0);
408 radeon_enc_code_fixed_bits(enc, 0x1, 1);
409 radeon_enc_code_fixed_bits(enc, 0x0, 4);
410 radeon_enc_code_fixed_bits(enc, 0x0, 1);
411 radeon_enc_code_fixed_bits(enc, 0x1, 1);
412 radeon_enc_code_ue(enc, 0x0);
413 radeon_enc_code_ue(enc, 0x0);
414 radeon_enc_code_se(enc, 0x0);
415 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
416 radeon_enc_code_fixed_bits(enc, 0x1, 1);
417 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE &&
418 enc->enc_pic.enc_qp_map.qp_map_type == RENCODE_QP_MAP_TYPE_NONE)
419 radeon_enc_code_fixed_bits(enc, 0x0, 1);
420 else {
421 radeon_enc_code_fixed_bits(enc, 0x1, 1);
422 radeon_enc_code_ue(enc, 0x0);
423 }
424 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
425 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
426 radeon_enc_code_fixed_bits(enc, 0x0, 1);
427 radeon_enc_code_fixed_bits(enc, 0x0, 2);
428 radeon_enc_code_fixed_bits(enc, 0x0, 1);
429 radeon_enc_code_fixed_bits(enc, 0x0, 1);
430 radeon_enc_code_fixed_bits(enc, 0x0, 1);
431 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
432 radeon_enc_code_fixed_bits(enc, 0x1, 1);
433 radeon_enc_code_fixed_bits(enc, 0x0, 1);
434 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
435
436 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
437 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
438 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
439 }
440
441 radeon_enc_code_fixed_bits(enc, 0x0, 1);
442 radeon_enc_code_fixed_bits(enc, 0x0, 1);
443 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
444 radeon_enc_code_fixed_bits(enc, 0x0, 2);
445
446 radeon_enc_code_fixed_bits(enc, 0x1, 1);
447
448 radeon_enc_byte_align(enc);
449 radeon_enc_flush_headers(enc);
450 *size_in_bytes = (enc->bits_output + 7) / 8;
451 RADEON_ENC_END();
452 }
453
radeon_enc_ref_swizzle_mode(struct radeon_encoder * enc)454 static uint32_t radeon_enc_ref_swizzle_mode(struct radeon_encoder *enc)
455 {
456 /* return RENCODE_REC_SWIZZLE_MODE_LINEAR; for debugging purpose */
457 if (enc->enc_pic.bit_depth_luma_minus8 != 0)
458 return RENCODE_REC_SWIZZLE_MODE_8x8_1D_THIN_12_24BPP;
459 else
460 return RENCODE_REC_SWIZZLE_MODE_256B_S;
461 }
462
radeon_enc_ctx(struct radeon_encoder * enc)463 static void radeon_enc_ctx(struct radeon_encoder *enc)
464 {
465 enc->enc_pic.ctx_buf.swizzle_mode = radeon_enc_ref_swizzle_mode(enc);
466 enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0;
467
468 RADEON_ENC_BEGIN(enc->cmd.ctx);
469 RADEON_ENC_READWRITE(enc->dpb->res->buf, enc->dpb->res->domains, 0);
470 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
471 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
472 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
473 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
474
475 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
476 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
477 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
478 }
479
480 RADEON_ENC_CS(enc->enc_pic.ctx_buf.colloc_buffer_offset);
481 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_luma_pitch);
482 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_picture_chroma_pitch);
483
484 for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
485 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].luma_offset);
486 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_reconstructed_pictures[i].chroma_offset);
487 }
488
489 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.red_offset);
490 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.green_offset);
491 RADEON_ENC_CS(enc->enc_pic.ctx_buf.pre_encode_input_picture.rgb.blue_offset);
492
493 RADEON_ENC_CS(enc->enc_pic.ctx_buf.two_pass_search_center_map_offset);
494 RADEON_ENC_CS(0x00000000);
495 RADEON_ENC_CS(0x00000000);
496 RADEON_ENC_END();
497 }
498
radeon_enc_session_init(struct radeon_encoder * enc)499 static void radeon_enc_session_init(struct radeon_encoder *enc)
500 {
501 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
502 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
503 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
504 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
505 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
506 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
507 }
508 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
509 enc->enc_pic.session_init.padding_width =
510 enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
511 enc->enc_pic.session_init.padding_height =
512 enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
513 enc->enc_pic.session_init.slice_output_enabled = 0;
514 enc->enc_pic.session_init.display_remote = 0;
515 enc->enc_pic.session_init.pre_encode_mode = enc->enc_pic.quality_modes.pre_encode_mode;
516 enc->enc_pic.session_init.pre_encode_chroma_enabled = !!(enc->enc_pic.quality_modes.pre_encode_mode);
517
518 RADEON_ENC_BEGIN(enc->cmd.session_init);
519 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
520 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
521 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
522 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
523 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
524 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
525 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
526 RADEON_ENC_CS(enc->enc_pic.session_init.slice_output_enabled);
527 RADEON_ENC_CS(enc->enc_pic.session_init.display_remote);
528 RADEON_ENC_END();
529 }
530
radeon_enc_3_0_init(struct radeon_encoder * enc)531 void radeon_enc_3_0_init(struct radeon_encoder *enc)
532 {
533 radeon_enc_2_0_init(enc);
534
535 enc->session_info = radeon_enc_session_info;
536 enc->session_init = radeon_enc_session_init;
537 enc->ctx = radeon_enc_ctx;
538 enc->quality_params = radeon_enc_quality_params;
539
540 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
541 enc->spec_misc = radeon_enc_spec_misc;
542 enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
543 enc->nalu_sps = radeon_enc_nalu_sps;
544 enc->slice_header = radeon_enc_slice_header;
545 }
546
547 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
548 enc->spec_misc = radeon_enc_spec_misc_hevc;
549 enc->nalu_pps = radeon_enc_nalu_pps_hevc;
550 }
551
552 enc->enc_pic.session_info.interface_version =
553 ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
554 (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
555 }
556